d1_pac/ccu/
tpadc_clk.rs

1#[doc = "Register `tpadc_clk` reader"]
2pub type R = crate::R<TPADC_CLK_SPEC>;
3#[doc = "Register `tpadc_clk` writer"]
4pub type W = crate::W<TPADC_CLK_SPEC>;
5#[doc = "Field `clk_src_sel` reader - Clock Source Select"]
6pub type CLK_SRC_SEL_R = crate::FieldReader<CLK_SRC_SEL_A>;
7#[doc = "Clock Source Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum CLK_SRC_SEL_A {
11    #[doc = "0: `0`"]
12    HOSC = 0,
13    #[doc = "1: `1`"]
14    PLL_AUDIO0_1X = 1,
15}
16impl From<CLK_SRC_SEL_A> for u8 {
17    #[inline(always)]
18    fn from(variant: CLK_SRC_SEL_A) -> Self {
19        variant as _
20    }
21}
22impl crate::FieldSpec for CLK_SRC_SEL_A {
23    type Ux = u8;
24}
25impl CLK_SRC_SEL_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> Option<CLK_SRC_SEL_A> {
29        match self.bits {
30            0 => Some(CLK_SRC_SEL_A::HOSC),
31            1 => Some(CLK_SRC_SEL_A::PLL_AUDIO0_1X),
32            _ => None,
33        }
34    }
35    #[doc = "`0`"]
36    #[inline(always)]
37    pub fn is_hosc(&self) -> bool {
38        *self == CLK_SRC_SEL_A::HOSC
39    }
40    #[doc = "`1`"]
41    #[inline(always)]
42    pub fn is_pll_audio0_1x(&self) -> bool {
43        *self == CLK_SRC_SEL_A::PLL_AUDIO0_1X
44    }
45}
46#[doc = "Field `clk_src_sel` writer - Clock Source Select"]
47pub type CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CLK_SRC_SEL_A>;
48impl<'a, REG> CLK_SRC_SEL_W<'a, REG>
49where
50    REG: crate::Writable + crate::RegisterSpec,
51    REG::Ux: From<u8>,
52{
53    #[doc = "`0`"]
54    #[inline(always)]
55    pub fn hosc(self) -> &'a mut crate::W<REG> {
56        self.variant(CLK_SRC_SEL_A::HOSC)
57    }
58    #[doc = "`1`"]
59    #[inline(always)]
60    pub fn pll_audio0_1x(self) -> &'a mut crate::W<REG> {
61        self.variant(CLK_SRC_SEL_A::PLL_AUDIO0_1X)
62    }
63}
64#[doc = "Field `clk_gating` reader - Gating Clock"]
65pub type CLK_GATING_R = crate::BitReader<CLK_GATING_A>;
66#[doc = "Gating Clock\n\nValue on reset: 0"]
67#[derive(Clone, Copy, Debug, PartialEq, Eq)]
68pub enum CLK_GATING_A {
69    #[doc = "0: `0`"]
70    OFF = 0,
71    #[doc = "1: `1`"]
72    ON = 1,
73}
74impl From<CLK_GATING_A> for bool {
75    #[inline(always)]
76    fn from(variant: CLK_GATING_A) -> Self {
77        variant as u8 != 0
78    }
79}
80impl CLK_GATING_R {
81    #[doc = "Get enumerated values variant"]
82    #[inline(always)]
83    pub const fn variant(&self) -> CLK_GATING_A {
84        match self.bits {
85            false => CLK_GATING_A::OFF,
86            true => CLK_GATING_A::ON,
87        }
88    }
89    #[doc = "`0`"]
90    #[inline(always)]
91    pub fn is_off(&self) -> bool {
92        *self == CLK_GATING_A::OFF
93    }
94    #[doc = "`1`"]
95    #[inline(always)]
96    pub fn is_on(&self) -> bool {
97        *self == CLK_GATING_A::ON
98    }
99}
100#[doc = "Field `clk_gating` writer - Gating Clock"]
101pub type CLK_GATING_W<'a, REG> = crate::BitWriter<'a, REG, CLK_GATING_A>;
102impl<'a, REG> CLK_GATING_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    #[doc = "`0`"]
107    #[inline(always)]
108    pub fn off(self) -> &'a mut crate::W<REG> {
109        self.variant(CLK_GATING_A::OFF)
110    }
111    #[doc = "`1`"]
112    #[inline(always)]
113    pub fn on(self) -> &'a mut crate::W<REG> {
114        self.variant(CLK_GATING_A::ON)
115    }
116}
117impl R {
118    #[doc = "Bits 24:26 - Clock Source Select"]
119    #[inline(always)]
120    pub fn clk_src_sel(&self) -> CLK_SRC_SEL_R {
121        CLK_SRC_SEL_R::new(((self.bits >> 24) & 7) as u8)
122    }
123    #[doc = "Bit 31 - Gating Clock"]
124    #[inline(always)]
125    pub fn clk_gating(&self) -> CLK_GATING_R {
126        CLK_GATING_R::new(((self.bits >> 31) & 1) != 0)
127    }
128}
129impl W {
130    #[doc = "Bits 24:26 - Clock Source Select"]
131    #[inline(always)]
132    #[must_use]
133    pub fn clk_src_sel(&mut self) -> CLK_SRC_SEL_W<TPADC_CLK_SPEC> {
134        CLK_SRC_SEL_W::new(self, 24)
135    }
136    #[doc = "Bit 31 - Gating Clock"]
137    #[inline(always)]
138    #[must_use]
139    pub fn clk_gating(&mut self) -> CLK_GATING_W<TPADC_CLK_SPEC> {
140        CLK_GATING_W::new(self, 31)
141    }
142    #[doc = r" Writes raw bits to the register."]
143    #[doc = r""]
144    #[doc = r" # Safety"]
145    #[doc = r""]
146    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
147    #[inline(always)]
148    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
149        self.bits = bits;
150        self
151    }
152}
153#[doc = "TPADC Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tpadc_clk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tpadc_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
154pub struct TPADC_CLK_SPEC;
155impl crate::RegisterSpec for TPADC_CLK_SPEC {
156    type Ux = u32;
157}
158#[doc = "`read()` method returns [`tpadc_clk::R`](R) reader structure"]
159impl crate::Readable for TPADC_CLK_SPEC {}
160#[doc = "`write(|w| ..)` method takes [`tpadc_clk::W`](W) writer structure"]
161impl crate::Writable for TPADC_CLK_SPEC {
162    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
163    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
164}
165#[doc = "`reset()` method sets tpadc_clk to value 0"]
166impl crate::Resettable for TPADC_CLK_SPEC {
167    const RESET_VALUE: Self::Ux = 0;
168}
d1_pac/ccu/tpadc_clk.rs

d1_pac/ccu/
tpadc_clk.rs
