d1_pac/ccu/
tcontv_clk.rs

1#[doc = "Register `tcontv_clk` reader"]
2pub type R = crate::R<TCONTV_CLK_SPEC>;
3#[doc = "Register `tcontv_clk` writer"]
4pub type W = crate::W<TCONTV_CLK_SPEC>;
5#[doc = "Field `factor_m` reader - Factor M"]
6pub type FACTOR_M_R = crate::FieldReader;
7#[doc = "Field `factor_m` writer - Factor M"]
8pub type FACTOR_M_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `factor_n` reader - Factor N"]
10pub type FACTOR_N_R = crate::FieldReader<FACTOR_N_A>;
11#[doc = "Factor N\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13#[repr(u8)]
14pub enum FACTOR_N_A {
15    #[doc = "0: `0`"]
16    N1 = 0,
17    #[doc = "1: `1`"]
18    N2 = 1,
19    #[doc = "2: `10`"]
20    N4 = 2,
21    #[doc = "3: `11`"]
22    N8 = 3,
23}
24impl From<FACTOR_N_A> for u8 {
25    #[inline(always)]
26    fn from(variant: FACTOR_N_A) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for FACTOR_N_A {
31    type Ux = u8;
32}
33impl FACTOR_N_R {
34    #[doc = "Get enumerated values variant"]
35    #[inline(always)]
36    pub const fn variant(&self) -> FACTOR_N_A {
37        match self.bits {
38            0 => FACTOR_N_A::N1,
39            1 => FACTOR_N_A::N2,
40            2 => FACTOR_N_A::N4,
41            3 => FACTOR_N_A::N8,
42            _ => unreachable!(),
43        }
44    }
45    #[doc = "`0`"]
46    #[inline(always)]
47    pub fn is_n1(&self) -> bool {
48        *self == FACTOR_N_A::N1
49    }
50    #[doc = "`1`"]
51    #[inline(always)]
52    pub fn is_n2(&self) -> bool {
53        *self == FACTOR_N_A::N2
54    }
55    #[doc = "`10`"]
56    #[inline(always)]
57    pub fn is_n4(&self) -> bool {
58        *self == FACTOR_N_A::N4
59    }
60    #[doc = "`11`"]
61    #[inline(always)]
62    pub fn is_n8(&self) -> bool {
63        *self == FACTOR_N_A::N8
64    }
65}
66#[doc = "Field `factor_n` writer - Factor N"]
67pub type FACTOR_N_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, FACTOR_N_A>;
68impl<'a, REG> FACTOR_N_W<'a, REG>
69where
70    REG: crate::Writable + crate::RegisterSpec,
71    REG::Ux: From<u8>,
72{
73    #[doc = "`0`"]
74    #[inline(always)]
75    pub fn n1(self) -> &'a mut crate::W<REG> {
76        self.variant(FACTOR_N_A::N1)
77    }
78    #[doc = "`1`"]
79    #[inline(always)]
80    pub fn n2(self) -> &'a mut crate::W<REG> {
81        self.variant(FACTOR_N_A::N2)
82    }
83    #[doc = "`10`"]
84    #[inline(always)]
85    pub fn n4(self) -> &'a mut crate::W<REG> {
86        self.variant(FACTOR_N_A::N4)
87    }
88    #[doc = "`11`"]
89    #[inline(always)]
90    pub fn n8(self) -> &'a mut crate::W<REG> {
91        self.variant(FACTOR_N_A::N8)
92    }
93}
94#[doc = "Field `clk_src_sel` reader - Clock Source Select"]
95pub type CLK_SRC_SEL_R = crate::FieldReader<CLK_SRC_SEL_A>;
96#[doc = "Clock Source Select\n\nValue on reset: 0"]
97#[derive(Clone, Copy, Debug, PartialEq, Eq)]
98#[repr(u8)]
99pub enum CLK_SRC_SEL_A {
100    #[doc = "0: `0`"]
101    PLL_VIDEO0_1X = 0,
102    #[doc = "1: `1`"]
103    PLL_VIDEO0_4X = 1,
104    #[doc = "2: `10`"]
105    PLL_VIDEO1_1X = 2,
106    #[doc = "3: `11`"]
107    PLL_VIDEO1_4X = 3,
108    #[doc = "4: `100`"]
109    PLL_PERI_2X = 4,
110    #[doc = "5: `101`"]
111    PLL_AUDIO1_DIV2 = 5,
112}
113impl From<CLK_SRC_SEL_A> for u8 {
114    #[inline(always)]
115    fn from(variant: CLK_SRC_SEL_A) -> Self {
116        variant as _
117    }
118}
119impl crate::FieldSpec for CLK_SRC_SEL_A {
120    type Ux = u8;
121}
122impl CLK_SRC_SEL_R {
123    #[doc = "Get enumerated values variant"]
124    #[inline(always)]
125    pub const fn variant(&self) -> Option<CLK_SRC_SEL_A> {
126        match self.bits {
127            0 => Some(CLK_SRC_SEL_A::PLL_VIDEO0_1X),
128            1 => Some(CLK_SRC_SEL_A::PLL_VIDEO0_4X),
129            2 => Some(CLK_SRC_SEL_A::PLL_VIDEO1_1X),
130            3 => Some(CLK_SRC_SEL_A::PLL_VIDEO1_4X),
131            4 => Some(CLK_SRC_SEL_A::PLL_PERI_2X),
132            5 => Some(CLK_SRC_SEL_A::PLL_AUDIO1_DIV2),
133            _ => None,
134        }
135    }
136    #[doc = "`0`"]
137    #[inline(always)]
138    pub fn is_pll_video0_1x(&self) -> bool {
139        *self == CLK_SRC_SEL_A::PLL_VIDEO0_1X
140    }
141    #[doc = "`1`"]
142    #[inline(always)]
143    pub fn is_pll_video0_4x(&self) -> bool {
144        *self == CLK_SRC_SEL_A::PLL_VIDEO0_4X
145    }
146    #[doc = "`10`"]
147    #[inline(always)]
148    pub fn is_pll_video1_1x(&self) -> bool {
149        *self == CLK_SRC_SEL_A::PLL_VIDEO1_1X
150    }
151    #[doc = "`11`"]
152    #[inline(always)]
153    pub fn is_pll_video1_4x(&self) -> bool {
154        *self == CLK_SRC_SEL_A::PLL_VIDEO1_4X
155    }
156    #[doc = "`100`"]
157    #[inline(always)]
158    pub fn is_pll_peri_2x(&self) -> bool {
159        *self == CLK_SRC_SEL_A::PLL_PERI_2X
160    }
161    #[doc = "`101`"]
162    #[inline(always)]
163    pub fn is_pll_audio1_div2(&self) -> bool {
164        *self == CLK_SRC_SEL_A::PLL_AUDIO1_DIV2
165    }
166}
167#[doc = "Field `clk_src_sel` writer - Clock Source Select"]
168pub type CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CLK_SRC_SEL_A>;
169impl<'a, REG> CLK_SRC_SEL_W<'a, REG>
170where
171    REG: crate::Writable + crate::RegisterSpec,
172    REG::Ux: From<u8>,
173{
174    #[doc = "`0`"]
175    #[inline(always)]
176    pub fn pll_video0_1x(self) -> &'a mut crate::W<REG> {
177        self.variant(CLK_SRC_SEL_A::PLL_VIDEO0_1X)
178    }
179    #[doc = "`1`"]
180    #[inline(always)]
181    pub fn pll_video0_4x(self) -> &'a mut crate::W<REG> {
182        self.variant(CLK_SRC_SEL_A::PLL_VIDEO0_4X)
183    }
184    #[doc = "`10`"]
185    #[inline(always)]
186    pub fn pll_video1_1x(self) -> &'a mut crate::W<REG> {
187        self.variant(CLK_SRC_SEL_A::PLL_VIDEO1_1X)
188    }
189    #[doc = "`11`"]
190    #[inline(always)]
191    pub fn pll_video1_4x(self) -> &'a mut crate::W<REG> {
192        self.variant(CLK_SRC_SEL_A::PLL_VIDEO1_4X)
193    }
194    #[doc = "`100`"]
195    #[inline(always)]
196    pub fn pll_peri_2x(self) -> &'a mut crate::W<REG> {
197        self.variant(CLK_SRC_SEL_A::PLL_PERI_2X)
198    }
199    #[doc = "`101`"]
200    #[inline(always)]
201    pub fn pll_audio1_div2(self) -> &'a mut crate::W<REG> {
202        self.variant(CLK_SRC_SEL_A::PLL_AUDIO1_DIV2)
203    }
204}
205#[doc = "Field `clk_gating` reader - Gating Clock"]
206pub type CLK_GATING_R = crate::BitReader<CLK_GATING_A>;
207#[doc = "Gating Clock\n\nValue on reset: 0"]
208#[derive(Clone, Copy, Debug, PartialEq, Eq)]
209pub enum CLK_GATING_A {
210    #[doc = "0: `0`"]
211    OFF = 0,
212    #[doc = "1: `1`"]
213    ON = 1,
214}
215impl From<CLK_GATING_A> for bool {
216    #[inline(always)]
217    fn from(variant: CLK_GATING_A) -> Self {
218        variant as u8 != 0
219    }
220}
221impl CLK_GATING_R {
222    #[doc = "Get enumerated values variant"]
223    #[inline(always)]
224    pub const fn variant(&self) -> CLK_GATING_A {
225        match self.bits {
226            false => CLK_GATING_A::OFF,
227            true => CLK_GATING_A::ON,
228        }
229    }
230    #[doc = "`0`"]
231    #[inline(always)]
232    pub fn is_off(&self) -> bool {
233        *self == CLK_GATING_A::OFF
234    }
235    #[doc = "`1`"]
236    #[inline(always)]
237    pub fn is_on(&self) -> bool {
238        *self == CLK_GATING_A::ON
239    }
240}
241#[doc = "Field `clk_gating` writer - Gating Clock"]
242pub type CLK_GATING_W<'a, REG> = crate::BitWriter<'a, REG, CLK_GATING_A>;
243impl<'a, REG> CLK_GATING_W<'a, REG>
244where
245    REG: crate::Writable + crate::RegisterSpec,
246{
247    #[doc = "`0`"]
248    #[inline(always)]
249    pub fn off(self) -> &'a mut crate::W<REG> {
250        self.variant(CLK_GATING_A::OFF)
251    }
252    #[doc = "`1`"]
253    #[inline(always)]
254    pub fn on(self) -> &'a mut crate::W<REG> {
255        self.variant(CLK_GATING_A::ON)
256    }
257}
258impl R {
259    #[doc = "Bits 0:3 - Factor M"]
260    #[inline(always)]
261    pub fn factor_m(&self) -> FACTOR_M_R {
262        FACTOR_M_R::new((self.bits & 0x0f) as u8)
263    }
264    #[doc = "Bits 8:9 - Factor N"]
265    #[inline(always)]
266    pub fn factor_n(&self) -> FACTOR_N_R {
267        FACTOR_N_R::new(((self.bits >> 8) & 3) as u8)
268    }
269    #[doc = "Bits 24:26 - Clock Source Select"]
270    #[inline(always)]
271    pub fn clk_src_sel(&self) -> CLK_SRC_SEL_R {
272        CLK_SRC_SEL_R::new(((self.bits >> 24) & 7) as u8)
273    }
274    #[doc = "Bit 31 - Gating Clock"]
275    #[inline(always)]
276    pub fn clk_gating(&self) -> CLK_GATING_R {
277        CLK_GATING_R::new(((self.bits >> 31) & 1) != 0)
278    }
279}
280impl W {
281    #[doc = "Bits 0:3 - Factor M"]
282    #[inline(always)]
283    #[must_use]
284    pub fn factor_m(&mut self) -> FACTOR_M_W<TCONTV_CLK_SPEC> {
285        FACTOR_M_W::new(self, 0)
286    }
287    #[doc = "Bits 8:9 - Factor N"]
288    #[inline(always)]
289    #[must_use]
290    pub fn factor_n(&mut self) -> FACTOR_N_W<TCONTV_CLK_SPEC> {
291        FACTOR_N_W::new(self, 8)
292    }
293    #[doc = "Bits 24:26 - Clock Source Select"]
294    #[inline(always)]
295    #[must_use]
296    pub fn clk_src_sel(&mut self) -> CLK_SRC_SEL_W<TCONTV_CLK_SPEC> {
297        CLK_SRC_SEL_W::new(self, 24)
298    }
299    #[doc = "Bit 31 - Gating Clock"]
300    #[inline(always)]
301    #[must_use]
302    pub fn clk_gating(&mut self) -> CLK_GATING_W<TCONTV_CLK_SPEC> {
303        CLK_GATING_W::new(self, 31)
304    }
305    #[doc = r" Writes raw bits to the register."]
306    #[doc = r""]
307    #[doc = r" # Safety"]
308    #[doc = r""]
309    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
310    #[inline(always)]
311    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
312        self.bits = bits;
313        self
314    }
315}
316#[doc = "TCONTV Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcontv_clk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcontv_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
317pub struct TCONTV_CLK_SPEC;
318impl crate::RegisterSpec for TCONTV_CLK_SPEC {
319    type Ux = u32;
320}
321#[doc = "`read()` method returns [`tcontv_clk::R`](R) reader structure"]
322impl crate::Readable for TCONTV_CLK_SPEC {}
323#[doc = "`write(|w| ..)` method takes [`tcontv_clk::W`](W) writer structure"]
324impl crate::Writable for TCONTV_CLK_SPEC {
325    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
326    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
327}
328#[doc = "`reset()` method sets tcontv_clk to value 0"]
329impl crate::Resettable for TCONTV_CLK_SPEC {
330    const RESET_VALUE: Self::Ux = 0;
331}
d1_pac/ccu/tcontv_clk.rs

d1_pac/ccu/
tcontv_clk.rs
