d1_pac/ccu/
spi_bgr.rs

1#[doc = "Register `spi_bgr` reader"]
2pub type R = crate::R<SPI_BGR_SPEC>;
3#[doc = "Register `spi_bgr` writer"]
4pub type W = crate::W<SPI_BGR_SPEC>;
5#[doc = "Field `spi_gating[0-1]` reader - Gating Clock"]
6pub type SPI_GATING_R = crate::BitReader<SPI_GATING_A>;
7#[doc = "Gating Clock\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum SPI_GATING_A {
10    #[doc = "0: `0`"]
11    MASK = 0,
12    #[doc = "1: `1`"]
13    PASS = 1,
14}
15impl From<SPI_GATING_A> for bool {
16    #[inline(always)]
17    fn from(variant: SPI_GATING_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl SPI_GATING_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> SPI_GATING_A {
25        match self.bits {
26            false => SPI_GATING_A::MASK,
27            true => SPI_GATING_A::PASS,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_mask(&self) -> bool {
33        *self == SPI_GATING_A::MASK
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_pass(&self) -> bool {
38        *self == SPI_GATING_A::PASS
39    }
40}
41#[doc = "Field `spi_gating[0-1]` writer - Gating Clock"]
42pub type SPI_GATING_W<'a, REG> = crate::BitWriter<'a, REG, SPI_GATING_A>;
43impl<'a, REG> SPI_GATING_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn mask(self) -> &'a mut crate::W<REG> {
50        self.variant(SPI_GATING_A::MASK)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn pass(self) -> &'a mut crate::W<REG> {
55        self.variant(SPI_GATING_A::PASS)
56    }
57}
58#[doc = "Field `spi_rst[0-1]` reader - Reset"]
59pub type SPI_RST_R = crate::BitReader<SPI_RST_A>;
60#[doc = "Reset\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum SPI_RST_A {
63    #[doc = "0: `0`"]
64    ASSERT = 0,
65    #[doc = "1: `1`"]
66    DEASSERT = 1,
67}
68impl From<SPI_RST_A> for bool {
69    #[inline(always)]
70    fn from(variant: SPI_RST_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl SPI_RST_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> SPI_RST_A {
78        match self.bits {
79            false => SPI_RST_A::ASSERT,
80            true => SPI_RST_A::DEASSERT,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_assert(&self) -> bool {
86        *self == SPI_RST_A::ASSERT
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_deassert(&self) -> bool {
91        *self == SPI_RST_A::DEASSERT
92    }
93}
94#[doc = "Field `spi_rst[0-1]` writer - Reset"]
95pub type SPI_RST_W<'a, REG> = crate::BitWriter<'a, REG, SPI_RST_A>;
96impl<'a, REG> SPI_RST_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn assert(self) -> &'a mut crate::W<REG> {
103        self.variant(SPI_RST_A::ASSERT)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn deassert(self) -> &'a mut crate::W<REG> {
108        self.variant(SPI_RST_A::DEASSERT)
109    }
110}
111impl R {
112    #[doc = "Gating Clock\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `spi0_gating` field"]
113    #[inline(always)]
114    pub fn spi_gating(&self, n: u8) -> SPI_GATING_R {
115        #[allow(clippy::no_effect)]
116        [(); 2][n as usize];
117        SPI_GATING_R::new(((self.bits >> n) & 1) != 0)
118    }
119    #[doc = "Bit 0 - Gating Clock"]
120    #[inline(always)]
121    pub fn spi0_gating(&self) -> SPI_GATING_R {
122        SPI_GATING_R::new((self.bits & 1) != 0)
123    }
124    #[doc = "Bit 1 - Gating Clock"]
125    #[inline(always)]
126    pub fn spi1_gating(&self) -> SPI_GATING_R {
127        SPI_GATING_R::new(((self.bits >> 1) & 1) != 0)
128    }
129    #[doc = "Reset\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `spi0_rst` field"]
130    #[inline(always)]
131    pub fn spi_rst(&self, n: u8) -> SPI_RST_R {
132        #[allow(clippy::no_effect)]
133        [(); 2][n as usize];
134        SPI_RST_R::new(((self.bits >> (n + 16)) & 1) != 0)
135    }
136    #[doc = "Bit 16 - Reset"]
137    #[inline(always)]
138    pub fn spi0_rst(&self) -> SPI_RST_R {
139        SPI_RST_R::new(((self.bits >> 16) & 1) != 0)
140    }
141    #[doc = "Bit 17 - Reset"]
142    #[inline(always)]
143    pub fn spi1_rst(&self) -> SPI_RST_R {
144        SPI_RST_R::new(((self.bits >> 17) & 1) != 0)
145    }
146}
147impl W {
148    #[doc = "Gating Clock\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `spi0_gating` field"]
149    #[inline(always)]
150    #[must_use]
151    pub fn spi_gating(&mut self, n: u8) -> SPI_GATING_W<SPI_BGR_SPEC> {
152        #[allow(clippy::no_effect)]
153        [(); 2][n as usize];
154        SPI_GATING_W::new(self, n)
155    }
156    #[doc = "Bit 0 - Gating Clock"]
157    #[inline(always)]
158    #[must_use]
159    pub fn spi0_gating(&mut self) -> SPI_GATING_W<SPI_BGR_SPEC> {
160        SPI_GATING_W::new(self, 0)
161    }
162    #[doc = "Bit 1 - Gating Clock"]
163    #[inline(always)]
164    #[must_use]
165    pub fn spi1_gating(&mut self) -> SPI_GATING_W<SPI_BGR_SPEC> {
166        SPI_GATING_W::new(self, 1)
167    }
168    #[doc = "Reset\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `spi0_rst` field"]
169    #[inline(always)]
170    #[must_use]
171    pub fn spi_rst(&mut self, n: u8) -> SPI_RST_W<SPI_BGR_SPEC> {
172        #[allow(clippy::no_effect)]
173        [(); 2][n as usize];
174        SPI_RST_W::new(self, n + 16)
175    }
176    #[doc = "Bit 16 - Reset"]
177    #[inline(always)]
178    #[must_use]
179    pub fn spi0_rst(&mut self) -> SPI_RST_W<SPI_BGR_SPEC> {
180        SPI_RST_W::new(self, 16)
181    }
182    #[doc = "Bit 17 - Reset"]
183    #[inline(always)]
184    #[must_use]
185    pub fn spi1_rst(&mut self) -> SPI_RST_W<SPI_BGR_SPEC> {
186        SPI_RST_W::new(self, 17)
187    }
188    #[doc = r" Writes raw bits to the register."]
189    #[doc = r""]
190    #[doc = r" # Safety"]
191    #[doc = r""]
192    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
193    #[inline(always)]
194    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
195        self.bits = bits;
196        self
197    }
198}
199#[doc = "SPI Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_bgr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_bgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
200pub struct SPI_BGR_SPEC;
201impl crate::RegisterSpec for SPI_BGR_SPEC {
202    type Ux = u32;
203}
204#[doc = "`read()` method returns [`spi_bgr::R`](R) reader structure"]
205impl crate::Readable for SPI_BGR_SPEC {}
206#[doc = "`write(|w| ..)` method takes [`spi_bgr::W`](W) writer structure"]
207impl crate::Writable for SPI_BGR_SPEC {
208    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
209    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
210}
211#[doc = "`reset()` method sets spi_bgr to value 0"]
212impl crate::Resettable for SPI_BGR_SPEC {
213    const RESET_VALUE: Self::Ux = 0;
214}
d1_pac/ccu/spi_bgr.rs

d1_pac/ccu/
spi_bgr.rs
