d1_pac/ccu/
smhc2_clk.rs

1#[doc = "Register `smhc2_clk` reader"]
2pub type R = crate::R<SMHC2_CLK_SPEC>;
3#[doc = "Register `smhc2_clk` writer"]
4pub type W = crate::W<SMHC2_CLK_SPEC>;
5#[doc = "Field `factor_m` reader - Factor M"]
6pub type FACTOR_M_R = crate::FieldReader;
7#[doc = "Field `factor_m` writer - Factor M"]
8pub type FACTOR_M_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `factor_n` reader - Factor N"]
10pub type FACTOR_N_R = crate::FieldReader<FACTOR_N_A>;
11#[doc = "Factor N\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13#[repr(u8)]
14pub enum FACTOR_N_A {
15    #[doc = "0: `0`"]
16    N1 = 0,
17    #[doc = "1: `1`"]
18    N2 = 1,
19    #[doc = "2: `10`"]
20    N4 = 2,
21    #[doc = "3: `11`"]
22    N8 = 3,
23}
24impl From<FACTOR_N_A> for u8 {
25    #[inline(always)]
26    fn from(variant: FACTOR_N_A) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for FACTOR_N_A {
31    type Ux = u8;
32}
33impl FACTOR_N_R {
34    #[doc = "Get enumerated values variant"]
35    #[inline(always)]
36    pub const fn variant(&self) -> FACTOR_N_A {
37        match self.bits {
38            0 => FACTOR_N_A::N1,
39            1 => FACTOR_N_A::N2,
40            2 => FACTOR_N_A::N4,
41            3 => FACTOR_N_A::N8,
42            _ => unreachable!(),
43        }
44    }
45    #[doc = "`0`"]
46    #[inline(always)]
47    pub fn is_n1(&self) -> bool {
48        *self == FACTOR_N_A::N1
49    }
50    #[doc = "`1`"]
51    #[inline(always)]
52    pub fn is_n2(&self) -> bool {
53        *self == FACTOR_N_A::N2
54    }
55    #[doc = "`10`"]
56    #[inline(always)]
57    pub fn is_n4(&self) -> bool {
58        *self == FACTOR_N_A::N4
59    }
60    #[doc = "`11`"]
61    #[inline(always)]
62    pub fn is_n8(&self) -> bool {
63        *self == FACTOR_N_A::N8
64    }
65}
66#[doc = "Field `factor_n` writer - Factor N"]
67pub type FACTOR_N_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, FACTOR_N_A>;
68impl<'a, REG> FACTOR_N_W<'a, REG>
69where
70    REG: crate::Writable + crate::RegisterSpec,
71    REG::Ux: From<u8>,
72{
73    #[doc = "`0`"]
74    #[inline(always)]
75    pub fn n1(self) -> &'a mut crate::W<REG> {
76        self.variant(FACTOR_N_A::N1)
77    }
78    #[doc = "`1`"]
79    #[inline(always)]
80    pub fn n2(self) -> &'a mut crate::W<REG> {
81        self.variant(FACTOR_N_A::N2)
82    }
83    #[doc = "`10`"]
84    #[inline(always)]
85    pub fn n4(self) -> &'a mut crate::W<REG> {
86        self.variant(FACTOR_N_A::N4)
87    }
88    #[doc = "`11`"]
89    #[inline(always)]
90    pub fn n8(self) -> &'a mut crate::W<REG> {
91        self.variant(FACTOR_N_A::N8)
92    }
93}
94#[doc = "Field `clk_src_sel` reader - Clock Source Select"]
95pub type CLK_SRC_SEL_R = crate::FieldReader<CLK_SRC_SEL_A>;
96#[doc = "Clock Source Select\n\nValue on reset: 0"]
97#[derive(Clone, Copy, Debug, PartialEq, Eq)]
98#[repr(u8)]
99pub enum CLK_SRC_SEL_A {
100    #[doc = "0: `0`"]
101    HOSC = 0,
102    #[doc = "1: `1`"]
103    PLL_PERI_1X = 1,
104    #[doc = "2: `10`"]
105    PLL_PERI_2X = 2,
106    #[doc = "3: `11`"]
107    PLL_PERI_800M = 3,
108    #[doc = "4: `100`"]
109    PLL_AUDIO1_DIV2 = 4,
110}
111impl From<CLK_SRC_SEL_A> for u8 {
112    #[inline(always)]
113    fn from(variant: CLK_SRC_SEL_A) -> Self {
114        variant as _
115    }
116}
117impl crate::FieldSpec for CLK_SRC_SEL_A {
118    type Ux = u8;
119}
120impl CLK_SRC_SEL_R {
121    #[doc = "Get enumerated values variant"]
122    #[inline(always)]
123    pub const fn variant(&self) -> Option<CLK_SRC_SEL_A> {
124        match self.bits {
125            0 => Some(CLK_SRC_SEL_A::HOSC),
126            1 => Some(CLK_SRC_SEL_A::PLL_PERI_1X),
127            2 => Some(CLK_SRC_SEL_A::PLL_PERI_2X),
128            3 => Some(CLK_SRC_SEL_A::PLL_PERI_800M),
129            4 => Some(CLK_SRC_SEL_A::PLL_AUDIO1_DIV2),
130            _ => None,
131        }
132    }
133    #[doc = "`0`"]
134    #[inline(always)]
135    pub fn is_hosc(&self) -> bool {
136        *self == CLK_SRC_SEL_A::HOSC
137    }
138    #[doc = "`1`"]
139    #[inline(always)]
140    pub fn is_pll_peri_1x(&self) -> bool {
141        *self == CLK_SRC_SEL_A::PLL_PERI_1X
142    }
143    #[doc = "`10`"]
144    #[inline(always)]
145    pub fn is_pll_peri_2x(&self) -> bool {
146        *self == CLK_SRC_SEL_A::PLL_PERI_2X
147    }
148    #[doc = "`11`"]
149    #[inline(always)]
150    pub fn is_pll_peri_800m(&self) -> bool {
151        *self == CLK_SRC_SEL_A::PLL_PERI_800M
152    }
153    #[doc = "`100`"]
154    #[inline(always)]
155    pub fn is_pll_audio1_div2(&self) -> bool {
156        *self == CLK_SRC_SEL_A::PLL_AUDIO1_DIV2
157    }
158}
159#[doc = "Field `clk_src_sel` writer - Clock Source Select"]
160pub type CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CLK_SRC_SEL_A>;
161impl<'a, REG> CLK_SRC_SEL_W<'a, REG>
162where
163    REG: crate::Writable + crate::RegisterSpec,
164    REG::Ux: From<u8>,
165{
166    #[doc = "`0`"]
167    #[inline(always)]
168    pub fn hosc(self) -> &'a mut crate::W<REG> {
169        self.variant(CLK_SRC_SEL_A::HOSC)
170    }
171    #[doc = "`1`"]
172    #[inline(always)]
173    pub fn pll_peri_1x(self) -> &'a mut crate::W<REG> {
174        self.variant(CLK_SRC_SEL_A::PLL_PERI_1X)
175    }
176    #[doc = "`10`"]
177    #[inline(always)]
178    pub fn pll_peri_2x(self) -> &'a mut crate::W<REG> {
179        self.variant(CLK_SRC_SEL_A::PLL_PERI_2X)
180    }
181    #[doc = "`11`"]
182    #[inline(always)]
183    pub fn pll_peri_800m(self) -> &'a mut crate::W<REG> {
184        self.variant(CLK_SRC_SEL_A::PLL_PERI_800M)
185    }
186    #[doc = "`100`"]
187    #[inline(always)]
188    pub fn pll_audio1_div2(self) -> &'a mut crate::W<REG> {
189        self.variant(CLK_SRC_SEL_A::PLL_AUDIO1_DIV2)
190    }
191}
192#[doc = "Field `clk_gating` reader - Gating Clock"]
193pub type CLK_GATING_R = crate::BitReader<CLK_GATING_A>;
194#[doc = "Gating Clock\n\nValue on reset: 0"]
195#[derive(Clone, Copy, Debug, PartialEq, Eq)]
196pub enum CLK_GATING_A {
197    #[doc = "0: `0`"]
198    OFF = 0,
199    #[doc = "1: `1`"]
200    ON = 1,
201}
202impl From<CLK_GATING_A> for bool {
203    #[inline(always)]
204    fn from(variant: CLK_GATING_A) -> Self {
205        variant as u8 != 0
206    }
207}
208impl CLK_GATING_R {
209    #[doc = "Get enumerated values variant"]
210    #[inline(always)]
211    pub const fn variant(&self) -> CLK_GATING_A {
212        match self.bits {
213            false => CLK_GATING_A::OFF,
214            true => CLK_GATING_A::ON,
215        }
216    }
217    #[doc = "`0`"]
218    #[inline(always)]
219    pub fn is_off(&self) -> bool {
220        *self == CLK_GATING_A::OFF
221    }
222    #[doc = "`1`"]
223    #[inline(always)]
224    pub fn is_on(&self) -> bool {
225        *self == CLK_GATING_A::ON
226    }
227}
228#[doc = "Field `clk_gating` writer - Gating Clock"]
229pub type CLK_GATING_W<'a, REG> = crate::BitWriter<'a, REG, CLK_GATING_A>;
230impl<'a, REG> CLK_GATING_W<'a, REG>
231where
232    REG: crate::Writable + crate::RegisterSpec,
233{
234    #[doc = "`0`"]
235    #[inline(always)]
236    pub fn off(self) -> &'a mut crate::W<REG> {
237        self.variant(CLK_GATING_A::OFF)
238    }
239    #[doc = "`1`"]
240    #[inline(always)]
241    pub fn on(self) -> &'a mut crate::W<REG> {
242        self.variant(CLK_GATING_A::ON)
243    }
244}
245impl R {
246    #[doc = "Bits 0:3 - Factor M"]
247    #[inline(always)]
248    pub fn factor_m(&self) -> FACTOR_M_R {
249        FACTOR_M_R::new((self.bits & 0x0f) as u8)
250    }
251    #[doc = "Bits 8:9 - Factor N"]
252    #[inline(always)]
253    pub fn factor_n(&self) -> FACTOR_N_R {
254        FACTOR_N_R::new(((self.bits >> 8) & 3) as u8)
255    }
256    #[doc = "Bits 24:26 - Clock Source Select"]
257    #[inline(always)]
258    pub fn clk_src_sel(&self) -> CLK_SRC_SEL_R {
259        CLK_SRC_SEL_R::new(((self.bits >> 24) & 7) as u8)
260    }
261    #[doc = "Bit 31 - Gating Clock"]
262    #[inline(always)]
263    pub fn clk_gating(&self) -> CLK_GATING_R {
264        CLK_GATING_R::new(((self.bits >> 31) & 1) != 0)
265    }
266}
267impl W {
268    #[doc = "Bits 0:3 - Factor M"]
269    #[inline(always)]
270    #[must_use]
271    pub fn factor_m(&mut self) -> FACTOR_M_W<SMHC2_CLK_SPEC> {
272        FACTOR_M_W::new(self, 0)
273    }
274    #[doc = "Bits 8:9 - Factor N"]
275    #[inline(always)]
276    #[must_use]
277    pub fn factor_n(&mut self) -> FACTOR_N_W<SMHC2_CLK_SPEC> {
278        FACTOR_N_W::new(self, 8)
279    }
280    #[doc = "Bits 24:26 - Clock Source Select"]
281    #[inline(always)]
282    #[must_use]
283    pub fn clk_src_sel(&mut self) -> CLK_SRC_SEL_W<SMHC2_CLK_SPEC> {
284        CLK_SRC_SEL_W::new(self, 24)
285    }
286    #[doc = "Bit 31 - Gating Clock"]
287    #[inline(always)]
288    #[must_use]
289    pub fn clk_gating(&mut self) -> CLK_GATING_W<SMHC2_CLK_SPEC> {
290        CLK_GATING_W::new(self, 31)
291    }
292    #[doc = r" Writes raw bits to the register."]
293    #[doc = r""]
294    #[doc = r" # Safety"]
295    #[doc = r""]
296    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
297    #[inline(always)]
298    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
299        self.bits = bits;
300        self
301    }
302}
303#[doc = "SMHC2 Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc2_clk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc2_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
304pub struct SMHC2_CLK_SPEC;
305impl crate::RegisterSpec for SMHC2_CLK_SPEC {
306    type Ux = u32;
307}
308#[doc = "`read()` method returns [`smhc2_clk::R`](R) reader structure"]
309impl crate::Readable for SMHC2_CLK_SPEC {}
310#[doc = "`write(|w| ..)` method takes [`smhc2_clk::W`](W) writer structure"]
311impl crate::Writable for SMHC2_CLK_SPEC {
312    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
313    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
314}
315#[doc = "`reset()` method sets smhc2_clk to value 0"]
316impl crate::Resettable for SMHC2_CLK_SPEC {
317    const RESET_VALUE: Self::Ux = 0;
318}
d1_pac/ccu/smhc2_clk.rs

d1_pac/ccu/
smhc2_clk.rs
