d1_pac/ccu/
riscv_gating.rs

1#[doc = "Register `riscv_gating` reader"]
2pub type R = crate::R<RISCV_GATING_SPEC>;
3#[doc = "Register `riscv_gating` writer"]
4pub type W = crate::W<RISCV_GATING_SPEC>;
5#[doc = "Field `gating_field` reader - "]
6pub type GATING_FIELD_R = crate::FieldReader<u16>;
7#[doc = "Field `gating_field` writer - "]
8pub type GATING_FIELD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9#[doc = "Field `gating` reader - Gating Clock"]
10pub type GATING_R = crate::BitReader<GATING_A>;
11#[doc = "Gating Clock\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13pub enum GATING_A {
14    #[doc = "0: `0`"]
15    MASK = 0,
16    #[doc = "1: `1`"]
17    PASS = 1,
18}
19impl From<GATING_A> for bool {
20    #[inline(always)]
21    fn from(variant: GATING_A) -> Self {
22        variant as u8 != 0
23    }
24}
25impl GATING_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> GATING_A {
29        match self.bits {
30            false => GATING_A::MASK,
31            true => GATING_A::PASS,
32        }
33    }
34    #[doc = "`0`"]
35    #[inline(always)]
36    pub fn is_mask(&self) -> bool {
37        *self == GATING_A::MASK
38    }
39    #[doc = "`1`"]
40    #[inline(always)]
41    pub fn is_pass(&self) -> bool {
42        *self == GATING_A::PASS
43    }
44}
45#[doc = "Field `gating` writer - Gating Clock"]
46pub type GATING_W<'a, REG> = crate::BitWriter<'a, REG, GATING_A>;
47impl<'a, REG> GATING_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "`0`"]
52    #[inline(always)]
53    pub fn mask(self) -> &'a mut crate::W<REG> {
54        self.variant(GATING_A::MASK)
55    }
56    #[doc = "`1`"]
57    #[inline(always)]
58    pub fn pass(self) -> &'a mut crate::W<REG> {
59        self.variant(GATING_A::PASS)
60    }
61}
62impl R {
63    #[doc = "Bits 0:15"]
64    #[inline(always)]
65    pub fn gating_field(&self) -> GATING_FIELD_R {
66        GATING_FIELD_R::new((self.bits & 0xffff) as u16)
67    }
68    #[doc = "Bit 31 - Gating Clock"]
69    #[inline(always)]
70    pub fn gating(&self) -> GATING_R {
71        GATING_R::new(((self.bits >> 31) & 1) != 0)
72    }
73}
74impl W {
75    #[doc = "Bits 0:15"]
76    #[inline(always)]
77    #[must_use]
78    pub fn gating_field(&mut self) -> GATING_FIELD_W<RISCV_GATING_SPEC> {
79        GATING_FIELD_W::new(self, 0)
80    }
81    #[doc = "Bit 31 - Gating Clock"]
82    #[inline(always)]
83    #[must_use]
84    pub fn gating(&mut self) -> GATING_W<RISCV_GATING_SPEC> {
85        GATING_W::new(self, 31)
86    }
87    #[doc = r" Writes raw bits to the register."]
88    #[doc = r""]
89    #[doc = r" # Safety"]
90    #[doc = r""]
91    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
92    #[inline(always)]
93    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
94        self.bits = bits;
95        self
96    }
97}
98#[doc = "RISC-V GATING Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`riscv_gating::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`riscv_gating::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
99pub struct RISCV_GATING_SPEC;
100impl crate::RegisterSpec for RISCV_GATING_SPEC {
101    type Ux = u32;
102}
103#[doc = "`read()` method returns [`riscv_gating::R`](R) reader structure"]
104impl crate::Readable for RISCV_GATING_SPEC {}
105#[doc = "`write(|w| ..)` method takes [`riscv_gating::W`](W) writer structure"]
106impl crate::Writable for RISCV_GATING_SPEC {
107    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
108    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
109}
110#[doc = "`reset()` method sets riscv_gating to value 0"]
111impl crate::Resettable for RISCV_GATING_SPEC {
112    const RESET_VALUE: Self::Ux = 0;
113}
d1_pac/ccu/riscv_gating.rs

d1_pac/ccu/
riscv_gating.rs
