1#[doc = "Register `riscv_clk` reader"]
2pub type R = crate::R<RISCV_CLK_SPEC>;
3#[doc = "Register `riscv_clk` writer"]
4pub type W = crate::W<RISCV_CLK_SPEC>;
5#[doc = "Field `div_cfg` reader - Factor M"]
6pub type DIV_CFG_R = crate::FieldReader;
7#[doc = "Field `div_cfg` writer - Factor M"]
8pub type DIV_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `axi_div_cfg` reader - Factor N"]
10pub type AXI_DIV_CFG_R = crate::FieldReader;
11#[doc = "Field `axi_div_cfg` writer - Factor N"]
12pub type AXI_DIV_CFG_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `clk_src_sel` reader - Clock Source Select"]
14pub type CLK_SRC_SEL_R = crate::FieldReader<CLK_SRC_SEL_A>;
15#[doc = "Clock Source Select\n\nValue on reset: 0"]
16#[derive(Clone, Copy, Debug, PartialEq, Eq)]
17#[repr(u8)]
18pub enum CLK_SRC_SEL_A {
19 #[doc = "0: `0`"]
20 HOSC = 0,
21 #[doc = "1: `1`"]
22 CLK32K = 1,
23 #[doc = "2: `10`"]
24 CLK16M_RC = 2,
25 #[doc = "3: `11`"]
26 PLL_PERI_800M = 3,
27 #[doc = "4: `100`"]
28 PLL_PERI_1X = 4,
29 #[doc = "5: `101`"]
30 PLL_CPU = 5,
31 #[doc = "6: `110`"]
32 PLL_AUDIO1_DIV2 = 6,
33}
34impl From<CLK_SRC_SEL_A> for u8 {
35 #[inline(always)]
36 fn from(variant: CLK_SRC_SEL_A) -> Self {
37 variant as _
38 }
39}
40impl crate::FieldSpec for CLK_SRC_SEL_A {
41 type Ux = u8;
42}
43impl CLK_SRC_SEL_R {
44 #[doc = "Get enumerated values variant"]
45 #[inline(always)]
46 pub const fn variant(&self) -> Option<CLK_SRC_SEL_A> {
47 match self.bits {
48 0 => Some(CLK_SRC_SEL_A::HOSC),
49 1 => Some(CLK_SRC_SEL_A::CLK32K),
50 2 => Some(CLK_SRC_SEL_A::CLK16M_RC),
51 3 => Some(CLK_SRC_SEL_A::PLL_PERI_800M),
52 4 => Some(CLK_SRC_SEL_A::PLL_PERI_1X),
53 5 => Some(CLK_SRC_SEL_A::PLL_CPU),
54 6 => Some(CLK_SRC_SEL_A::PLL_AUDIO1_DIV2),
55 _ => None,
56 }
57 }
58 #[doc = "`0`"]
59 #[inline(always)]
60 pub fn is_hosc(&self) -> bool {
61 *self == CLK_SRC_SEL_A::HOSC
62 }
63 #[doc = "`1`"]
64 #[inline(always)]
65 pub fn is_clk32k(&self) -> bool {
66 *self == CLK_SRC_SEL_A::CLK32K
67 }
68 #[doc = "`10`"]
69 #[inline(always)]
70 pub fn is_clk16m_rc(&self) -> bool {
71 *self == CLK_SRC_SEL_A::CLK16M_RC
72 }
73 #[doc = "`11`"]
74 #[inline(always)]
75 pub fn is_pll_peri_800m(&self) -> bool {
76 *self == CLK_SRC_SEL_A::PLL_PERI_800M
77 }
78 #[doc = "`100`"]
79 #[inline(always)]
80 pub fn is_pll_peri_1x(&self) -> bool {
81 *self == CLK_SRC_SEL_A::PLL_PERI_1X
82 }
83 #[doc = "`101`"]
84 #[inline(always)]
85 pub fn is_pll_cpu(&self) -> bool {
86 *self == CLK_SRC_SEL_A::PLL_CPU
87 }
88 #[doc = "`110`"]
89 #[inline(always)]
90 pub fn is_pll_audio1_div2(&self) -> bool {
91 *self == CLK_SRC_SEL_A::PLL_AUDIO1_DIV2
92 }
93}
94#[doc = "Field `clk_src_sel` writer - Clock Source Select"]
95pub type CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CLK_SRC_SEL_A>;
96impl<'a, REG> CLK_SRC_SEL_W<'a, REG>
97where
98 REG: crate::Writable + crate::RegisterSpec,
99 REG::Ux: From<u8>,
100{
101 #[doc = "`0`"]
102 #[inline(always)]
103 pub fn hosc(self) -> &'a mut crate::W<REG> {
104 self.variant(CLK_SRC_SEL_A::HOSC)
105 }
106 #[doc = "`1`"]
107 #[inline(always)]
108 pub fn clk32k(self) -> &'a mut crate::W<REG> {
109 self.variant(CLK_SRC_SEL_A::CLK32K)
110 }
111 #[doc = "`10`"]
112 #[inline(always)]
113 pub fn clk16m_rc(self) -> &'a mut crate::W<REG> {
114 self.variant(CLK_SRC_SEL_A::CLK16M_RC)
115 }
116 #[doc = "`11`"]
117 #[inline(always)]
118 pub fn pll_peri_800m(self) -> &'a mut crate::W<REG> {
119 self.variant(CLK_SRC_SEL_A::PLL_PERI_800M)
120 }
121 #[doc = "`100`"]
122 #[inline(always)]
123 pub fn pll_peri_1x(self) -> &'a mut crate::W<REG> {
124 self.variant(CLK_SRC_SEL_A::PLL_PERI_1X)
125 }
126 #[doc = "`101`"]
127 #[inline(always)]
128 pub fn pll_cpu(self) -> &'a mut crate::W<REG> {
129 self.variant(CLK_SRC_SEL_A::PLL_CPU)
130 }
131 #[doc = "`110`"]
132 #[inline(always)]
133 pub fn pll_audio1_div2(self) -> &'a mut crate::W<REG> {
134 self.variant(CLK_SRC_SEL_A::PLL_AUDIO1_DIV2)
135 }
136}
137impl R {
138 #[doc = "Bits 0:4 - Factor M"]
139 #[inline(always)]
140 pub fn div_cfg(&self) -> DIV_CFG_R {
141 DIV_CFG_R::new((self.bits & 0x1f) as u8)
142 }
143 #[doc = "Bits 8:9 - Factor N"]
144 #[inline(always)]
145 pub fn axi_div_cfg(&self) -> AXI_DIV_CFG_R {
146 AXI_DIV_CFG_R::new(((self.bits >> 8) & 3) as u8)
147 }
148 #[doc = "Bits 24:26 - Clock Source Select"]
149 #[inline(always)]
150 pub fn clk_src_sel(&self) -> CLK_SRC_SEL_R {
151 CLK_SRC_SEL_R::new(((self.bits >> 24) & 7) as u8)
152 }
153}
154impl W {
155 #[doc = "Bits 0:4 - Factor M"]
156 #[inline(always)]
157 #[must_use]
158 pub fn div_cfg(&mut self) -> DIV_CFG_W<RISCV_CLK_SPEC> {
159 DIV_CFG_W::new(self, 0)
160 }
161 #[doc = "Bits 8:9 - Factor N"]
162 #[inline(always)]
163 #[must_use]
164 pub fn axi_div_cfg(&mut self) -> AXI_DIV_CFG_W<RISCV_CLK_SPEC> {
165 AXI_DIV_CFG_W::new(self, 8)
166 }
167 #[doc = "Bits 24:26 - Clock Source Select"]
168 #[inline(always)]
169 #[must_use]
170 pub fn clk_src_sel(&mut self) -> CLK_SRC_SEL_W<RISCV_CLK_SPEC> {
171 CLK_SRC_SEL_W::new(self, 24)
172 }
173 #[doc = r" Writes raw bits to the register."]
174 #[doc = r""]
175 #[doc = r" # Safety"]
176 #[doc = r""]
177 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
178 #[inline(always)]
179 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
180 self.bits = bits;
181 self
182 }
183}
184#[doc = "RISC-V Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`riscv_clk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`riscv_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
185pub struct RISCV_CLK_SPEC;
186impl crate::RegisterSpec for RISCV_CLK_SPEC {
187 type Ux = u32;
188}
189#[doc = "`read()` method returns [`riscv_clk::R`](R) reader structure"]
190impl crate::Readable for RISCV_CLK_SPEC {}
191#[doc = "`write(|w| ..)` method takes [`riscv_clk::W`](W) writer structure"]
192impl crate::Writable for RISCV_CLK_SPEC {
193 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
194 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
195}
196#[doc = "`reset()` method sets riscv_clk to value 0"]
197impl crate::Resettable for RISCV_CLK_SPEC {
198 const RESET_VALUE: Self::Ux = 0;
199}