d1_pac/ccu/
psi_clk.rs

1#[doc = "Register `psi_clk` reader"]
2pub type R = crate::R<PSI_CLK_SPEC>;
3#[doc = "Register `psi_clk` writer"]
4pub type W = crate::W<PSI_CLK_SPEC>;
5#[doc = "Field `factor_m` reader - Factor M"]
6pub type FACTOR_M_R = crate::FieldReader;
7#[doc = "Field `factor_m` writer - Factor M"]
8pub type FACTOR_M_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `factor_n` reader - Factor N"]
10pub type FACTOR_N_R = crate::FieldReader<FACTOR_N_A>;
11#[doc = "Factor N\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13#[repr(u8)]
14pub enum FACTOR_N_A {
15    #[doc = "0: `0`"]
16    N1 = 0,
17    #[doc = "1: `1`"]
18    N2 = 1,
19    #[doc = "2: `10`"]
20    N4 = 2,
21    #[doc = "3: `11`"]
22    N8 = 3,
23}
24impl From<FACTOR_N_A> for u8 {
25    #[inline(always)]
26    fn from(variant: FACTOR_N_A) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for FACTOR_N_A {
31    type Ux = u8;
32}
33impl FACTOR_N_R {
34    #[doc = "Get enumerated values variant"]
35    #[inline(always)]
36    pub const fn variant(&self) -> FACTOR_N_A {
37        match self.bits {
38            0 => FACTOR_N_A::N1,
39            1 => FACTOR_N_A::N2,
40            2 => FACTOR_N_A::N4,
41            3 => FACTOR_N_A::N8,
42            _ => unreachable!(),
43        }
44    }
45    #[doc = "`0`"]
46    #[inline(always)]
47    pub fn is_n1(&self) -> bool {
48        *self == FACTOR_N_A::N1
49    }
50    #[doc = "`1`"]
51    #[inline(always)]
52    pub fn is_n2(&self) -> bool {
53        *self == FACTOR_N_A::N2
54    }
55    #[doc = "`10`"]
56    #[inline(always)]
57    pub fn is_n4(&self) -> bool {
58        *self == FACTOR_N_A::N4
59    }
60    #[doc = "`11`"]
61    #[inline(always)]
62    pub fn is_n8(&self) -> bool {
63        *self == FACTOR_N_A::N8
64    }
65}
66#[doc = "Field `factor_n` writer - Factor N"]
67pub type FACTOR_N_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, FACTOR_N_A>;
68impl<'a, REG> FACTOR_N_W<'a, REG>
69where
70    REG: crate::Writable + crate::RegisterSpec,
71    REG::Ux: From<u8>,
72{
73    #[doc = "`0`"]
74    #[inline(always)]
75    pub fn n1(self) -> &'a mut crate::W<REG> {
76        self.variant(FACTOR_N_A::N1)
77    }
78    #[doc = "`1`"]
79    #[inline(always)]
80    pub fn n2(self) -> &'a mut crate::W<REG> {
81        self.variant(FACTOR_N_A::N2)
82    }
83    #[doc = "`10`"]
84    #[inline(always)]
85    pub fn n4(self) -> &'a mut crate::W<REG> {
86        self.variant(FACTOR_N_A::N4)
87    }
88    #[doc = "`11`"]
89    #[inline(always)]
90    pub fn n8(self) -> &'a mut crate::W<REG> {
91        self.variant(FACTOR_N_A::N8)
92    }
93}
94#[doc = "Field `clk_src_sel` reader - Clock Source Select"]
95pub type CLK_SRC_SEL_R = crate::FieldReader<CLK_SRC_SEL_A>;
96#[doc = "Clock Source Select\n\nValue on reset: 0"]
97#[derive(Clone, Copy, Debug, PartialEq, Eq)]
98#[repr(u8)]
99pub enum CLK_SRC_SEL_A {
100    #[doc = "0: `0`"]
101    HOSC = 0,
102    #[doc = "1: `1`"]
103    CLK32K = 1,
104    #[doc = "2: `10`"]
105    CLK16M_RC = 2,
106    #[doc = "3: `11`"]
107    PLL_PERI_1X = 3,
108}
109impl From<CLK_SRC_SEL_A> for u8 {
110    #[inline(always)]
111    fn from(variant: CLK_SRC_SEL_A) -> Self {
112        variant as _
113    }
114}
115impl crate::FieldSpec for CLK_SRC_SEL_A {
116    type Ux = u8;
117}
118impl CLK_SRC_SEL_R {
119    #[doc = "Get enumerated values variant"]
120    #[inline(always)]
121    pub const fn variant(&self) -> CLK_SRC_SEL_A {
122        match self.bits {
123            0 => CLK_SRC_SEL_A::HOSC,
124            1 => CLK_SRC_SEL_A::CLK32K,
125            2 => CLK_SRC_SEL_A::CLK16M_RC,
126            3 => CLK_SRC_SEL_A::PLL_PERI_1X,
127            _ => unreachable!(),
128        }
129    }
130    #[doc = "`0`"]
131    #[inline(always)]
132    pub fn is_hosc(&self) -> bool {
133        *self == CLK_SRC_SEL_A::HOSC
134    }
135    #[doc = "`1`"]
136    #[inline(always)]
137    pub fn is_clk32k(&self) -> bool {
138        *self == CLK_SRC_SEL_A::CLK32K
139    }
140    #[doc = "`10`"]
141    #[inline(always)]
142    pub fn is_clk16m_rc(&self) -> bool {
143        *self == CLK_SRC_SEL_A::CLK16M_RC
144    }
145    #[doc = "`11`"]
146    #[inline(always)]
147    pub fn is_pll_peri_1x(&self) -> bool {
148        *self == CLK_SRC_SEL_A::PLL_PERI_1X
149    }
150}
151#[doc = "Field `clk_src_sel` writer - Clock Source Select"]
152pub type CLK_SRC_SEL_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, CLK_SRC_SEL_A>;
153impl<'a, REG> CLK_SRC_SEL_W<'a, REG>
154where
155    REG: crate::Writable + crate::RegisterSpec,
156    REG::Ux: From<u8>,
157{
158    #[doc = "`0`"]
159    #[inline(always)]
160    pub fn hosc(self) -> &'a mut crate::W<REG> {
161        self.variant(CLK_SRC_SEL_A::HOSC)
162    }
163    #[doc = "`1`"]
164    #[inline(always)]
165    pub fn clk32k(self) -> &'a mut crate::W<REG> {
166        self.variant(CLK_SRC_SEL_A::CLK32K)
167    }
168    #[doc = "`10`"]
169    #[inline(always)]
170    pub fn clk16m_rc(self) -> &'a mut crate::W<REG> {
171        self.variant(CLK_SRC_SEL_A::CLK16M_RC)
172    }
173    #[doc = "`11`"]
174    #[inline(always)]
175    pub fn pll_peri_1x(self) -> &'a mut crate::W<REG> {
176        self.variant(CLK_SRC_SEL_A::PLL_PERI_1X)
177    }
178}
179impl R {
180    #[doc = "Bits 0:1 - Factor M"]
181    #[inline(always)]
182    pub fn factor_m(&self) -> FACTOR_M_R {
183        FACTOR_M_R::new((self.bits & 3) as u8)
184    }
185    #[doc = "Bits 8:9 - Factor N"]
186    #[inline(always)]
187    pub fn factor_n(&self) -> FACTOR_N_R {
188        FACTOR_N_R::new(((self.bits >> 8) & 3) as u8)
189    }
190    #[doc = "Bits 24:25 - Clock Source Select"]
191    #[inline(always)]
192    pub fn clk_src_sel(&self) -> CLK_SRC_SEL_R {
193        CLK_SRC_SEL_R::new(((self.bits >> 24) & 3) as u8)
194    }
195}
196impl W {
197    #[doc = "Bits 0:1 - Factor M"]
198    #[inline(always)]
199    #[must_use]
200    pub fn factor_m(&mut self) -> FACTOR_M_W<PSI_CLK_SPEC> {
201        FACTOR_M_W::new(self, 0)
202    }
203    #[doc = "Bits 8:9 - Factor N"]
204    #[inline(always)]
205    #[must_use]
206    pub fn factor_n(&mut self) -> FACTOR_N_W<PSI_CLK_SPEC> {
207        FACTOR_N_W::new(self, 8)
208    }
209    #[doc = "Bits 24:25 - Clock Source Select"]
210    #[inline(always)]
211    #[must_use]
212    pub fn clk_src_sel(&mut self) -> CLK_SRC_SEL_W<PSI_CLK_SPEC> {
213        CLK_SRC_SEL_W::new(self, 24)
214    }
215    #[doc = r" Writes raw bits to the register."]
216    #[doc = r""]
217    #[doc = r" # Safety"]
218    #[doc = r""]
219    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
220    #[inline(always)]
221    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
222        self.bits = bits;
223        self
224    }
225}
226#[doc = "PSI Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psi_clk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psi_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
227pub struct PSI_CLK_SPEC;
228impl crate::RegisterSpec for PSI_CLK_SPEC {
229    type Ux = u32;
230}
231#[doc = "`read()` method returns [`psi_clk::R`](R) reader structure"]
232impl crate::Readable for PSI_CLK_SPEC {}
233#[doc = "`write(|w| ..)` method takes [`psi_clk::W`](W) writer structure"]
234impl crate::Writable for PSI_CLK_SPEC {
235    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
236    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
237}
238#[doc = "`reset()` method sets psi_clk to value 0"]
239impl crate::Resettable for PSI_CLK_SPEC {
240    const RESET_VALUE: Self::Ux = 0;
241}
d1_pac/ccu/psi_clk.rs

d1_pac/ccu/
psi_clk.rs
