d1_pac/ccu/
pll_video0_ctrl.rs

1#[doc = "Register `pll_video0_ctrl` reader"]
2pub type R = crate::R<PLL_VIDEO0_CTRL_SPEC>;
3#[doc = "Register `pll_video0_ctrl` writer"]
4pub type W = crate::W<PLL_VIDEO0_CTRL_SPEC>;
5#[doc = "Field `pll_output_div2` reader - PLL Output Div D"]
6pub type PLL_OUTPUT_DIV2_R = crate::BitReader;
7#[doc = "Field `pll_output_div2` writer - PLL Output Div D"]
8pub type PLL_OUTPUT_DIV2_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `pll_input_div2` reader - PLL Input Div M"]
10pub type PLL_INPUT_DIV2_R = crate::BitReader;
11#[doc = "Field `pll_input_div2` writer - PLL Input Div M"]
12pub type PLL_INPUT_DIV2_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `pll_lock_mdsel` reader - PLL Lock Level"]
14pub type PLL_LOCK_MDSEL_R = crate::BitReader<PLL_LOCK_MDSEL_A>;
15#[doc = "PLL Lock Level\n\nValue on reset: 0"]
16#[derive(Clone, Copy, Debug, PartialEq, Eq)]
17pub enum PLL_LOCK_MDSEL_A {
18    #[doc = "0: `0`"]
19    CC_24_26 = 0,
20    #[doc = "1: `1`"]
21    CC_23_27 = 1,
22}
23impl From<PLL_LOCK_MDSEL_A> for bool {
24    #[inline(always)]
25    fn from(variant: PLL_LOCK_MDSEL_A) -> Self {
26        variant as u8 != 0
27    }
28}
29impl PLL_LOCK_MDSEL_R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> PLL_LOCK_MDSEL_A {
33        match self.bits {
34            false => PLL_LOCK_MDSEL_A::CC_24_26,
35            true => PLL_LOCK_MDSEL_A::CC_23_27,
36        }
37    }
38    #[doc = "`0`"]
39    #[inline(always)]
40    pub fn is_cc_24_26(&self) -> bool {
41        *self == PLL_LOCK_MDSEL_A::CC_24_26
42    }
43    #[doc = "`1`"]
44    #[inline(always)]
45    pub fn is_cc_23_27(&self) -> bool {
46        *self == PLL_LOCK_MDSEL_A::CC_23_27
47    }
48}
49#[doc = "Field `pll_lock_mdsel` writer - PLL Lock Level"]
50pub type PLL_LOCK_MDSEL_W<'a, REG> = crate::BitWriter<'a, REG, PLL_LOCK_MDSEL_A>;
51impl<'a, REG> PLL_LOCK_MDSEL_W<'a, REG>
52where
53    REG: crate::Writable + crate::RegisterSpec,
54{
55    #[doc = "`0`"]
56    #[inline(always)]
57    pub fn cc_24_26(self) -> &'a mut crate::W<REG> {
58        self.variant(PLL_LOCK_MDSEL_A::CC_24_26)
59    }
60    #[doc = "`1`"]
61    #[inline(always)]
62    pub fn cc_23_27(self) -> &'a mut crate::W<REG> {
63        self.variant(PLL_LOCK_MDSEL_A::CC_23_27)
64    }
65}
66#[doc = "Field `pll_unlock_mdsel` reader - PLL Unlock Level"]
67pub type PLL_UNLOCK_MDSEL_R = crate::FieldReader<PLL_UNLOCK_MDSEL_A>;
68#[doc = "PLL Unlock Level\n\nValue on reset: 0"]
69#[derive(Clone, Copy, Debug, PartialEq, Eq)]
70#[repr(u8)]
71pub enum PLL_UNLOCK_MDSEL_A {
72    #[doc = "0: `0`"]
73    CC_21_29 = 0,
74    #[doc = "1: `1`"]
75    CC_22_28 = 1,
76    #[doc = "2: `10`"]
77    CC_20_30 = 2,
78}
79impl From<PLL_UNLOCK_MDSEL_A> for u8 {
80    #[inline(always)]
81    fn from(variant: PLL_UNLOCK_MDSEL_A) -> Self {
82        variant as _
83    }
84}
85impl crate::FieldSpec for PLL_UNLOCK_MDSEL_A {
86    type Ux = u8;
87}
88impl PLL_UNLOCK_MDSEL_R {
89    #[doc = "Get enumerated values variant"]
90    #[inline(always)]
91    pub const fn variant(&self) -> Option<PLL_UNLOCK_MDSEL_A> {
92        match self.bits {
93            0 => Some(PLL_UNLOCK_MDSEL_A::CC_21_29),
94            1 => Some(PLL_UNLOCK_MDSEL_A::CC_22_28),
95            2 => Some(PLL_UNLOCK_MDSEL_A::CC_20_30),
96            _ => None,
97        }
98    }
99    #[doc = "`0`"]
100    #[inline(always)]
101    pub fn is_cc_21_29(&self) -> bool {
102        *self == PLL_UNLOCK_MDSEL_A::CC_21_29
103    }
104    #[doc = "`1`"]
105    #[inline(always)]
106    pub fn is_cc_22_28(&self) -> bool {
107        *self == PLL_UNLOCK_MDSEL_A::CC_22_28
108    }
109    #[doc = "`10`"]
110    #[inline(always)]
111    pub fn is_cc_20_30(&self) -> bool {
112        *self == PLL_UNLOCK_MDSEL_A::CC_20_30
113    }
114}
115#[doc = "Field `pll_unlock_mdsel` writer - PLL Unlock Level"]
116pub type PLL_UNLOCK_MDSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PLL_UNLOCK_MDSEL_A>;
117impl<'a, REG> PLL_UNLOCK_MDSEL_W<'a, REG>
118where
119    REG: crate::Writable + crate::RegisterSpec,
120    REG::Ux: From<u8>,
121{
122    #[doc = "`0`"]
123    #[inline(always)]
124    pub fn cc_21_29(self) -> &'a mut crate::W<REG> {
125        self.variant(PLL_UNLOCK_MDSEL_A::CC_21_29)
126    }
127    #[doc = "`1`"]
128    #[inline(always)]
129    pub fn cc_22_28(self) -> &'a mut crate::W<REG> {
130        self.variant(PLL_UNLOCK_MDSEL_A::CC_22_28)
131    }
132    #[doc = "`10`"]
133    #[inline(always)]
134    pub fn cc_20_30(self) -> &'a mut crate::W<REG> {
135        self.variant(PLL_UNLOCK_MDSEL_A::CC_20_30)
136    }
137}
138#[doc = "Field `pll_n` reader - PLL N"]
139pub type PLL_N_R = crate::FieldReader;
140#[doc = "Field `pll_n` writer - PLL N"]
141pub type PLL_N_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
142#[doc = "Field `pll_sdm_en` reader - PLL SDM Enable"]
143pub type PLL_SDM_EN_R = crate::BitReader<PLL_SDM_EN_A>;
144#[doc = "PLL SDM Enable\n\nValue on reset: 0"]
145#[derive(Clone, Copy, Debug, PartialEq, Eq)]
146pub enum PLL_SDM_EN_A {
147    #[doc = "0: `0`"]
148    DISABLE = 0,
149    #[doc = "1: `1`"]
150    ENABLE = 1,
151}
152impl From<PLL_SDM_EN_A> for bool {
153    #[inline(always)]
154    fn from(variant: PLL_SDM_EN_A) -> Self {
155        variant as u8 != 0
156    }
157}
158impl PLL_SDM_EN_R {
159    #[doc = "Get enumerated values variant"]
160    #[inline(always)]
161    pub const fn variant(&self) -> PLL_SDM_EN_A {
162        match self.bits {
163            false => PLL_SDM_EN_A::DISABLE,
164            true => PLL_SDM_EN_A::ENABLE,
165        }
166    }
167    #[doc = "`0`"]
168    #[inline(always)]
169    pub fn is_disable(&self) -> bool {
170        *self == PLL_SDM_EN_A::DISABLE
171    }
172    #[doc = "`1`"]
173    #[inline(always)]
174    pub fn is_enable(&self) -> bool {
175        *self == PLL_SDM_EN_A::ENABLE
176    }
177}
178#[doc = "Field `pll_sdm_en` writer - PLL SDM Enable"]
179pub type PLL_SDM_EN_W<'a, REG> = crate::BitWriter<'a, REG, PLL_SDM_EN_A>;
180impl<'a, REG> PLL_SDM_EN_W<'a, REG>
181where
182    REG: crate::Writable + crate::RegisterSpec,
183{
184    #[doc = "`0`"]
185    #[inline(always)]
186    pub fn disable(self) -> &'a mut crate::W<REG> {
187        self.variant(PLL_SDM_EN_A::DISABLE)
188    }
189    #[doc = "`1`"]
190    #[inline(always)]
191    pub fn enable(self) -> &'a mut crate::W<REG> {
192        self.variant(PLL_SDM_EN_A::ENABLE)
193    }
194}
195#[doc = "Field `pll_output_gate` reader - PLL Output Gating Enable"]
196pub type PLL_OUTPUT_GATE_R = crate::BitReader<PLL_OUTPUT_GATE_A>;
197#[doc = "PLL Output Gating Enable\n\nValue on reset: 0"]
198#[derive(Clone, Copy, Debug, PartialEq, Eq)]
199pub enum PLL_OUTPUT_GATE_A {
200    #[doc = "0: `0`"]
201    DISABLE = 0,
202    #[doc = "1: `1`"]
203    ENABLE = 1,
204}
205impl From<PLL_OUTPUT_GATE_A> for bool {
206    #[inline(always)]
207    fn from(variant: PLL_OUTPUT_GATE_A) -> Self {
208        variant as u8 != 0
209    }
210}
211impl PLL_OUTPUT_GATE_R {
212    #[doc = "Get enumerated values variant"]
213    #[inline(always)]
214    pub const fn variant(&self) -> PLL_OUTPUT_GATE_A {
215        match self.bits {
216            false => PLL_OUTPUT_GATE_A::DISABLE,
217            true => PLL_OUTPUT_GATE_A::ENABLE,
218        }
219    }
220    #[doc = "`0`"]
221    #[inline(always)]
222    pub fn is_disable(&self) -> bool {
223        *self == PLL_OUTPUT_GATE_A::DISABLE
224    }
225    #[doc = "`1`"]
226    #[inline(always)]
227    pub fn is_enable(&self) -> bool {
228        *self == PLL_OUTPUT_GATE_A::ENABLE
229    }
230}
231#[doc = "Field `pll_output_gate` writer - PLL Output Gating Enable"]
232pub type PLL_OUTPUT_GATE_W<'a, REG> = crate::BitWriter<'a, REG, PLL_OUTPUT_GATE_A>;
233impl<'a, REG> PLL_OUTPUT_GATE_W<'a, REG>
234where
235    REG: crate::Writable + crate::RegisterSpec,
236{
237    #[doc = "`0`"]
238    #[inline(always)]
239    pub fn disable(self) -> &'a mut crate::W<REG> {
240        self.variant(PLL_OUTPUT_GATE_A::DISABLE)
241    }
242    #[doc = "`1`"]
243    #[inline(always)]
244    pub fn enable(self) -> &'a mut crate::W<REG> {
245        self.variant(PLL_OUTPUT_GATE_A::ENABLE)
246    }
247}
248#[doc = "Field `lock` reader - PLL Lock Status"]
249pub type LOCK_R = crate::BitReader<LOCK_A>;
250#[doc = "PLL Lock Status\n\nValue on reset: 0"]
251#[derive(Clone, Copy, Debug, PartialEq, Eq)]
252pub enum LOCK_A {
253    #[doc = "0: `0`"]
254    UNLOCKED = 0,
255    #[doc = "1: `1`"]
256    LOCKED = 1,
257}
258impl From<LOCK_A> for bool {
259    #[inline(always)]
260    fn from(variant: LOCK_A) -> Self {
261        variant as u8 != 0
262    }
263}
264impl LOCK_R {
265    #[doc = "Get enumerated values variant"]
266    #[inline(always)]
267    pub const fn variant(&self) -> LOCK_A {
268        match self.bits {
269            false => LOCK_A::UNLOCKED,
270            true => LOCK_A::LOCKED,
271        }
272    }
273    #[doc = "`0`"]
274    #[inline(always)]
275    pub fn is_unlocked(&self) -> bool {
276        *self == LOCK_A::UNLOCKED
277    }
278    #[doc = "`1`"]
279    #[inline(always)]
280    pub fn is_locked(&self) -> bool {
281        *self == LOCK_A::LOCKED
282    }
283}
284#[doc = "Field `lock_enable` reader - Lock Enable"]
285pub type LOCK_ENABLE_R = crate::BitReader<LOCK_ENABLE_A>;
286#[doc = "Lock Enable\n\nValue on reset: 0"]
287#[derive(Clone, Copy, Debug, PartialEq, Eq)]
288pub enum LOCK_ENABLE_A {
289    #[doc = "0: `0`"]
290    DISABLE = 0,
291    #[doc = "1: `1`"]
292    ENABLE = 1,
293}
294impl From<LOCK_ENABLE_A> for bool {
295    #[inline(always)]
296    fn from(variant: LOCK_ENABLE_A) -> Self {
297        variant as u8 != 0
298    }
299}
300impl LOCK_ENABLE_R {
301    #[doc = "Get enumerated values variant"]
302    #[inline(always)]
303    pub const fn variant(&self) -> LOCK_ENABLE_A {
304        match self.bits {
305            false => LOCK_ENABLE_A::DISABLE,
306            true => LOCK_ENABLE_A::ENABLE,
307        }
308    }
309    #[doc = "`0`"]
310    #[inline(always)]
311    pub fn is_disable(&self) -> bool {
312        *self == LOCK_ENABLE_A::DISABLE
313    }
314    #[doc = "`1`"]
315    #[inline(always)]
316    pub fn is_enable(&self) -> bool {
317        *self == LOCK_ENABLE_A::ENABLE
318    }
319}
320#[doc = "Field `lock_enable` writer - Lock Enable"]
321pub type LOCK_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, LOCK_ENABLE_A>;
322impl<'a, REG> LOCK_ENABLE_W<'a, REG>
323where
324    REG: crate::Writable + crate::RegisterSpec,
325{
326    #[doc = "`0`"]
327    #[inline(always)]
328    pub fn disable(self) -> &'a mut crate::W<REG> {
329        self.variant(LOCK_ENABLE_A::DISABLE)
330    }
331    #[doc = "`1`"]
332    #[inline(always)]
333    pub fn enable(self) -> &'a mut crate::W<REG> {
334        self.variant(LOCK_ENABLE_A::ENABLE)
335    }
336}
337#[doc = "Field `pll_ldo_en` reader - LDO Enable"]
338pub type PLL_LDO_EN_R = crate::BitReader<PLL_LDO_EN_A>;
339#[doc = "LDO Enable\n\nValue on reset: 0"]
340#[derive(Clone, Copy, Debug, PartialEq, Eq)]
341pub enum PLL_LDO_EN_A {
342    #[doc = "0: `0`"]
343    DISABLE = 0,
344    #[doc = "1: `1`"]
345    ENABLE = 1,
346}
347impl From<PLL_LDO_EN_A> for bool {
348    #[inline(always)]
349    fn from(variant: PLL_LDO_EN_A) -> Self {
350        variant as u8 != 0
351    }
352}
353impl PLL_LDO_EN_R {
354    #[doc = "Get enumerated values variant"]
355    #[inline(always)]
356    pub const fn variant(&self) -> PLL_LDO_EN_A {
357        match self.bits {
358            false => PLL_LDO_EN_A::DISABLE,
359            true => PLL_LDO_EN_A::ENABLE,
360        }
361    }
362    #[doc = "`0`"]
363    #[inline(always)]
364    pub fn is_disable(&self) -> bool {
365        *self == PLL_LDO_EN_A::DISABLE
366    }
367    #[doc = "`1`"]
368    #[inline(always)]
369    pub fn is_enable(&self) -> bool {
370        *self == PLL_LDO_EN_A::ENABLE
371    }
372}
373#[doc = "Field `pll_ldo_en` writer - LDO Enable"]
374pub type PLL_LDO_EN_W<'a, REG> = crate::BitWriter<'a, REG, PLL_LDO_EN_A>;
375impl<'a, REG> PLL_LDO_EN_W<'a, REG>
376where
377    REG: crate::Writable + crate::RegisterSpec,
378{
379    #[doc = "`0`"]
380    #[inline(always)]
381    pub fn disable(self) -> &'a mut crate::W<REG> {
382        self.variant(PLL_LDO_EN_A::DISABLE)
383    }
384    #[doc = "`1`"]
385    #[inline(always)]
386    pub fn enable(self) -> &'a mut crate::W<REG> {
387        self.variant(PLL_LDO_EN_A::ENABLE)
388    }
389}
390#[doc = "Field `pll_en` reader - PLL Enable"]
391pub type PLL_EN_R = crate::BitReader<PLL_EN_A>;
392#[doc = "PLL Enable\n\nValue on reset: 0"]
393#[derive(Clone, Copy, Debug, PartialEq, Eq)]
394pub enum PLL_EN_A {
395    #[doc = "0: `0`"]
396    DISABLE = 0,
397    #[doc = "1: `1`"]
398    ENABLE = 1,
399}
400impl From<PLL_EN_A> for bool {
401    #[inline(always)]
402    fn from(variant: PLL_EN_A) -> Self {
403        variant as u8 != 0
404    }
405}
406impl PLL_EN_R {
407    #[doc = "Get enumerated values variant"]
408    #[inline(always)]
409    pub const fn variant(&self) -> PLL_EN_A {
410        match self.bits {
411            false => PLL_EN_A::DISABLE,
412            true => PLL_EN_A::ENABLE,
413        }
414    }
415    #[doc = "`0`"]
416    #[inline(always)]
417    pub fn is_disable(&self) -> bool {
418        *self == PLL_EN_A::DISABLE
419    }
420    #[doc = "`1`"]
421    #[inline(always)]
422    pub fn is_enable(&self) -> bool {
423        *self == PLL_EN_A::ENABLE
424    }
425}
426#[doc = "Field `pll_en` writer - PLL Enable"]
427pub type PLL_EN_W<'a, REG> = crate::BitWriter<'a, REG, PLL_EN_A>;
428impl<'a, REG> PLL_EN_W<'a, REG>
429where
430    REG: crate::Writable + crate::RegisterSpec,
431{
432    #[doc = "`0`"]
433    #[inline(always)]
434    pub fn disable(self) -> &'a mut crate::W<REG> {
435        self.variant(PLL_EN_A::DISABLE)
436    }
437    #[doc = "`1`"]
438    #[inline(always)]
439    pub fn enable(self) -> &'a mut crate::W<REG> {
440        self.variant(PLL_EN_A::ENABLE)
441    }
442}
443impl R {
444    #[doc = "Bit 0 - PLL Output Div D"]
445    #[inline(always)]
446    pub fn pll_output_div2(&self) -> PLL_OUTPUT_DIV2_R {
447        PLL_OUTPUT_DIV2_R::new((self.bits & 1) != 0)
448    }
449    #[doc = "Bit 1 - PLL Input Div M"]
450    #[inline(always)]
451    pub fn pll_input_div2(&self) -> PLL_INPUT_DIV2_R {
452        PLL_INPUT_DIV2_R::new(((self.bits >> 1) & 1) != 0)
453    }
454    #[doc = "Bit 5 - PLL Lock Level"]
455    #[inline(always)]
456    pub fn pll_lock_mdsel(&self) -> PLL_LOCK_MDSEL_R {
457        PLL_LOCK_MDSEL_R::new(((self.bits >> 5) & 1) != 0)
458    }
459    #[doc = "Bits 6:7 - PLL Unlock Level"]
460    #[inline(always)]
461    pub fn pll_unlock_mdsel(&self) -> PLL_UNLOCK_MDSEL_R {
462        PLL_UNLOCK_MDSEL_R::new(((self.bits >> 6) & 3) as u8)
463    }
464    #[doc = "Bits 8:15 - PLL N"]
465    #[inline(always)]
466    pub fn pll_n(&self) -> PLL_N_R {
467        PLL_N_R::new(((self.bits >> 8) & 0xff) as u8)
468    }
469    #[doc = "Bit 24 - PLL SDM Enable"]
470    #[inline(always)]
471    pub fn pll_sdm_en(&self) -> PLL_SDM_EN_R {
472        PLL_SDM_EN_R::new(((self.bits >> 24) & 1) != 0)
473    }
474    #[doc = "Bit 27 - PLL Output Gating Enable"]
475    #[inline(always)]
476    pub fn pll_output_gate(&self) -> PLL_OUTPUT_GATE_R {
477        PLL_OUTPUT_GATE_R::new(((self.bits >> 27) & 1) != 0)
478    }
479    #[doc = "Bit 28 - PLL Lock Status"]
480    #[inline(always)]
481    pub fn lock(&self) -> LOCK_R {
482        LOCK_R::new(((self.bits >> 28) & 1) != 0)
483    }
484    #[doc = "Bit 29 - Lock Enable"]
485    #[inline(always)]
486    pub fn lock_enable(&self) -> LOCK_ENABLE_R {
487        LOCK_ENABLE_R::new(((self.bits >> 29) & 1) != 0)
488    }
489    #[doc = "Bit 30 - LDO Enable"]
490    #[inline(always)]
491    pub fn pll_ldo_en(&self) -> PLL_LDO_EN_R {
492        PLL_LDO_EN_R::new(((self.bits >> 30) & 1) != 0)
493    }
494    #[doc = "Bit 31 - PLL Enable"]
495    #[inline(always)]
496    pub fn pll_en(&self) -> PLL_EN_R {
497        PLL_EN_R::new(((self.bits >> 31) & 1) != 0)
498    }
499}
500impl W {
501    #[doc = "Bit 0 - PLL Output Div D"]
502    #[inline(always)]
503    #[must_use]
504    pub fn pll_output_div2(&mut self) -> PLL_OUTPUT_DIV2_W<PLL_VIDEO0_CTRL_SPEC> {
505        PLL_OUTPUT_DIV2_W::new(self, 0)
506    }
507    #[doc = "Bit 1 - PLL Input Div M"]
508    #[inline(always)]
509    #[must_use]
510    pub fn pll_input_div2(&mut self) -> PLL_INPUT_DIV2_W<PLL_VIDEO0_CTRL_SPEC> {
511        PLL_INPUT_DIV2_W::new(self, 1)
512    }
513    #[doc = "Bit 5 - PLL Lock Level"]
514    #[inline(always)]
515    #[must_use]
516    pub fn pll_lock_mdsel(&mut self) -> PLL_LOCK_MDSEL_W<PLL_VIDEO0_CTRL_SPEC> {
517        PLL_LOCK_MDSEL_W::new(self, 5)
518    }
519    #[doc = "Bits 6:7 - PLL Unlock Level"]
520    #[inline(always)]
521    #[must_use]
522    pub fn pll_unlock_mdsel(&mut self) -> PLL_UNLOCK_MDSEL_W<PLL_VIDEO0_CTRL_SPEC> {
523        PLL_UNLOCK_MDSEL_W::new(self, 6)
524    }
525    #[doc = "Bits 8:15 - PLL N"]
526    #[inline(always)]
527    #[must_use]
528    pub fn pll_n(&mut self) -> PLL_N_W<PLL_VIDEO0_CTRL_SPEC> {
529        PLL_N_W::new(self, 8)
530    }
531    #[doc = "Bit 24 - PLL SDM Enable"]
532    #[inline(always)]
533    #[must_use]
534    pub fn pll_sdm_en(&mut self) -> PLL_SDM_EN_W<PLL_VIDEO0_CTRL_SPEC> {
535        PLL_SDM_EN_W::new(self, 24)
536    }
537    #[doc = "Bit 27 - PLL Output Gating Enable"]
538    #[inline(always)]
539    #[must_use]
540    pub fn pll_output_gate(&mut self) -> PLL_OUTPUT_GATE_W<PLL_VIDEO0_CTRL_SPEC> {
541        PLL_OUTPUT_GATE_W::new(self, 27)
542    }
543    #[doc = "Bit 29 - Lock Enable"]
544    #[inline(always)]
545    #[must_use]
546    pub fn lock_enable(&mut self) -> LOCK_ENABLE_W<PLL_VIDEO0_CTRL_SPEC> {
547        LOCK_ENABLE_W::new(self, 29)
548    }
549    #[doc = "Bit 30 - LDO Enable"]
550    #[inline(always)]
551    #[must_use]
552    pub fn pll_ldo_en(&mut self) -> PLL_LDO_EN_W<PLL_VIDEO0_CTRL_SPEC> {
553        PLL_LDO_EN_W::new(self, 30)
554    }
555    #[doc = "Bit 31 - PLL Enable"]
556    #[inline(always)]
557    #[must_use]
558    pub fn pll_en(&mut self) -> PLL_EN_W<PLL_VIDEO0_CTRL_SPEC> {
559        PLL_EN_W::new(self, 31)
560    }
561    #[doc = r" Writes raw bits to the register."]
562    #[doc = r""]
563    #[doc = r" # Safety"]
564    #[doc = r""]
565    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
566    #[inline(always)]
567    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
568        self.bits = bits;
569        self
570    }
571}
572#[doc = "PLL_VIDEO0 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_video0_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_video0_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
573pub struct PLL_VIDEO0_CTRL_SPEC;
574impl crate::RegisterSpec for PLL_VIDEO0_CTRL_SPEC {
575    type Ux = u32;
576}
577#[doc = "`read()` method returns [`pll_video0_ctrl::R`](R) reader structure"]
578impl crate::Readable for PLL_VIDEO0_CTRL_SPEC {}
579#[doc = "`write(|w| ..)` method takes [`pll_video0_ctrl::W`](W) writer structure"]
580impl crate::Writable for PLL_VIDEO0_CTRL_SPEC {
581    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
582    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
583}
584#[doc = "`reset()` method sets pll_video0_ctrl to value 0"]
585impl crate::Resettable for PLL_VIDEO0_CTRL_SPEC {
586    const RESET_VALUE: Self::Ux = 0;
587}
d1_pac/ccu/pll_video0_ctrl.rs

d1_pac/ccu/
pll_video0_ctrl.rs
