d1_pac/ccu/
pll_cpu_tun.rs

1#[doc = "Register `pll_cpu_tun` reader"]
2pub type R = crate::R<PLL_CPU_TUN_SPEC>;
3#[doc = "Register `pll_cpu_tun` writer"]
4pub type W = crate::W<PLL_CPU_TUN_SPEC>;
5#[doc = "Field `pll_b_out` reader - PLL-B-OUT \\[6:0\\] for verify"]
6pub type PLL_B_OUT_R = crate::FieldReader;
7#[doc = "Field `pll_reg_od1` reader - PLL-REG-OD1 for verify"]
8pub type PLL_REG_OD1_R = crate::BitReader;
9#[doc = "Field `pll_reg_od1` writer - PLL-REG-OD1 for verify"]
10pub type PLL_REG_OD1_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `pll_b_in` reader - PLL-B-IN \\[6:0\\] for verify"]
12pub type PLL_B_IN_R = crate::FieldReader;
13#[doc = "Field `pll_b_in` writer - PLL-B-IN \\[6:0\\] for verify"]
14pub type PLL_B_IN_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
15#[doc = "Field `pll_reg_od` reader - PLL-REG-OD0 for verify"]
16pub type PLL_REG_OD_R = crate::BitReader;
17#[doc = "Field `pll_reg_od` writer - PLL-REG-OD0 for verify"]
18pub type PLL_REG_OD_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `pll_cnt_int` reader - Counter initial control"]
20pub type PLL_CNT_INT_R = crate::FieldReader;
21#[doc = "Field `pll_cnt_int` writer - Counter initial control"]
22pub type PLL_CNT_INT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
23#[doc = "Field `pll_vco_gain` reader - KVCO gain control"]
24pub type PLL_VCO_GAIN_R = crate::FieldReader;
25#[doc = "Field `pll_vco_gain` writer - KVCO gain control"]
26pub type PLL_VCO_GAIN_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
27#[doc = "Field `pll_vco` reader - VCO range control"]
28pub type PLL_VCO_R = crate::FieldReader;
29#[doc = "Field `pll_vco` writer - VCO range control"]
30pub type PLL_VCO_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
31impl R {
32    #[doc = "Bits 0:6 - PLL-B-OUT \\[6:0\\] for verify"]
33    #[inline(always)]
34    pub fn pll_b_out(&self) -> PLL_B_OUT_R {
35        PLL_B_OUT_R::new((self.bits & 0x7f) as u8)
36    }
37    #[doc = "Bit 7 - PLL-REG-OD1 for verify"]
38    #[inline(always)]
39    pub fn pll_reg_od1(&self) -> PLL_REG_OD1_R {
40        PLL_REG_OD1_R::new(((self.bits >> 7) & 1) != 0)
41    }
42    #[doc = "Bits 8:14 - PLL-B-IN \\[6:0\\] for verify"]
43    #[inline(always)]
44    pub fn pll_b_in(&self) -> PLL_B_IN_R {
45        PLL_B_IN_R::new(((self.bits >> 8) & 0x7f) as u8)
46    }
47    #[doc = "Bit 15 - PLL-REG-OD0 for verify"]
48    #[inline(always)]
49    pub fn pll_reg_od(&self) -> PLL_REG_OD_R {
50        PLL_REG_OD_R::new(((self.bits >> 15) & 1) != 0)
51    }
52    #[doc = "Bits 16:22 - Counter initial control"]
53    #[inline(always)]
54    pub fn pll_cnt_int(&self) -> PLL_CNT_INT_R {
55        PLL_CNT_INT_R::new(((self.bits >> 16) & 0x7f) as u8)
56    }
57    #[doc = "Bits 24:26 - KVCO gain control"]
58    #[inline(always)]
59    pub fn pll_vco_gain(&self) -> PLL_VCO_GAIN_R {
60        PLL_VCO_GAIN_R::new(((self.bits >> 24) & 7) as u8)
61    }
62    #[doc = "Bits 28:30 - VCO range control"]
63    #[inline(always)]
64    pub fn pll_vco(&self) -> PLL_VCO_R {
65        PLL_VCO_R::new(((self.bits >> 28) & 7) as u8)
66    }
67}
68impl W {
69    #[doc = "Bit 7 - PLL-REG-OD1 for verify"]
70    #[inline(always)]
71    #[must_use]
72    pub fn pll_reg_od1(&mut self) -> PLL_REG_OD1_W<PLL_CPU_TUN_SPEC> {
73        PLL_REG_OD1_W::new(self, 7)
74    }
75    #[doc = "Bits 8:14 - PLL-B-IN \\[6:0\\] for verify"]
76    #[inline(always)]
77    #[must_use]
78    pub fn pll_b_in(&mut self) -> PLL_B_IN_W<PLL_CPU_TUN_SPEC> {
79        PLL_B_IN_W::new(self, 8)
80    }
81    #[doc = "Bit 15 - PLL-REG-OD0 for verify"]
82    #[inline(always)]
83    #[must_use]
84    pub fn pll_reg_od(&mut self) -> PLL_REG_OD_W<PLL_CPU_TUN_SPEC> {
85        PLL_REG_OD_W::new(self, 15)
86    }
87    #[doc = "Bits 16:22 - Counter initial control"]
88    #[inline(always)]
89    #[must_use]
90    pub fn pll_cnt_int(&mut self) -> PLL_CNT_INT_W<PLL_CPU_TUN_SPEC> {
91        PLL_CNT_INT_W::new(self, 16)
92    }
93    #[doc = "Bits 24:26 - KVCO gain control"]
94    #[inline(always)]
95    #[must_use]
96    pub fn pll_vco_gain(&mut self) -> PLL_VCO_GAIN_W<PLL_CPU_TUN_SPEC> {
97        PLL_VCO_GAIN_W::new(self, 24)
98    }
99    #[doc = "Bits 28:30 - VCO range control"]
100    #[inline(always)]
101    #[must_use]
102    pub fn pll_vco(&mut self) -> PLL_VCO_W<PLL_CPU_TUN_SPEC> {
103        PLL_VCO_W::new(self, 28)
104    }
105    #[doc = r" Writes raw bits to the register."]
106    #[doc = r""]
107    #[doc = r" # Safety"]
108    #[doc = r""]
109    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
110    #[inline(always)]
111    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
112        self.bits = bits;
113        self
114    }
115}
116#[doc = "PLL_CPU Tuning Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_cpu_tun::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_cpu_tun::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
117pub struct PLL_CPU_TUN_SPEC;
118impl crate::RegisterSpec for PLL_CPU_TUN_SPEC {
119    type Ux = u32;
120}
121#[doc = "`read()` method returns [`pll_cpu_tun::R`](R) reader structure"]
122impl crate::Readable for PLL_CPU_TUN_SPEC {}
123#[doc = "`write(|w| ..)` method takes [`pll_cpu_tun::W`](W) writer structure"]
124impl crate::Writable for PLL_CPU_TUN_SPEC {
125    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
126    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
127}
128#[doc = "`reset()` method sets pll_cpu_tun to value 0"]
129impl crate::Resettable for PLL_CPU_TUN_SPEC {
130    const RESET_VALUE: Self::Ux = 0;
131}
d1_pac/ccu/pll_cpu_tun.rs

d1_pac/ccu/
pll_cpu_tun.rs
