d1_pac/ccu/
pll_cpu_bias.rs

1#[doc = "Register `pll_cpu_bias` reader"]
2pub type R = crate::R<PLL_CPU_BIAS_SPEC>;
3#[doc = "Register `pll_cpu_bias` writer"]
4pub type W = crate::W<PLL_CPU_BIAS_SPEC>;
5#[doc = "Field `pll_cp` reader - PLL current bias control"]
6pub type PLL_CP_R = crate::FieldReader;
7#[doc = "Field `pll_cp` writer - PLL current bias control"]
8pub type PLL_CP_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `pll_vco_rst_in` reader - VCO reset in"]
10pub type PLL_VCO_RST_IN_R = crate::BitReader;
11#[doc = "Field `pll_vco_rst_in` writer - VCO reset in"]
12pub type PLL_VCO_RST_IN_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bits 16:20 - PLL current bias control"]
15    #[inline(always)]
16    pub fn pll_cp(&self) -> PLL_CP_R {
17        PLL_CP_R::new(((self.bits >> 16) & 0x1f) as u8)
18    }
19    #[doc = "Bit 31 - VCO reset in"]
20    #[inline(always)]
21    pub fn pll_vco_rst_in(&self) -> PLL_VCO_RST_IN_R {
22        PLL_VCO_RST_IN_R::new(((self.bits >> 31) & 1) != 0)
23    }
24}
25impl W {
26    #[doc = "Bits 16:20 - PLL current bias control"]
27    #[inline(always)]
28    #[must_use]
29    pub fn pll_cp(&mut self) -> PLL_CP_W<PLL_CPU_BIAS_SPEC> {
30        PLL_CP_W::new(self, 16)
31    }
32    #[doc = "Bit 31 - VCO reset in"]
33    #[inline(always)]
34    #[must_use]
35    pub fn pll_vco_rst_in(&mut self) -> PLL_VCO_RST_IN_W<PLL_CPU_BIAS_SPEC> {
36        PLL_VCO_RST_IN_W::new(self, 31)
37    }
38    #[doc = r" Writes raw bits to the register."]
39    #[doc = r""]
40    #[doc = r" # Safety"]
41    #[doc = r""]
42    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
43    #[inline(always)]
44    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
45        self.bits = bits;
46        self
47    }
48}
49#[doc = "PLL_CPU Bias Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_cpu_bias::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_cpu_bias::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
50pub struct PLL_CPU_BIAS_SPEC;
51impl crate::RegisterSpec for PLL_CPU_BIAS_SPEC {
52    type Ux = u32;
53}
54#[doc = "`read()` method returns [`pll_cpu_bias::R`](R) reader structure"]
55impl crate::Readable for PLL_CPU_BIAS_SPEC {}
56#[doc = "`write(|w| ..)` method takes [`pll_cpu_bias::W`](W) writer structure"]
57impl crate::Writable for PLL_CPU_BIAS_SPEC {
58    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
59    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
60}
61#[doc = "`reset()` method sets pll_cpu_bias to value 0"]
62impl crate::Resettable for PLL_CPU_BIAS_SPEC {
63    const RESET_VALUE: Self::Ux = 0;
64}
d1_pac/ccu/pll_cpu_bias.rs

d1_pac/ccu/
pll_cpu_bias.rs
