d1_pac/ccu/
pll_audio1_pat0_ctrl.rs

1#[doc = "Register `pll_audio1_pat0_ctrl` reader"]
2pub type R = crate::R<PLL_AUDIO1_PAT0_CTRL_SPEC>;
3#[doc = "Register `pll_audio1_pat0_ctrl` writer"]
4pub type W = crate::W<PLL_AUDIO1_PAT0_CTRL_SPEC>;
5#[doc = "Field `wave_bot` reader - Wave Bottom"]
6pub type WAVE_BOT_R = crate::FieldReader<u32>;
7#[doc = "Field `wave_bot` writer - Wave Bottom"]
8pub type WAVE_BOT_W<'a, REG> = crate::FieldWriter<'a, REG, 17, u32>;
9#[doc = "Field `freq` reader - Frequency"]
10pub type FREQ_R = crate::FieldReader<FREQ_A>;
11#[doc = "Frequency\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13#[repr(u8)]
14pub enum FREQ_A {
15    #[doc = "0: `0`"]
16    F_31_5_K = 0,
17    #[doc = "1: `1`"]
18    F_32_K = 1,
19    #[doc = "2: `10`"]
20    F_32_5_K = 2,
21    #[doc = "3: `11`"]
22    F_33_K = 3,
23}
24impl From<FREQ_A> for u8 {
25    #[inline(always)]
26    fn from(variant: FREQ_A) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for FREQ_A {
31    type Ux = u8;
32}
33impl FREQ_R {
34    #[doc = "Get enumerated values variant"]
35    #[inline(always)]
36    pub const fn variant(&self) -> FREQ_A {
37        match self.bits {
38            0 => FREQ_A::F_31_5_K,
39            1 => FREQ_A::F_32_K,
40            2 => FREQ_A::F_32_5_K,
41            3 => FREQ_A::F_33_K,
42            _ => unreachable!(),
43        }
44    }
45    #[doc = "`0`"]
46    #[inline(always)]
47    pub fn is_f_31_5_k(&self) -> bool {
48        *self == FREQ_A::F_31_5_K
49    }
50    #[doc = "`1`"]
51    #[inline(always)]
52    pub fn is_f_32_k(&self) -> bool {
53        *self == FREQ_A::F_32_K
54    }
55    #[doc = "`10`"]
56    #[inline(always)]
57    pub fn is_f_32_5_k(&self) -> bool {
58        *self == FREQ_A::F_32_5_K
59    }
60    #[doc = "`11`"]
61    #[inline(always)]
62    pub fn is_f_33_k(&self) -> bool {
63        *self == FREQ_A::F_33_K
64    }
65}
66#[doc = "Field `freq` writer - Frequency"]
67pub type FREQ_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, FREQ_A>;
68impl<'a, REG> FREQ_W<'a, REG>
69where
70    REG: crate::Writable + crate::RegisterSpec,
71    REG::Ux: From<u8>,
72{
73    #[doc = "`0`"]
74    #[inline(always)]
75    pub fn f_31_5_k(self) -> &'a mut crate::W<REG> {
76        self.variant(FREQ_A::F_31_5_K)
77    }
78    #[doc = "`1`"]
79    #[inline(always)]
80    pub fn f_32_k(self) -> &'a mut crate::W<REG> {
81        self.variant(FREQ_A::F_32_K)
82    }
83    #[doc = "`10`"]
84    #[inline(always)]
85    pub fn f_32_5_k(self) -> &'a mut crate::W<REG> {
86        self.variant(FREQ_A::F_32_5_K)
87    }
88    #[doc = "`11`"]
89    #[inline(always)]
90    pub fn f_33_k(self) -> &'a mut crate::W<REG> {
91        self.variant(FREQ_A::F_33_K)
92    }
93}
94#[doc = "Field `sdm_clk_sel` reader - SDM Clock Select"]
95pub type SDM_CLK_SEL_R = crate::BitReader<SDM_CLK_SEL_A>;
96#[doc = "SDM Clock Select\n\nValue on reset: 0"]
97#[derive(Clone, Copy, Debug, PartialEq, Eq)]
98pub enum SDM_CLK_SEL_A {
99    #[doc = "0: `0`"]
100    F_24_M = 0,
101    #[doc = "1: `1`"]
102    F_12_M = 1,
103}
104impl From<SDM_CLK_SEL_A> for bool {
105    #[inline(always)]
106    fn from(variant: SDM_CLK_SEL_A) -> Self {
107        variant as u8 != 0
108    }
109}
110impl SDM_CLK_SEL_R {
111    #[doc = "Get enumerated values variant"]
112    #[inline(always)]
113    pub const fn variant(&self) -> SDM_CLK_SEL_A {
114        match self.bits {
115            false => SDM_CLK_SEL_A::F_24_M,
116            true => SDM_CLK_SEL_A::F_12_M,
117        }
118    }
119    #[doc = "`0`"]
120    #[inline(always)]
121    pub fn is_f_24_m(&self) -> bool {
122        *self == SDM_CLK_SEL_A::F_24_M
123    }
124    #[doc = "`1`"]
125    #[inline(always)]
126    pub fn is_f_12_m(&self) -> bool {
127        *self == SDM_CLK_SEL_A::F_12_M
128    }
129}
130#[doc = "Field `sdm_clk_sel` writer - SDM Clock Select"]
131pub type SDM_CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG, SDM_CLK_SEL_A>;
132impl<'a, REG> SDM_CLK_SEL_W<'a, REG>
133where
134    REG: crate::Writable + crate::RegisterSpec,
135{
136    #[doc = "`0`"]
137    #[inline(always)]
138    pub fn f_24_m(self) -> &'a mut crate::W<REG> {
139        self.variant(SDM_CLK_SEL_A::F_24_M)
140    }
141    #[doc = "`1`"]
142    #[inline(always)]
143    pub fn f_12_m(self) -> &'a mut crate::W<REG> {
144        self.variant(SDM_CLK_SEL_A::F_12_M)
145    }
146}
147#[doc = "Field `wave_step` reader - Wave Step"]
148pub type WAVE_STEP_R = crate::FieldReader<u16>;
149#[doc = "Field `wave_step` writer - Wave Step"]
150pub type WAVE_STEP_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
151#[doc = "Field `spr_freq_mode` reader - Spread Frequency Mode"]
152pub type SPR_FREQ_MODE_R = crate::FieldReader<SPR_FREQ_MODE_A>;
153#[doc = "Spread Frequency Mode\n\nValue on reset: 0"]
154#[derive(Clone, Copy, Debug, PartialEq, Eq)]
155#[repr(u8)]
156pub enum SPR_FREQ_MODE_A {
157    #[doc = "0: `0`"]
158    DC0 = 0,
159    #[doc = "1: `1`"]
160    DC1 = 1,
161    #[doc = "2: `10`"]
162    TRIANGULAR_1 = 2,
163    #[doc = "3: `11`"]
164    TRIANGULAR_N = 3,
165}
166impl From<SPR_FREQ_MODE_A> for u8 {
167    #[inline(always)]
168    fn from(variant: SPR_FREQ_MODE_A) -> Self {
169        variant as _
170    }
171}
172impl crate::FieldSpec for SPR_FREQ_MODE_A {
173    type Ux = u8;
174}
175impl SPR_FREQ_MODE_R {
176    #[doc = "Get enumerated values variant"]
177    #[inline(always)]
178    pub const fn variant(&self) -> SPR_FREQ_MODE_A {
179        match self.bits {
180            0 => SPR_FREQ_MODE_A::DC0,
181            1 => SPR_FREQ_MODE_A::DC1,
182            2 => SPR_FREQ_MODE_A::TRIANGULAR_1,
183            3 => SPR_FREQ_MODE_A::TRIANGULAR_N,
184            _ => unreachable!(),
185        }
186    }
187    #[doc = "`0`"]
188    #[inline(always)]
189    pub fn is_dc0(&self) -> bool {
190        *self == SPR_FREQ_MODE_A::DC0
191    }
192    #[doc = "`1`"]
193    #[inline(always)]
194    pub fn is_dc1(&self) -> bool {
195        *self == SPR_FREQ_MODE_A::DC1
196    }
197    #[doc = "`10`"]
198    #[inline(always)]
199    pub fn is_triangular_1(&self) -> bool {
200        *self == SPR_FREQ_MODE_A::TRIANGULAR_1
201    }
202    #[doc = "`11`"]
203    #[inline(always)]
204    pub fn is_triangular_n(&self) -> bool {
205        *self == SPR_FREQ_MODE_A::TRIANGULAR_N
206    }
207}
208#[doc = "Field `spr_freq_mode` writer - Spread Frequency Mode"]
209pub type SPR_FREQ_MODE_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, SPR_FREQ_MODE_A>;
210impl<'a, REG> SPR_FREQ_MODE_W<'a, REG>
211where
212    REG: crate::Writable + crate::RegisterSpec,
213    REG::Ux: From<u8>,
214{
215    #[doc = "`0`"]
216    #[inline(always)]
217    pub fn dc0(self) -> &'a mut crate::W<REG> {
218        self.variant(SPR_FREQ_MODE_A::DC0)
219    }
220    #[doc = "`1`"]
221    #[inline(always)]
222    pub fn dc1(self) -> &'a mut crate::W<REG> {
223        self.variant(SPR_FREQ_MODE_A::DC1)
224    }
225    #[doc = "`10`"]
226    #[inline(always)]
227    pub fn triangular_1(self) -> &'a mut crate::W<REG> {
228        self.variant(SPR_FREQ_MODE_A::TRIANGULAR_1)
229    }
230    #[doc = "`11`"]
231    #[inline(always)]
232    pub fn triangular_n(self) -> &'a mut crate::W<REG> {
233        self.variant(SPR_FREQ_MODE_A::TRIANGULAR_N)
234    }
235}
236#[doc = "Field `sig_delt_pat_en` reader - Sigma-Delta Pattern Enable"]
237pub type SIG_DELT_PAT_EN_R = crate::BitReader;
238#[doc = "Field `sig_delt_pat_en` writer - Sigma-Delta Pattern Enable"]
239pub type SIG_DELT_PAT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
240impl R {
241    #[doc = "Bits 0:16 - Wave Bottom"]
242    #[inline(always)]
243    pub fn wave_bot(&self) -> WAVE_BOT_R {
244        WAVE_BOT_R::new(self.bits & 0x0001_ffff)
245    }
246    #[doc = "Bits 17:18 - Frequency"]
247    #[inline(always)]
248    pub fn freq(&self) -> FREQ_R {
249        FREQ_R::new(((self.bits >> 17) & 3) as u8)
250    }
251    #[doc = "Bit 19 - SDM Clock Select"]
252    #[inline(always)]
253    pub fn sdm_clk_sel(&self) -> SDM_CLK_SEL_R {
254        SDM_CLK_SEL_R::new(((self.bits >> 19) & 1) != 0)
255    }
256    #[doc = "Bits 20:28 - Wave Step"]
257    #[inline(always)]
258    pub fn wave_step(&self) -> WAVE_STEP_R {
259        WAVE_STEP_R::new(((self.bits >> 20) & 0x01ff) as u16)
260    }
261    #[doc = "Bits 29:30 - Spread Frequency Mode"]
262    #[inline(always)]
263    pub fn spr_freq_mode(&self) -> SPR_FREQ_MODE_R {
264        SPR_FREQ_MODE_R::new(((self.bits >> 29) & 3) as u8)
265    }
266    #[doc = "Bit 31 - Sigma-Delta Pattern Enable"]
267    #[inline(always)]
268    pub fn sig_delt_pat_en(&self) -> SIG_DELT_PAT_EN_R {
269        SIG_DELT_PAT_EN_R::new(((self.bits >> 31) & 1) != 0)
270    }
271}
272impl W {
273    #[doc = "Bits 0:16 - Wave Bottom"]
274    #[inline(always)]
275    #[must_use]
276    pub fn wave_bot(&mut self) -> WAVE_BOT_W<PLL_AUDIO1_PAT0_CTRL_SPEC> {
277        WAVE_BOT_W::new(self, 0)
278    }
279    #[doc = "Bits 17:18 - Frequency"]
280    #[inline(always)]
281    #[must_use]
282    pub fn freq(&mut self) -> FREQ_W<PLL_AUDIO1_PAT0_CTRL_SPEC> {
283        FREQ_W::new(self, 17)
284    }
285    #[doc = "Bit 19 - SDM Clock Select"]
286    #[inline(always)]
287    #[must_use]
288    pub fn sdm_clk_sel(&mut self) -> SDM_CLK_SEL_W<PLL_AUDIO1_PAT0_CTRL_SPEC> {
289        SDM_CLK_SEL_W::new(self, 19)
290    }
291    #[doc = "Bits 20:28 - Wave Step"]
292    #[inline(always)]
293    #[must_use]
294    pub fn wave_step(&mut self) -> WAVE_STEP_W<PLL_AUDIO1_PAT0_CTRL_SPEC> {
295        WAVE_STEP_W::new(self, 20)
296    }
297    #[doc = "Bits 29:30 - Spread Frequency Mode"]
298    #[inline(always)]
299    #[must_use]
300    pub fn spr_freq_mode(&mut self) -> SPR_FREQ_MODE_W<PLL_AUDIO1_PAT0_CTRL_SPEC> {
301        SPR_FREQ_MODE_W::new(self, 29)
302    }
303    #[doc = "Bit 31 - Sigma-Delta Pattern Enable"]
304    #[inline(always)]
305    #[must_use]
306    pub fn sig_delt_pat_en(&mut self) -> SIG_DELT_PAT_EN_W<PLL_AUDIO1_PAT0_CTRL_SPEC> {
307        SIG_DELT_PAT_EN_W::new(self, 31)
308    }
309    #[doc = r" Writes raw bits to the register."]
310    #[doc = r""]
311    #[doc = r" # Safety"]
312    #[doc = r""]
313    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
314    #[inline(always)]
315    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
316        self.bits = bits;
317        self
318    }
319}
320#[doc = "PLL_AUDIO1 Pattern0 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_audio1_pat0_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_audio1_pat0_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
321pub struct PLL_AUDIO1_PAT0_CTRL_SPEC;
322impl crate::RegisterSpec for PLL_AUDIO1_PAT0_CTRL_SPEC {
323    type Ux = u32;
324}
325#[doc = "`read()` method returns [`pll_audio1_pat0_ctrl::R`](R) reader structure"]
326impl crate::Readable for PLL_AUDIO1_PAT0_CTRL_SPEC {}
327#[doc = "`write(|w| ..)` method takes [`pll_audio1_pat0_ctrl::W`](W) writer structure"]
328impl crate::Writable for PLL_AUDIO1_PAT0_CTRL_SPEC {
329    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
330    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
331}
332#[doc = "`reset()` method sets pll_audio1_pat0_ctrl to value 0"]
333impl crate::Resettable for PLL_AUDIO1_PAT0_CTRL_SPEC {
334    const RESET_VALUE: Self::Ux = 0;
335}
d1_pac/ccu/pll_audio1_pat0_ctrl.rs

d1_pac/ccu/
pll_audio1_pat0_ctrl.rs
