d1_pac/ccu/
pll_audio0_ctrl.rs

1#[doc = "Register `pll_audio0_ctrl` reader"]
2pub type R = crate::R<PLL_AUDIO0_CTRL_SPEC>;
3#[doc = "Register `pll_audio0_ctrl` writer"]
4pub type W = crate::W<PLL_AUDIO0_CTRL_SPEC>;
5#[doc = "Field `pll_output_div2` reader - PLL Output Div M0"]
6pub type PLL_OUTPUT_DIV2_R = crate::BitReader;
7#[doc = "Field `pll_output_div2` writer - PLL Output Div M0"]
8pub type PLL_OUTPUT_DIV2_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `pll_input_div2` reader - PLL Input Div M1"]
10pub type PLL_INPUT_DIV2_R = crate::BitReader;
11#[doc = "Field `pll_input_div2` writer - PLL Input Div M1"]
12pub type PLL_INPUT_DIV2_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `pll_lock_mdsel` reader - PLL Lock Level"]
14pub type PLL_LOCK_MDSEL_R = crate::BitReader<PLL_LOCK_MDSEL_A>;
15#[doc = "PLL Lock Level\n\nValue on reset: 0"]
16#[derive(Clone, Copy, Debug, PartialEq, Eq)]
17pub enum PLL_LOCK_MDSEL_A {
18    #[doc = "0: `0`"]
19    CC_24_26 = 0,
20    #[doc = "1: `1`"]
21    CC_23_27 = 1,
22}
23impl From<PLL_LOCK_MDSEL_A> for bool {
24    #[inline(always)]
25    fn from(variant: PLL_LOCK_MDSEL_A) -> Self {
26        variant as u8 != 0
27    }
28}
29impl PLL_LOCK_MDSEL_R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> PLL_LOCK_MDSEL_A {
33        match self.bits {
34            false => PLL_LOCK_MDSEL_A::CC_24_26,
35            true => PLL_LOCK_MDSEL_A::CC_23_27,
36        }
37    }
38    #[doc = "`0`"]
39    #[inline(always)]
40    pub fn is_cc_24_26(&self) -> bool {
41        *self == PLL_LOCK_MDSEL_A::CC_24_26
42    }
43    #[doc = "`1`"]
44    #[inline(always)]
45    pub fn is_cc_23_27(&self) -> bool {
46        *self == PLL_LOCK_MDSEL_A::CC_23_27
47    }
48}
49#[doc = "Field `pll_lock_mdsel` writer - PLL Lock Level"]
50pub type PLL_LOCK_MDSEL_W<'a, REG> = crate::BitWriter<'a, REG, PLL_LOCK_MDSEL_A>;
51impl<'a, REG> PLL_LOCK_MDSEL_W<'a, REG>
52where
53    REG: crate::Writable + crate::RegisterSpec,
54{
55    #[doc = "`0`"]
56    #[inline(always)]
57    pub fn cc_24_26(self) -> &'a mut crate::W<REG> {
58        self.variant(PLL_LOCK_MDSEL_A::CC_24_26)
59    }
60    #[doc = "`1`"]
61    #[inline(always)]
62    pub fn cc_23_27(self) -> &'a mut crate::W<REG> {
63        self.variant(PLL_LOCK_MDSEL_A::CC_23_27)
64    }
65}
66#[doc = "Field `pll_unlock_mdsel` reader - PLL Unlock Level"]
67pub type PLL_UNLOCK_MDSEL_R = crate::FieldReader<PLL_UNLOCK_MDSEL_A>;
68#[doc = "PLL Unlock Level\n\nValue on reset: 0"]
69#[derive(Clone, Copy, Debug, PartialEq, Eq)]
70#[repr(u8)]
71pub enum PLL_UNLOCK_MDSEL_A {
72    #[doc = "0: `0`"]
73    CC_21_29 = 0,
74    #[doc = "1: `1`"]
75    CC_22_28 = 1,
76    #[doc = "2: `10`"]
77    CC_20_30 = 2,
78}
79impl From<PLL_UNLOCK_MDSEL_A> for u8 {
80    #[inline(always)]
81    fn from(variant: PLL_UNLOCK_MDSEL_A) -> Self {
82        variant as _
83    }
84}
85impl crate::FieldSpec for PLL_UNLOCK_MDSEL_A {
86    type Ux = u8;
87}
88impl PLL_UNLOCK_MDSEL_R {
89    #[doc = "Get enumerated values variant"]
90    #[inline(always)]
91    pub const fn variant(&self) -> Option<PLL_UNLOCK_MDSEL_A> {
92        match self.bits {
93            0 => Some(PLL_UNLOCK_MDSEL_A::CC_21_29),
94            1 => Some(PLL_UNLOCK_MDSEL_A::CC_22_28),
95            2 => Some(PLL_UNLOCK_MDSEL_A::CC_20_30),
96            _ => None,
97        }
98    }
99    #[doc = "`0`"]
100    #[inline(always)]
101    pub fn is_cc_21_29(&self) -> bool {
102        *self == PLL_UNLOCK_MDSEL_A::CC_21_29
103    }
104    #[doc = "`1`"]
105    #[inline(always)]
106    pub fn is_cc_22_28(&self) -> bool {
107        *self == PLL_UNLOCK_MDSEL_A::CC_22_28
108    }
109    #[doc = "`10`"]
110    #[inline(always)]
111    pub fn is_cc_20_30(&self) -> bool {
112        *self == PLL_UNLOCK_MDSEL_A::CC_20_30
113    }
114}
115#[doc = "Field `pll_unlock_mdsel` writer - PLL Unlock Level"]
116pub type PLL_UNLOCK_MDSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PLL_UNLOCK_MDSEL_A>;
117impl<'a, REG> PLL_UNLOCK_MDSEL_W<'a, REG>
118where
119    REG: crate::Writable + crate::RegisterSpec,
120    REG::Ux: From<u8>,
121{
122    #[doc = "`0`"]
123    #[inline(always)]
124    pub fn cc_21_29(self) -> &'a mut crate::W<REG> {
125        self.variant(PLL_UNLOCK_MDSEL_A::CC_21_29)
126    }
127    #[doc = "`1`"]
128    #[inline(always)]
129    pub fn cc_22_28(self) -> &'a mut crate::W<REG> {
130        self.variant(PLL_UNLOCK_MDSEL_A::CC_22_28)
131    }
132    #[doc = "`10`"]
133    #[inline(always)]
134    pub fn cc_20_30(self) -> &'a mut crate::W<REG> {
135        self.variant(PLL_UNLOCK_MDSEL_A::CC_20_30)
136    }
137}
138#[doc = "Field `pll_n` reader - PLL N"]
139pub type PLL_N_R = crate::FieldReader;
140#[doc = "Field `pll_n` writer - PLL N"]
141pub type PLL_N_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
142#[doc = "Field `pll_p` reader - PLL Post-div P"]
143pub type PLL_P_R = crate::FieldReader;
144#[doc = "Field `pll_p` writer - PLL Post-div P"]
145pub type PLL_P_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
146#[doc = "Field `pll_sdm_en` reader - PLL SDM Enable"]
147pub type PLL_SDM_EN_R = crate::BitReader<PLL_SDM_EN_A>;
148#[doc = "PLL SDM Enable\n\nValue on reset: 0"]
149#[derive(Clone, Copy, Debug, PartialEq, Eq)]
150pub enum PLL_SDM_EN_A {
151    #[doc = "0: `0`"]
152    DISABLE = 0,
153    #[doc = "1: `1`"]
154    ENABLE = 1,
155}
156impl From<PLL_SDM_EN_A> for bool {
157    #[inline(always)]
158    fn from(variant: PLL_SDM_EN_A) -> Self {
159        variant as u8 != 0
160    }
161}
162impl PLL_SDM_EN_R {
163    #[doc = "Get enumerated values variant"]
164    #[inline(always)]
165    pub const fn variant(&self) -> PLL_SDM_EN_A {
166        match self.bits {
167            false => PLL_SDM_EN_A::DISABLE,
168            true => PLL_SDM_EN_A::ENABLE,
169        }
170    }
171    #[doc = "`0`"]
172    #[inline(always)]
173    pub fn is_disable(&self) -> bool {
174        *self == PLL_SDM_EN_A::DISABLE
175    }
176    #[doc = "`1`"]
177    #[inline(always)]
178    pub fn is_enable(&self) -> bool {
179        *self == PLL_SDM_EN_A::ENABLE
180    }
181}
182#[doc = "Field `pll_sdm_en` writer - PLL SDM Enable"]
183pub type PLL_SDM_EN_W<'a, REG> = crate::BitWriter<'a, REG, PLL_SDM_EN_A>;
184impl<'a, REG> PLL_SDM_EN_W<'a, REG>
185where
186    REG: crate::Writable + crate::RegisterSpec,
187{
188    #[doc = "`0`"]
189    #[inline(always)]
190    pub fn disable(self) -> &'a mut crate::W<REG> {
191        self.variant(PLL_SDM_EN_A::DISABLE)
192    }
193    #[doc = "`1`"]
194    #[inline(always)]
195    pub fn enable(self) -> &'a mut crate::W<REG> {
196        self.variant(PLL_SDM_EN_A::ENABLE)
197    }
198}
199#[doc = "Field `pll_output_gate` reader - PLL Output Gating Enable"]
200pub type PLL_OUTPUT_GATE_R = crate::BitReader<PLL_OUTPUT_GATE_A>;
201#[doc = "PLL Output Gating Enable\n\nValue on reset: 0"]
202#[derive(Clone, Copy, Debug, PartialEq, Eq)]
203pub enum PLL_OUTPUT_GATE_A {
204    #[doc = "0: `0`"]
205    DISABLE = 0,
206    #[doc = "1: `1`"]
207    ENABLE = 1,
208}
209impl From<PLL_OUTPUT_GATE_A> for bool {
210    #[inline(always)]
211    fn from(variant: PLL_OUTPUT_GATE_A) -> Self {
212        variant as u8 != 0
213    }
214}
215impl PLL_OUTPUT_GATE_R {
216    #[doc = "Get enumerated values variant"]
217    #[inline(always)]
218    pub const fn variant(&self) -> PLL_OUTPUT_GATE_A {
219        match self.bits {
220            false => PLL_OUTPUT_GATE_A::DISABLE,
221            true => PLL_OUTPUT_GATE_A::ENABLE,
222        }
223    }
224    #[doc = "`0`"]
225    #[inline(always)]
226    pub fn is_disable(&self) -> bool {
227        *self == PLL_OUTPUT_GATE_A::DISABLE
228    }
229    #[doc = "`1`"]
230    #[inline(always)]
231    pub fn is_enable(&self) -> bool {
232        *self == PLL_OUTPUT_GATE_A::ENABLE
233    }
234}
235#[doc = "Field `pll_output_gate` writer - PLL Output Gating Enable"]
236pub type PLL_OUTPUT_GATE_W<'a, REG> = crate::BitWriter<'a, REG, PLL_OUTPUT_GATE_A>;
237impl<'a, REG> PLL_OUTPUT_GATE_W<'a, REG>
238where
239    REG: crate::Writable + crate::RegisterSpec,
240{
241    #[doc = "`0`"]
242    #[inline(always)]
243    pub fn disable(self) -> &'a mut crate::W<REG> {
244        self.variant(PLL_OUTPUT_GATE_A::DISABLE)
245    }
246    #[doc = "`1`"]
247    #[inline(always)]
248    pub fn enable(self) -> &'a mut crate::W<REG> {
249        self.variant(PLL_OUTPUT_GATE_A::ENABLE)
250    }
251}
252#[doc = "Field `lock` reader - PLL Lock Status"]
253pub type LOCK_R = crate::BitReader<LOCK_A>;
254#[doc = "PLL Lock Status\n\nValue on reset: 0"]
255#[derive(Clone, Copy, Debug, PartialEq, Eq)]
256pub enum LOCK_A {
257    #[doc = "0: `0`"]
258    UNLOCKED = 0,
259    #[doc = "1: `1`"]
260    LOCKED = 1,
261}
262impl From<LOCK_A> for bool {
263    #[inline(always)]
264    fn from(variant: LOCK_A) -> Self {
265        variant as u8 != 0
266    }
267}
268impl LOCK_R {
269    #[doc = "Get enumerated values variant"]
270    #[inline(always)]
271    pub const fn variant(&self) -> LOCK_A {
272        match self.bits {
273            false => LOCK_A::UNLOCKED,
274            true => LOCK_A::LOCKED,
275        }
276    }
277    #[doc = "`0`"]
278    #[inline(always)]
279    pub fn is_unlocked(&self) -> bool {
280        *self == LOCK_A::UNLOCKED
281    }
282    #[doc = "`1`"]
283    #[inline(always)]
284    pub fn is_locked(&self) -> bool {
285        *self == LOCK_A::LOCKED
286    }
287}
288#[doc = "Field `lock_enable` reader - Lock Enable"]
289pub type LOCK_ENABLE_R = crate::BitReader<LOCK_ENABLE_A>;
290#[doc = "Lock Enable\n\nValue on reset: 0"]
291#[derive(Clone, Copy, Debug, PartialEq, Eq)]
292pub enum LOCK_ENABLE_A {
293    #[doc = "0: `0`"]
294    DISABLE = 0,
295    #[doc = "1: `1`"]
296    ENABLE = 1,
297}
298impl From<LOCK_ENABLE_A> for bool {
299    #[inline(always)]
300    fn from(variant: LOCK_ENABLE_A) -> Self {
301        variant as u8 != 0
302    }
303}
304impl LOCK_ENABLE_R {
305    #[doc = "Get enumerated values variant"]
306    #[inline(always)]
307    pub const fn variant(&self) -> LOCK_ENABLE_A {
308        match self.bits {
309            false => LOCK_ENABLE_A::DISABLE,
310            true => LOCK_ENABLE_A::ENABLE,
311        }
312    }
313    #[doc = "`0`"]
314    #[inline(always)]
315    pub fn is_disable(&self) -> bool {
316        *self == LOCK_ENABLE_A::DISABLE
317    }
318    #[doc = "`1`"]
319    #[inline(always)]
320    pub fn is_enable(&self) -> bool {
321        *self == LOCK_ENABLE_A::ENABLE
322    }
323}
324#[doc = "Field `lock_enable` writer - Lock Enable"]
325pub type LOCK_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, LOCK_ENABLE_A>;
326impl<'a, REG> LOCK_ENABLE_W<'a, REG>
327where
328    REG: crate::Writable + crate::RegisterSpec,
329{
330    #[doc = "`0`"]
331    #[inline(always)]
332    pub fn disable(self) -> &'a mut crate::W<REG> {
333        self.variant(LOCK_ENABLE_A::DISABLE)
334    }
335    #[doc = "`1`"]
336    #[inline(always)]
337    pub fn enable(self) -> &'a mut crate::W<REG> {
338        self.variant(LOCK_ENABLE_A::ENABLE)
339    }
340}
341#[doc = "Field `pll_ldo_en` reader - LDO Enable"]
342pub type PLL_LDO_EN_R = crate::BitReader<PLL_LDO_EN_A>;
343#[doc = "LDO Enable\n\nValue on reset: 0"]
344#[derive(Clone, Copy, Debug, PartialEq, Eq)]
345pub enum PLL_LDO_EN_A {
346    #[doc = "0: `0`"]
347    DISABLE = 0,
348    #[doc = "1: `1`"]
349    ENABLE = 1,
350}
351impl From<PLL_LDO_EN_A> for bool {
352    #[inline(always)]
353    fn from(variant: PLL_LDO_EN_A) -> Self {
354        variant as u8 != 0
355    }
356}
357impl PLL_LDO_EN_R {
358    #[doc = "Get enumerated values variant"]
359    #[inline(always)]
360    pub const fn variant(&self) -> PLL_LDO_EN_A {
361        match self.bits {
362            false => PLL_LDO_EN_A::DISABLE,
363            true => PLL_LDO_EN_A::ENABLE,
364        }
365    }
366    #[doc = "`0`"]
367    #[inline(always)]
368    pub fn is_disable(&self) -> bool {
369        *self == PLL_LDO_EN_A::DISABLE
370    }
371    #[doc = "`1`"]
372    #[inline(always)]
373    pub fn is_enable(&self) -> bool {
374        *self == PLL_LDO_EN_A::ENABLE
375    }
376}
377#[doc = "Field `pll_ldo_en` writer - LDO Enable"]
378pub type PLL_LDO_EN_W<'a, REG> = crate::BitWriter<'a, REG, PLL_LDO_EN_A>;
379impl<'a, REG> PLL_LDO_EN_W<'a, REG>
380where
381    REG: crate::Writable + crate::RegisterSpec,
382{
383    #[doc = "`0`"]
384    #[inline(always)]
385    pub fn disable(self) -> &'a mut crate::W<REG> {
386        self.variant(PLL_LDO_EN_A::DISABLE)
387    }
388    #[doc = "`1`"]
389    #[inline(always)]
390    pub fn enable(self) -> &'a mut crate::W<REG> {
391        self.variant(PLL_LDO_EN_A::ENABLE)
392    }
393}
394#[doc = "Field `pll_en` reader - PLL Enable"]
395pub type PLL_EN_R = crate::BitReader<PLL_EN_A>;
396#[doc = "PLL Enable\n\nValue on reset: 0"]
397#[derive(Clone, Copy, Debug, PartialEq, Eq)]
398pub enum PLL_EN_A {
399    #[doc = "0: `0`"]
400    DISABLE = 0,
401    #[doc = "1: `1`"]
402    ENABLE = 1,
403}
404impl From<PLL_EN_A> for bool {
405    #[inline(always)]
406    fn from(variant: PLL_EN_A) -> Self {
407        variant as u8 != 0
408    }
409}
410impl PLL_EN_R {
411    #[doc = "Get enumerated values variant"]
412    #[inline(always)]
413    pub const fn variant(&self) -> PLL_EN_A {
414        match self.bits {
415            false => PLL_EN_A::DISABLE,
416            true => PLL_EN_A::ENABLE,
417        }
418    }
419    #[doc = "`0`"]
420    #[inline(always)]
421    pub fn is_disable(&self) -> bool {
422        *self == PLL_EN_A::DISABLE
423    }
424    #[doc = "`1`"]
425    #[inline(always)]
426    pub fn is_enable(&self) -> bool {
427        *self == PLL_EN_A::ENABLE
428    }
429}
430#[doc = "Field `pll_en` writer - PLL Enable"]
431pub type PLL_EN_W<'a, REG> = crate::BitWriter<'a, REG, PLL_EN_A>;
432impl<'a, REG> PLL_EN_W<'a, REG>
433where
434    REG: crate::Writable + crate::RegisterSpec,
435{
436    #[doc = "`0`"]
437    #[inline(always)]
438    pub fn disable(self) -> &'a mut crate::W<REG> {
439        self.variant(PLL_EN_A::DISABLE)
440    }
441    #[doc = "`1`"]
442    #[inline(always)]
443    pub fn enable(self) -> &'a mut crate::W<REG> {
444        self.variant(PLL_EN_A::ENABLE)
445    }
446}
447impl R {
448    #[doc = "Bit 0 - PLL Output Div M0"]
449    #[inline(always)]
450    pub fn pll_output_div2(&self) -> PLL_OUTPUT_DIV2_R {
451        PLL_OUTPUT_DIV2_R::new((self.bits & 1) != 0)
452    }
453    #[doc = "Bit 1 - PLL Input Div M1"]
454    #[inline(always)]
455    pub fn pll_input_div2(&self) -> PLL_INPUT_DIV2_R {
456        PLL_INPUT_DIV2_R::new(((self.bits >> 1) & 1) != 0)
457    }
458    #[doc = "Bit 5 - PLL Lock Level"]
459    #[inline(always)]
460    pub fn pll_lock_mdsel(&self) -> PLL_LOCK_MDSEL_R {
461        PLL_LOCK_MDSEL_R::new(((self.bits >> 5) & 1) != 0)
462    }
463    #[doc = "Bits 6:7 - PLL Unlock Level"]
464    #[inline(always)]
465    pub fn pll_unlock_mdsel(&self) -> PLL_UNLOCK_MDSEL_R {
466        PLL_UNLOCK_MDSEL_R::new(((self.bits >> 6) & 3) as u8)
467    }
468    #[doc = "Bits 8:15 - PLL N"]
469    #[inline(always)]
470    pub fn pll_n(&self) -> PLL_N_R {
471        PLL_N_R::new(((self.bits >> 8) & 0xff) as u8)
472    }
473    #[doc = "Bits 16:21 - PLL Post-div P"]
474    #[inline(always)]
475    pub fn pll_p(&self) -> PLL_P_R {
476        PLL_P_R::new(((self.bits >> 16) & 0x3f) as u8)
477    }
478    #[doc = "Bit 24 - PLL SDM Enable"]
479    #[inline(always)]
480    pub fn pll_sdm_en(&self) -> PLL_SDM_EN_R {
481        PLL_SDM_EN_R::new(((self.bits >> 24) & 1) != 0)
482    }
483    #[doc = "Bit 27 - PLL Output Gating Enable"]
484    #[inline(always)]
485    pub fn pll_output_gate(&self) -> PLL_OUTPUT_GATE_R {
486        PLL_OUTPUT_GATE_R::new(((self.bits >> 27) & 1) != 0)
487    }
488    #[doc = "Bit 28 - PLL Lock Status"]
489    #[inline(always)]
490    pub fn lock(&self) -> LOCK_R {
491        LOCK_R::new(((self.bits >> 28) & 1) != 0)
492    }
493    #[doc = "Bit 29 - Lock Enable"]
494    #[inline(always)]
495    pub fn lock_enable(&self) -> LOCK_ENABLE_R {
496        LOCK_ENABLE_R::new(((self.bits >> 29) & 1) != 0)
497    }
498    #[doc = "Bit 30 - LDO Enable"]
499    #[inline(always)]
500    pub fn pll_ldo_en(&self) -> PLL_LDO_EN_R {
501        PLL_LDO_EN_R::new(((self.bits >> 30) & 1) != 0)
502    }
503    #[doc = "Bit 31 - PLL Enable"]
504    #[inline(always)]
505    pub fn pll_en(&self) -> PLL_EN_R {
506        PLL_EN_R::new(((self.bits >> 31) & 1) != 0)
507    }
508}
509impl W {
510    #[doc = "Bit 0 - PLL Output Div M0"]
511    #[inline(always)]
512    #[must_use]
513    pub fn pll_output_div2(&mut self) -> PLL_OUTPUT_DIV2_W<PLL_AUDIO0_CTRL_SPEC> {
514        PLL_OUTPUT_DIV2_W::new(self, 0)
515    }
516    #[doc = "Bit 1 - PLL Input Div M1"]
517    #[inline(always)]
518    #[must_use]
519    pub fn pll_input_div2(&mut self) -> PLL_INPUT_DIV2_W<PLL_AUDIO0_CTRL_SPEC> {
520        PLL_INPUT_DIV2_W::new(self, 1)
521    }
522    #[doc = "Bit 5 - PLL Lock Level"]
523    #[inline(always)]
524    #[must_use]
525    pub fn pll_lock_mdsel(&mut self) -> PLL_LOCK_MDSEL_W<PLL_AUDIO0_CTRL_SPEC> {
526        PLL_LOCK_MDSEL_W::new(self, 5)
527    }
528    #[doc = "Bits 6:7 - PLL Unlock Level"]
529    #[inline(always)]
530    #[must_use]
531    pub fn pll_unlock_mdsel(&mut self) -> PLL_UNLOCK_MDSEL_W<PLL_AUDIO0_CTRL_SPEC> {
532        PLL_UNLOCK_MDSEL_W::new(self, 6)
533    }
534    #[doc = "Bits 8:15 - PLL N"]
535    #[inline(always)]
536    #[must_use]
537    pub fn pll_n(&mut self) -> PLL_N_W<PLL_AUDIO0_CTRL_SPEC> {
538        PLL_N_W::new(self, 8)
539    }
540    #[doc = "Bits 16:21 - PLL Post-div P"]
541    #[inline(always)]
542    #[must_use]
543    pub fn pll_p(&mut self) -> PLL_P_W<PLL_AUDIO0_CTRL_SPEC> {
544        PLL_P_W::new(self, 16)
545    }
546    #[doc = "Bit 24 - PLL SDM Enable"]
547    #[inline(always)]
548    #[must_use]
549    pub fn pll_sdm_en(&mut self) -> PLL_SDM_EN_W<PLL_AUDIO0_CTRL_SPEC> {
550        PLL_SDM_EN_W::new(self, 24)
551    }
552    #[doc = "Bit 27 - PLL Output Gating Enable"]
553    #[inline(always)]
554    #[must_use]
555    pub fn pll_output_gate(&mut self) -> PLL_OUTPUT_GATE_W<PLL_AUDIO0_CTRL_SPEC> {
556        PLL_OUTPUT_GATE_W::new(self, 27)
557    }
558    #[doc = "Bit 29 - Lock Enable"]
559    #[inline(always)]
560    #[must_use]
561    pub fn lock_enable(&mut self) -> LOCK_ENABLE_W<PLL_AUDIO0_CTRL_SPEC> {
562        LOCK_ENABLE_W::new(self, 29)
563    }
564    #[doc = "Bit 30 - LDO Enable"]
565    #[inline(always)]
566    #[must_use]
567    pub fn pll_ldo_en(&mut self) -> PLL_LDO_EN_W<PLL_AUDIO0_CTRL_SPEC> {
568        PLL_LDO_EN_W::new(self, 30)
569    }
570    #[doc = "Bit 31 - PLL Enable"]
571    #[inline(always)]
572    #[must_use]
573    pub fn pll_en(&mut self) -> PLL_EN_W<PLL_AUDIO0_CTRL_SPEC> {
574        PLL_EN_W::new(self, 31)
575    }
576    #[doc = r" Writes raw bits to the register."]
577    #[doc = r""]
578    #[doc = r" # Safety"]
579    #[doc = r""]
580    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
581    #[inline(always)]
582    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
583        self.bits = bits;
584        self
585    }
586}
587#[doc = "PLL_AUDIO0 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_audio0_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_audio0_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
588pub struct PLL_AUDIO0_CTRL_SPEC;
589impl crate::RegisterSpec for PLL_AUDIO0_CTRL_SPEC {
590    type Ux = u32;
591}
592#[doc = "`read()` method returns [`pll_audio0_ctrl::R`](R) reader structure"]
593impl crate::Readable for PLL_AUDIO0_CTRL_SPEC {}
594#[doc = "`write(|w| ..)` method takes [`pll_audio0_ctrl::W`](W) writer structure"]
595impl crate::Writable for PLL_AUDIO0_CTRL_SPEC {
596    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
597    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
598}
599#[doc = "`reset()` method sets pll_audio0_ctrl to value 0"]
600impl crate::Resettable for PLL_AUDIO0_CTRL_SPEC {
601    const RESET_VALUE: Self::Ux = 0;
602}
d1_pac/ccu/pll_audio0_ctrl.rs

d1_pac/ccu/
pll_audio0_ctrl.rs
