d1_pac/ccu/
owa_tx_clk.rs

1#[doc = "Register `owa_tx_clk` reader"]
2pub type R = crate::R<OWA_TX_CLK_SPEC>;
3#[doc = "Register `owa_tx_clk` writer"]
4pub type W = crate::W<OWA_TX_CLK_SPEC>;
5#[doc = "Field `factor_m` reader - Factor M"]
6pub type FACTOR_M_R = crate::FieldReader;
7#[doc = "Field `factor_m` writer - Factor M"]
8pub type FACTOR_M_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `factor_n` reader - Factor N"]
10pub type FACTOR_N_R = crate::FieldReader<FACTOR_N_A>;
11#[doc = "Factor N\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13#[repr(u8)]
14pub enum FACTOR_N_A {
15    #[doc = "0: `0`"]
16    N1 = 0,
17    #[doc = "1: `1`"]
18    N2 = 1,
19    #[doc = "2: `10`"]
20    N4 = 2,
21    #[doc = "3: `11`"]
22    N8 = 3,
23}
24impl From<FACTOR_N_A> for u8 {
25    #[inline(always)]
26    fn from(variant: FACTOR_N_A) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for FACTOR_N_A {
31    type Ux = u8;
32}
33impl FACTOR_N_R {
34    #[doc = "Get enumerated values variant"]
35    #[inline(always)]
36    pub const fn variant(&self) -> FACTOR_N_A {
37        match self.bits {
38            0 => FACTOR_N_A::N1,
39            1 => FACTOR_N_A::N2,
40            2 => FACTOR_N_A::N4,
41            3 => FACTOR_N_A::N8,
42            _ => unreachable!(),
43        }
44    }
45    #[doc = "`0`"]
46    #[inline(always)]
47    pub fn is_n1(&self) -> bool {
48        *self == FACTOR_N_A::N1
49    }
50    #[doc = "`1`"]
51    #[inline(always)]
52    pub fn is_n2(&self) -> bool {
53        *self == FACTOR_N_A::N2
54    }
55    #[doc = "`10`"]
56    #[inline(always)]
57    pub fn is_n4(&self) -> bool {
58        *self == FACTOR_N_A::N4
59    }
60    #[doc = "`11`"]
61    #[inline(always)]
62    pub fn is_n8(&self) -> bool {
63        *self == FACTOR_N_A::N8
64    }
65}
66#[doc = "Field `factor_n` writer - Factor N"]
67pub type FACTOR_N_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, FACTOR_N_A>;
68impl<'a, REG> FACTOR_N_W<'a, REG>
69where
70    REG: crate::Writable + crate::RegisterSpec,
71    REG::Ux: From<u8>,
72{
73    #[doc = "`0`"]
74    #[inline(always)]
75    pub fn n1(self) -> &'a mut crate::W<REG> {
76        self.variant(FACTOR_N_A::N1)
77    }
78    #[doc = "`1`"]
79    #[inline(always)]
80    pub fn n2(self) -> &'a mut crate::W<REG> {
81        self.variant(FACTOR_N_A::N2)
82    }
83    #[doc = "`10`"]
84    #[inline(always)]
85    pub fn n4(self) -> &'a mut crate::W<REG> {
86        self.variant(FACTOR_N_A::N4)
87    }
88    #[doc = "`11`"]
89    #[inline(always)]
90    pub fn n8(self) -> &'a mut crate::W<REG> {
91        self.variant(FACTOR_N_A::N8)
92    }
93}
94#[doc = "Field `clk_src_sel` reader - Clock Source Select"]
95pub type CLK_SRC_SEL_R = crate::FieldReader<CLK_SRC_SEL_A>;
96#[doc = "Clock Source Select\n\nValue on reset: 0"]
97#[derive(Clone, Copy, Debug, PartialEq, Eq)]
98#[repr(u8)]
99pub enum CLK_SRC_SEL_A {
100    #[doc = "0: `0`"]
101    PLL_AUDIO0_1X = 0,
102    #[doc = "1: `1`"]
103    PLL_AUDIO0_4X = 1,
104    #[doc = "2: `10`"]
105    PLL_AUDIO1_DIV2 = 2,
106    #[doc = "3: `11`"]
107    PLL_AUDIO1_DIV5 = 3,
108}
109impl From<CLK_SRC_SEL_A> for u8 {
110    #[inline(always)]
111    fn from(variant: CLK_SRC_SEL_A) -> Self {
112        variant as _
113    }
114}
115impl crate::FieldSpec for CLK_SRC_SEL_A {
116    type Ux = u8;
117}
118impl CLK_SRC_SEL_R {
119    #[doc = "Get enumerated values variant"]
120    #[inline(always)]
121    pub const fn variant(&self) -> Option<CLK_SRC_SEL_A> {
122        match self.bits {
123            0 => Some(CLK_SRC_SEL_A::PLL_AUDIO0_1X),
124            1 => Some(CLK_SRC_SEL_A::PLL_AUDIO0_4X),
125            2 => Some(CLK_SRC_SEL_A::PLL_AUDIO1_DIV2),
126            3 => Some(CLK_SRC_SEL_A::PLL_AUDIO1_DIV5),
127            _ => None,
128        }
129    }
130    #[doc = "`0`"]
131    #[inline(always)]
132    pub fn is_pll_audio0_1x(&self) -> bool {
133        *self == CLK_SRC_SEL_A::PLL_AUDIO0_1X
134    }
135    #[doc = "`1`"]
136    #[inline(always)]
137    pub fn is_pll_audio0_4x(&self) -> bool {
138        *self == CLK_SRC_SEL_A::PLL_AUDIO0_4X
139    }
140    #[doc = "`10`"]
141    #[inline(always)]
142    pub fn is_pll_audio1_div2(&self) -> bool {
143        *self == CLK_SRC_SEL_A::PLL_AUDIO1_DIV2
144    }
145    #[doc = "`11`"]
146    #[inline(always)]
147    pub fn is_pll_audio1_div5(&self) -> bool {
148        *self == CLK_SRC_SEL_A::PLL_AUDIO1_DIV5
149    }
150}
151#[doc = "Field `clk_src_sel` writer - Clock Source Select"]
152pub type CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CLK_SRC_SEL_A>;
153impl<'a, REG> CLK_SRC_SEL_W<'a, REG>
154where
155    REG: crate::Writable + crate::RegisterSpec,
156    REG::Ux: From<u8>,
157{
158    #[doc = "`0`"]
159    #[inline(always)]
160    pub fn pll_audio0_1x(self) -> &'a mut crate::W<REG> {
161        self.variant(CLK_SRC_SEL_A::PLL_AUDIO0_1X)
162    }
163    #[doc = "`1`"]
164    #[inline(always)]
165    pub fn pll_audio0_4x(self) -> &'a mut crate::W<REG> {
166        self.variant(CLK_SRC_SEL_A::PLL_AUDIO0_4X)
167    }
168    #[doc = "`10`"]
169    #[inline(always)]
170    pub fn pll_audio1_div2(self) -> &'a mut crate::W<REG> {
171        self.variant(CLK_SRC_SEL_A::PLL_AUDIO1_DIV2)
172    }
173    #[doc = "`11`"]
174    #[inline(always)]
175    pub fn pll_audio1_div5(self) -> &'a mut crate::W<REG> {
176        self.variant(CLK_SRC_SEL_A::PLL_AUDIO1_DIV5)
177    }
178}
179#[doc = "Field `clk_gating` reader - Gating Clock"]
180pub type CLK_GATING_R = crate::BitReader<CLK_GATING_A>;
181#[doc = "Gating Clock\n\nValue on reset: 0"]
182#[derive(Clone, Copy, Debug, PartialEq, Eq)]
183pub enum CLK_GATING_A {
184    #[doc = "0: `0`"]
185    OFF = 0,
186    #[doc = "1: `1`"]
187    ON = 1,
188}
189impl From<CLK_GATING_A> for bool {
190    #[inline(always)]
191    fn from(variant: CLK_GATING_A) -> Self {
192        variant as u8 != 0
193    }
194}
195impl CLK_GATING_R {
196    #[doc = "Get enumerated values variant"]
197    #[inline(always)]
198    pub const fn variant(&self) -> CLK_GATING_A {
199        match self.bits {
200            false => CLK_GATING_A::OFF,
201            true => CLK_GATING_A::ON,
202        }
203    }
204    #[doc = "`0`"]
205    #[inline(always)]
206    pub fn is_off(&self) -> bool {
207        *self == CLK_GATING_A::OFF
208    }
209    #[doc = "`1`"]
210    #[inline(always)]
211    pub fn is_on(&self) -> bool {
212        *self == CLK_GATING_A::ON
213    }
214}
215#[doc = "Field `clk_gating` writer - Gating Clock"]
216pub type CLK_GATING_W<'a, REG> = crate::BitWriter<'a, REG, CLK_GATING_A>;
217impl<'a, REG> CLK_GATING_W<'a, REG>
218where
219    REG: crate::Writable + crate::RegisterSpec,
220{
221    #[doc = "`0`"]
222    #[inline(always)]
223    pub fn off(self) -> &'a mut crate::W<REG> {
224        self.variant(CLK_GATING_A::OFF)
225    }
226    #[doc = "`1`"]
227    #[inline(always)]
228    pub fn on(self) -> &'a mut crate::W<REG> {
229        self.variant(CLK_GATING_A::ON)
230    }
231}
232impl R {
233    #[doc = "Bits 0:4 - Factor M"]
234    #[inline(always)]
235    pub fn factor_m(&self) -> FACTOR_M_R {
236        FACTOR_M_R::new((self.bits & 0x1f) as u8)
237    }
238    #[doc = "Bits 8:9 - Factor N"]
239    #[inline(always)]
240    pub fn factor_n(&self) -> FACTOR_N_R {
241        FACTOR_N_R::new(((self.bits >> 8) & 3) as u8)
242    }
243    #[doc = "Bits 24:26 - Clock Source Select"]
244    #[inline(always)]
245    pub fn clk_src_sel(&self) -> CLK_SRC_SEL_R {
246        CLK_SRC_SEL_R::new(((self.bits >> 24) & 7) as u8)
247    }
248    #[doc = "Bit 31 - Gating Clock"]
249    #[inline(always)]
250    pub fn clk_gating(&self) -> CLK_GATING_R {
251        CLK_GATING_R::new(((self.bits >> 31) & 1) != 0)
252    }
253}
254impl W {
255    #[doc = "Bits 0:4 - Factor M"]
256    #[inline(always)]
257    #[must_use]
258    pub fn factor_m(&mut self) -> FACTOR_M_W<OWA_TX_CLK_SPEC> {
259        FACTOR_M_W::new(self, 0)
260    }
261    #[doc = "Bits 8:9 - Factor N"]
262    #[inline(always)]
263    #[must_use]
264    pub fn factor_n(&mut self) -> FACTOR_N_W<OWA_TX_CLK_SPEC> {
265        FACTOR_N_W::new(self, 8)
266    }
267    #[doc = "Bits 24:26 - Clock Source Select"]
268    #[inline(always)]
269    #[must_use]
270    pub fn clk_src_sel(&mut self) -> CLK_SRC_SEL_W<OWA_TX_CLK_SPEC> {
271        CLK_SRC_SEL_W::new(self, 24)
272    }
273    #[doc = "Bit 31 - Gating Clock"]
274    #[inline(always)]
275    #[must_use]
276    pub fn clk_gating(&mut self) -> CLK_GATING_W<OWA_TX_CLK_SPEC> {
277        CLK_GATING_W::new(self, 31)
278    }
279    #[doc = r" Writes raw bits to the register."]
280    #[doc = r""]
281    #[doc = r" # Safety"]
282    #[doc = r""]
283    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
284    #[inline(always)]
285    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
286        self.bits = bits;
287        self
288    }
289}
290#[doc = "OWA_TX Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`owa_tx_clk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`owa_tx_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
291pub struct OWA_TX_CLK_SPEC;
292impl crate::RegisterSpec for OWA_TX_CLK_SPEC {
293    type Ux = u32;
294}
295#[doc = "`read()` method returns [`owa_tx_clk::R`](R) reader structure"]
296impl crate::Readable for OWA_TX_CLK_SPEC {}
297#[doc = "`write(|w| ..)` method takes [`owa_tx_clk::W`](W) writer structure"]
298impl crate::Writable for OWA_TX_CLK_SPEC {
299    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
300    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
301}
302#[doc = "`reset()` method sets owa_tx_clk to value 0"]
303impl crate::Resettable for OWA_TX_CLK_SPEC {
304    const RESET_VALUE: Self::Ux = 0;
305}
d1_pac/ccu/owa_tx_clk.rs

d1_pac/ccu/
owa_tx_clk.rs
