d1_pac/ccu/
msgbox_bgr.rs

1#[doc = "Register `msgbox_bgr` reader"]
2pub type R = crate::R<MSGBOX_BGR_SPEC>;
3#[doc = "Register `msgbox_bgr` writer"]
4pub type W = crate::W<MSGBOX_BGR_SPEC>;
5#[doc = "Field `msgbox_gating[0-2]` reader - Gating Clock for CPU, DSP, RISC-V MSGBOX"]
6pub type MSGBOX_GATING_R = crate::BitReader<MSGBOX_GATING_A>;
7#[doc = "Gating Clock for CPU, DSP, RISC-V MSGBOX\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum MSGBOX_GATING_A {
10    #[doc = "0: `0`"]
11    MASK = 0,
12    #[doc = "1: `1`"]
13    PASS = 1,
14}
15impl From<MSGBOX_GATING_A> for bool {
16    #[inline(always)]
17    fn from(variant: MSGBOX_GATING_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl MSGBOX_GATING_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> MSGBOX_GATING_A {
25        match self.bits {
26            false => MSGBOX_GATING_A::MASK,
27            true => MSGBOX_GATING_A::PASS,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_mask(&self) -> bool {
33        *self == MSGBOX_GATING_A::MASK
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_pass(&self) -> bool {
38        *self == MSGBOX_GATING_A::PASS
39    }
40}
41#[doc = "Field `msgbox_gating[0-2]` writer - Gating Clock for CPU, DSP, RISC-V MSGBOX"]
42pub type MSGBOX_GATING_W<'a, REG> = crate::BitWriter<'a, REG, MSGBOX_GATING_A>;
43impl<'a, REG> MSGBOX_GATING_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn mask(self) -> &'a mut crate::W<REG> {
50        self.variant(MSGBOX_GATING_A::MASK)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn pass(self) -> &'a mut crate::W<REG> {
55        self.variant(MSGBOX_GATING_A::PASS)
56    }
57}
58#[doc = "Field `msgbox_rst[0-2]` reader - CPU, DSP, RISC-V MSGBOX Reset"]
59pub type MSGBOX_RST_R = crate::BitReader<MSGBOX_RST_A>;
60#[doc = "CPU, DSP, RISC-V MSGBOX Reset\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum MSGBOX_RST_A {
63    #[doc = "0: `0`"]
64    ASSERT = 0,
65    #[doc = "1: `1`"]
66    DEASSERT = 1,
67}
68impl From<MSGBOX_RST_A> for bool {
69    #[inline(always)]
70    fn from(variant: MSGBOX_RST_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl MSGBOX_RST_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> MSGBOX_RST_A {
78        match self.bits {
79            false => MSGBOX_RST_A::ASSERT,
80            true => MSGBOX_RST_A::DEASSERT,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_assert(&self) -> bool {
86        *self == MSGBOX_RST_A::ASSERT
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_deassert(&self) -> bool {
91        *self == MSGBOX_RST_A::DEASSERT
92    }
93}
94#[doc = "Field `msgbox_rst[0-2]` writer - CPU, DSP, RISC-V MSGBOX Reset"]
95pub type MSGBOX_RST_W<'a, REG> = crate::BitWriter<'a, REG, MSGBOX_RST_A>;
96impl<'a, REG> MSGBOX_RST_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn assert(self) -> &'a mut crate::W<REG> {
103        self.variant(MSGBOX_RST_A::ASSERT)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn deassert(self) -> &'a mut crate::W<REG> {
108        self.variant(MSGBOX_RST_A::DEASSERT)
109    }
110}
111impl R {
112    #[doc = "Gating Clock for CPU, DSP, RISC-V MSGBOX\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `msgbox0_gating` field"]
113    #[inline(always)]
114    pub fn msgbox_gating(&self, n: u8) -> MSGBOX_GATING_R {
115        #[allow(clippy::no_effect)]
116        [(); 3][n as usize];
117        MSGBOX_GATING_R::new(((self.bits >> n) & 1) != 0)
118    }
119    #[doc = "Bit 0 - Gating Clock for CPU, DSP, RISC-V MSGBOX"]
120    #[inline(always)]
121    pub fn msgbox0_gating(&self) -> MSGBOX_GATING_R {
122        MSGBOX_GATING_R::new((self.bits & 1) != 0)
123    }
124    #[doc = "Bit 1 - Gating Clock for CPU, DSP, RISC-V MSGBOX"]
125    #[inline(always)]
126    pub fn msgbox1_gating(&self) -> MSGBOX_GATING_R {
127        MSGBOX_GATING_R::new(((self.bits >> 1) & 1) != 0)
128    }
129    #[doc = "Bit 2 - Gating Clock for CPU, DSP, RISC-V MSGBOX"]
130    #[inline(always)]
131    pub fn msgbox2_gating(&self) -> MSGBOX_GATING_R {
132        MSGBOX_GATING_R::new(((self.bits >> 2) & 1) != 0)
133    }
134    #[doc = "CPU, DSP, RISC-V MSGBOX Reset\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `msgbox0_rst` field"]
135    #[inline(always)]
136    pub fn msgbox_rst(&self, n: u8) -> MSGBOX_RST_R {
137        #[allow(clippy::no_effect)]
138        [(); 3][n as usize];
139        MSGBOX_RST_R::new(((self.bits >> (n + 16)) & 1) != 0)
140    }
141    #[doc = "Bit 16 - CPU, DSP, RISC-V MSGBOX Reset"]
142    #[inline(always)]
143    pub fn msgbox0_rst(&self) -> MSGBOX_RST_R {
144        MSGBOX_RST_R::new(((self.bits >> 16) & 1) != 0)
145    }
146    #[doc = "Bit 17 - CPU, DSP, RISC-V MSGBOX Reset"]
147    #[inline(always)]
148    pub fn msgbox1_rst(&self) -> MSGBOX_RST_R {
149        MSGBOX_RST_R::new(((self.bits >> 17) & 1) != 0)
150    }
151    #[doc = "Bit 18 - CPU, DSP, RISC-V MSGBOX Reset"]
152    #[inline(always)]
153    pub fn msgbox2_rst(&self) -> MSGBOX_RST_R {
154        MSGBOX_RST_R::new(((self.bits >> 18) & 1) != 0)
155    }
156}
157impl W {
158    #[doc = "Gating Clock for CPU, DSP, RISC-V MSGBOX\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `msgbox0_gating` field"]
159    #[inline(always)]
160    #[must_use]
161    pub fn msgbox_gating(&mut self, n: u8) -> MSGBOX_GATING_W<MSGBOX_BGR_SPEC> {
162        #[allow(clippy::no_effect)]
163        [(); 3][n as usize];
164        MSGBOX_GATING_W::new(self, n)
165    }
166    #[doc = "Bit 0 - Gating Clock for CPU, DSP, RISC-V MSGBOX"]
167    #[inline(always)]
168    #[must_use]
169    pub fn msgbox0_gating(&mut self) -> MSGBOX_GATING_W<MSGBOX_BGR_SPEC> {
170        MSGBOX_GATING_W::new(self, 0)
171    }
172    #[doc = "Bit 1 - Gating Clock for CPU, DSP, RISC-V MSGBOX"]
173    #[inline(always)]
174    #[must_use]
175    pub fn msgbox1_gating(&mut self) -> MSGBOX_GATING_W<MSGBOX_BGR_SPEC> {
176        MSGBOX_GATING_W::new(self, 1)
177    }
178    #[doc = "Bit 2 - Gating Clock for CPU, DSP, RISC-V MSGBOX"]
179    #[inline(always)]
180    #[must_use]
181    pub fn msgbox2_gating(&mut self) -> MSGBOX_GATING_W<MSGBOX_BGR_SPEC> {
182        MSGBOX_GATING_W::new(self, 2)
183    }
184    #[doc = "CPU, DSP, RISC-V MSGBOX Reset\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `msgbox0_rst` field"]
185    #[inline(always)]
186    #[must_use]
187    pub fn msgbox_rst(&mut self, n: u8) -> MSGBOX_RST_W<MSGBOX_BGR_SPEC> {
188        #[allow(clippy::no_effect)]
189        [(); 3][n as usize];
190        MSGBOX_RST_W::new(self, n + 16)
191    }
192    #[doc = "Bit 16 - CPU, DSP, RISC-V MSGBOX Reset"]
193    #[inline(always)]
194    #[must_use]
195    pub fn msgbox0_rst(&mut self) -> MSGBOX_RST_W<MSGBOX_BGR_SPEC> {
196        MSGBOX_RST_W::new(self, 16)
197    }
198    #[doc = "Bit 17 - CPU, DSP, RISC-V MSGBOX Reset"]
199    #[inline(always)]
200    #[must_use]
201    pub fn msgbox1_rst(&mut self) -> MSGBOX_RST_W<MSGBOX_BGR_SPEC> {
202        MSGBOX_RST_W::new(self, 17)
203    }
204    #[doc = "Bit 18 - CPU, DSP, RISC-V MSGBOX Reset"]
205    #[inline(always)]
206    #[must_use]
207    pub fn msgbox2_rst(&mut self) -> MSGBOX_RST_W<MSGBOX_BGR_SPEC> {
208        MSGBOX_RST_W::new(self, 18)
209    }
210    #[doc = r" Writes raw bits to the register."]
211    #[doc = r""]
212    #[doc = r" # Safety"]
213    #[doc = r""]
214    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
215    #[inline(always)]
216    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
217        self.bits = bits;
218        self
219    }
220}
221#[doc = "MSGBOX Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msgbox_bgr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msgbox_bgr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
222pub struct MSGBOX_BGR_SPEC;
223impl crate::RegisterSpec for MSGBOX_BGR_SPEC {
224    type Ux = u32;
225}
226#[doc = "`read()` method returns [`msgbox_bgr::R`](R) reader structure"]
227impl crate::Readable for MSGBOX_BGR_SPEC {}
228#[doc = "`write(|w| ..)` method takes [`msgbox_bgr::W`](W) writer structure"]
229impl crate::Writable for MSGBOX_BGR_SPEC {
230    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
231    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
232}
233#[doc = "`reset()` method sets msgbox_bgr to value 0"]
234impl crate::Resettable for MSGBOX_BGR_SPEC {
235    const RESET_VALUE: Self::Ux = 0;
236}
d1_pac/ccu/msgbox_bgr.rs

d1_pac/ccu/
msgbox_bgr.rs
