d1_pac/ccu/
mbus_mat_clk_gating.rs

1#[doc = "Register `mbus_mat_clk_gating` reader"]
2pub type R = crate::R<MBUS_MAT_CLK_GATING_SPEC>;
3#[doc = "Register `mbus_mat_clk_gating` writer"]
4pub type W = crate::W<MBUS_MAT_CLK_GATING_SPEC>;
5#[doc = "Field `dma_mclk_en` reader - Gating MBUS Clock"]
6pub type DMA_MCLK_EN_R = crate::BitReader<DMA_MCLK_EN_A>;
7#[doc = "Gating MBUS Clock\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum DMA_MCLK_EN_A {
10    #[doc = "0: `0`"]
11    MASK = 0,
12    #[doc = "1: `1`"]
13    PASS = 1,
14}
15impl From<DMA_MCLK_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: DMA_MCLK_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl DMA_MCLK_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> DMA_MCLK_EN_A {
25        match self.bits {
26            false => DMA_MCLK_EN_A::MASK,
27            true => DMA_MCLK_EN_A::PASS,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_mask(&self) -> bool {
33        *self == DMA_MCLK_EN_A::MASK
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_pass(&self) -> bool {
38        *self == DMA_MCLK_EN_A::PASS
39    }
40}
41#[doc = "Field `dma_mclk_en` writer - Gating MBUS Clock"]
42pub type DMA_MCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG, DMA_MCLK_EN_A>;
43impl<'a, REG> DMA_MCLK_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn mask(self) -> &'a mut crate::W<REG> {
50        self.variant(DMA_MCLK_EN_A::MASK)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn pass(self) -> &'a mut crate::W<REG> {
55        self.variant(DMA_MCLK_EN_A::PASS)
56    }
57}
58#[doc = "Field `ve_mclk_en` reader - Gating MBUS Clock"]
59pub type VE_MCLK_EN_R = crate::BitReader<VE_MCLK_EN_A>;
60#[doc = "Gating MBUS Clock\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum VE_MCLK_EN_A {
63    #[doc = "0: `0`"]
64    MASK = 0,
65    #[doc = "1: `1`"]
66    PASS = 1,
67}
68impl From<VE_MCLK_EN_A> for bool {
69    #[inline(always)]
70    fn from(variant: VE_MCLK_EN_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl VE_MCLK_EN_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> VE_MCLK_EN_A {
78        match self.bits {
79            false => VE_MCLK_EN_A::MASK,
80            true => VE_MCLK_EN_A::PASS,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_mask(&self) -> bool {
86        *self == VE_MCLK_EN_A::MASK
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_pass(&self) -> bool {
91        *self == VE_MCLK_EN_A::PASS
92    }
93}
94#[doc = "Field `ve_mclk_en` writer - Gating MBUS Clock"]
95pub type VE_MCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG, VE_MCLK_EN_A>;
96impl<'a, REG> VE_MCLK_EN_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn mask(self) -> &'a mut crate::W<REG> {
103        self.variant(VE_MCLK_EN_A::MASK)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn pass(self) -> &'a mut crate::W<REG> {
108        self.variant(VE_MCLK_EN_A::PASS)
109    }
110}
111#[doc = "Field `ce_mclk_en` reader - Gating MBUS Clock"]
112pub type CE_MCLK_EN_R = crate::BitReader<CE_MCLK_EN_A>;
113#[doc = "Gating MBUS Clock\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum CE_MCLK_EN_A {
116    #[doc = "0: `0`"]
117    MASK = 0,
118    #[doc = "1: `1`"]
119    PASS = 1,
120}
121impl From<CE_MCLK_EN_A> for bool {
122    #[inline(always)]
123    fn from(variant: CE_MCLK_EN_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl CE_MCLK_EN_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> CE_MCLK_EN_A {
131        match self.bits {
132            false => CE_MCLK_EN_A::MASK,
133            true => CE_MCLK_EN_A::PASS,
134        }
135    }
136    #[doc = "`0`"]
137    #[inline(always)]
138    pub fn is_mask(&self) -> bool {
139        *self == CE_MCLK_EN_A::MASK
140    }
141    #[doc = "`1`"]
142    #[inline(always)]
143    pub fn is_pass(&self) -> bool {
144        *self == CE_MCLK_EN_A::PASS
145    }
146}
147#[doc = "Field `ce_mclk_en` writer - Gating MBUS Clock"]
148pub type CE_MCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG, CE_MCLK_EN_A>;
149impl<'a, REG> CE_MCLK_EN_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "`0`"]
154    #[inline(always)]
155    pub fn mask(self) -> &'a mut crate::W<REG> {
156        self.variant(CE_MCLK_EN_A::MASK)
157    }
158    #[doc = "`1`"]
159    #[inline(always)]
160    pub fn pass(self) -> &'a mut crate::W<REG> {
161        self.variant(CE_MCLK_EN_A::PASS)
162    }
163}
164#[doc = "Field `tvin_mclk_en` reader - Gating MBUS Clock"]
165pub type TVIN_MCLK_EN_R = crate::BitReader<TVIN_MCLK_EN_A>;
166#[doc = "Gating MBUS Clock\n\nValue on reset: 0"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum TVIN_MCLK_EN_A {
169    #[doc = "0: `0`"]
170    MASK = 0,
171    #[doc = "1: `1`"]
172    PASS = 1,
173}
174impl From<TVIN_MCLK_EN_A> for bool {
175    #[inline(always)]
176    fn from(variant: TVIN_MCLK_EN_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl TVIN_MCLK_EN_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> TVIN_MCLK_EN_A {
184        match self.bits {
185            false => TVIN_MCLK_EN_A::MASK,
186            true => TVIN_MCLK_EN_A::PASS,
187        }
188    }
189    #[doc = "`0`"]
190    #[inline(always)]
191    pub fn is_mask(&self) -> bool {
192        *self == TVIN_MCLK_EN_A::MASK
193    }
194    #[doc = "`1`"]
195    #[inline(always)]
196    pub fn is_pass(&self) -> bool {
197        *self == TVIN_MCLK_EN_A::PASS
198    }
199}
200#[doc = "Field `tvin_mclk_en` writer - Gating MBUS Clock"]
201pub type TVIN_MCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG, TVIN_MCLK_EN_A>;
202impl<'a, REG> TVIN_MCLK_EN_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "`0`"]
207    #[inline(always)]
208    pub fn mask(self) -> &'a mut crate::W<REG> {
209        self.variant(TVIN_MCLK_EN_A::MASK)
210    }
211    #[doc = "`1`"]
212    #[inline(always)]
213    pub fn pass(self) -> &'a mut crate::W<REG> {
214        self.variant(TVIN_MCLK_EN_A::PASS)
215    }
216}
217#[doc = "Field `csi_mclk_en` reader - Gating MBUS Clock"]
218pub type CSI_MCLK_EN_R = crate::BitReader<CSI_MCLK_EN_A>;
219#[doc = "Gating MBUS Clock\n\nValue on reset: 0"]
220#[derive(Clone, Copy, Debug, PartialEq, Eq)]
221pub enum CSI_MCLK_EN_A {
222    #[doc = "0: `0`"]
223    MASK = 0,
224    #[doc = "1: `1`"]
225    PASS = 1,
226}
227impl From<CSI_MCLK_EN_A> for bool {
228    #[inline(always)]
229    fn from(variant: CSI_MCLK_EN_A) -> Self {
230        variant as u8 != 0
231    }
232}
233impl CSI_MCLK_EN_R {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> CSI_MCLK_EN_A {
237        match self.bits {
238            false => CSI_MCLK_EN_A::MASK,
239            true => CSI_MCLK_EN_A::PASS,
240        }
241    }
242    #[doc = "`0`"]
243    #[inline(always)]
244    pub fn is_mask(&self) -> bool {
245        *self == CSI_MCLK_EN_A::MASK
246    }
247    #[doc = "`1`"]
248    #[inline(always)]
249    pub fn is_pass(&self) -> bool {
250        *self == CSI_MCLK_EN_A::PASS
251    }
252}
253#[doc = "Field `csi_mclk_en` writer - Gating MBUS Clock"]
254pub type CSI_MCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG, CSI_MCLK_EN_A>;
255impl<'a, REG> CSI_MCLK_EN_W<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258{
259    #[doc = "`0`"]
260    #[inline(always)]
261    pub fn mask(self) -> &'a mut crate::W<REG> {
262        self.variant(CSI_MCLK_EN_A::MASK)
263    }
264    #[doc = "`1`"]
265    #[inline(always)]
266    pub fn pass(self) -> &'a mut crate::W<REG> {
267        self.variant(CSI_MCLK_EN_A::PASS)
268    }
269}
270#[doc = "Field `g2d_mclk_en` reader - Gating MBUS Clock"]
271pub type G2D_MCLK_EN_R = crate::BitReader<G2D_MCLK_EN_A>;
272#[doc = "Gating MBUS Clock\n\nValue on reset: 0"]
273#[derive(Clone, Copy, Debug, PartialEq, Eq)]
274pub enum G2D_MCLK_EN_A {
275    #[doc = "0: `0`"]
276    MASK = 0,
277    #[doc = "1: `1`"]
278    PASS = 1,
279}
280impl From<G2D_MCLK_EN_A> for bool {
281    #[inline(always)]
282    fn from(variant: G2D_MCLK_EN_A) -> Self {
283        variant as u8 != 0
284    }
285}
286impl G2D_MCLK_EN_R {
287    #[doc = "Get enumerated values variant"]
288    #[inline(always)]
289    pub const fn variant(&self) -> G2D_MCLK_EN_A {
290        match self.bits {
291            false => G2D_MCLK_EN_A::MASK,
292            true => G2D_MCLK_EN_A::PASS,
293        }
294    }
295    #[doc = "`0`"]
296    #[inline(always)]
297    pub fn is_mask(&self) -> bool {
298        *self == G2D_MCLK_EN_A::MASK
299    }
300    #[doc = "`1`"]
301    #[inline(always)]
302    pub fn is_pass(&self) -> bool {
303        *self == G2D_MCLK_EN_A::PASS
304    }
305}
306#[doc = "Field `g2d_mclk_en` writer - Gating MBUS Clock"]
307pub type G2D_MCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG, G2D_MCLK_EN_A>;
308impl<'a, REG> G2D_MCLK_EN_W<'a, REG>
309where
310    REG: crate::Writable + crate::RegisterSpec,
311{
312    #[doc = "`0`"]
313    #[inline(always)]
314    pub fn mask(self) -> &'a mut crate::W<REG> {
315        self.variant(G2D_MCLK_EN_A::MASK)
316    }
317    #[doc = "`1`"]
318    #[inline(always)]
319    pub fn pass(self) -> &'a mut crate::W<REG> {
320        self.variant(G2D_MCLK_EN_A::PASS)
321    }
322}
323#[doc = "Field `riscv_mclk_en` reader - Gating MBUS Clock"]
324pub type RISCV_MCLK_EN_R = crate::BitReader<RISCV_MCLK_EN_A>;
325#[doc = "Gating MBUS Clock\n\nValue on reset: 0"]
326#[derive(Clone, Copy, Debug, PartialEq, Eq)]
327pub enum RISCV_MCLK_EN_A {
328    #[doc = "0: `0`"]
329    MASK = 0,
330    #[doc = "1: `1`"]
331    PASS = 1,
332}
333impl From<RISCV_MCLK_EN_A> for bool {
334    #[inline(always)]
335    fn from(variant: RISCV_MCLK_EN_A) -> Self {
336        variant as u8 != 0
337    }
338}
339impl RISCV_MCLK_EN_R {
340    #[doc = "Get enumerated values variant"]
341    #[inline(always)]
342    pub const fn variant(&self) -> RISCV_MCLK_EN_A {
343        match self.bits {
344            false => RISCV_MCLK_EN_A::MASK,
345            true => RISCV_MCLK_EN_A::PASS,
346        }
347    }
348    #[doc = "`0`"]
349    #[inline(always)]
350    pub fn is_mask(&self) -> bool {
351        *self == RISCV_MCLK_EN_A::MASK
352    }
353    #[doc = "`1`"]
354    #[inline(always)]
355    pub fn is_pass(&self) -> bool {
356        *self == RISCV_MCLK_EN_A::PASS
357    }
358}
359#[doc = "Field `riscv_mclk_en` writer - Gating MBUS Clock"]
360pub type RISCV_MCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG, RISCV_MCLK_EN_A>;
361impl<'a, REG> RISCV_MCLK_EN_W<'a, REG>
362where
363    REG: crate::Writable + crate::RegisterSpec,
364{
365    #[doc = "`0`"]
366    #[inline(always)]
367    pub fn mask(self) -> &'a mut crate::W<REG> {
368        self.variant(RISCV_MCLK_EN_A::MASK)
369    }
370    #[doc = "`1`"]
371    #[inline(always)]
372    pub fn pass(self) -> &'a mut crate::W<REG> {
373        self.variant(RISCV_MCLK_EN_A::PASS)
374    }
375}
376impl R {
377    #[doc = "Bit 0 - Gating MBUS Clock"]
378    #[inline(always)]
379    pub fn dma_mclk_en(&self) -> DMA_MCLK_EN_R {
380        DMA_MCLK_EN_R::new((self.bits & 1) != 0)
381    }
382    #[doc = "Bit 1 - Gating MBUS Clock"]
383    #[inline(always)]
384    pub fn ve_mclk_en(&self) -> VE_MCLK_EN_R {
385        VE_MCLK_EN_R::new(((self.bits >> 1) & 1) != 0)
386    }
387    #[doc = "Bit 2 - Gating MBUS Clock"]
388    #[inline(always)]
389    pub fn ce_mclk_en(&self) -> CE_MCLK_EN_R {
390        CE_MCLK_EN_R::new(((self.bits >> 2) & 1) != 0)
391    }
392    #[doc = "Bit 7 - Gating MBUS Clock"]
393    #[inline(always)]
394    pub fn tvin_mclk_en(&self) -> TVIN_MCLK_EN_R {
395        TVIN_MCLK_EN_R::new(((self.bits >> 7) & 1) != 0)
396    }
397    #[doc = "Bit 8 - Gating MBUS Clock"]
398    #[inline(always)]
399    pub fn csi_mclk_en(&self) -> CSI_MCLK_EN_R {
400        CSI_MCLK_EN_R::new(((self.bits >> 8) & 1) != 0)
401    }
402    #[doc = "Bit 10 - Gating MBUS Clock"]
403    #[inline(always)]
404    pub fn g2d_mclk_en(&self) -> G2D_MCLK_EN_R {
405        G2D_MCLK_EN_R::new(((self.bits >> 10) & 1) != 0)
406    }
407    #[doc = "Bit 11 - Gating MBUS Clock"]
408    #[inline(always)]
409    pub fn riscv_mclk_en(&self) -> RISCV_MCLK_EN_R {
410        RISCV_MCLK_EN_R::new(((self.bits >> 11) & 1) != 0)
411    }
412}
413impl W {
414    #[doc = "Bit 0 - Gating MBUS Clock"]
415    #[inline(always)]
416    #[must_use]
417    pub fn dma_mclk_en(&mut self) -> DMA_MCLK_EN_W<MBUS_MAT_CLK_GATING_SPEC> {
418        DMA_MCLK_EN_W::new(self, 0)
419    }
420    #[doc = "Bit 1 - Gating MBUS Clock"]
421    #[inline(always)]
422    #[must_use]
423    pub fn ve_mclk_en(&mut self) -> VE_MCLK_EN_W<MBUS_MAT_CLK_GATING_SPEC> {
424        VE_MCLK_EN_W::new(self, 1)
425    }
426    #[doc = "Bit 2 - Gating MBUS Clock"]
427    #[inline(always)]
428    #[must_use]
429    pub fn ce_mclk_en(&mut self) -> CE_MCLK_EN_W<MBUS_MAT_CLK_GATING_SPEC> {
430        CE_MCLK_EN_W::new(self, 2)
431    }
432    #[doc = "Bit 7 - Gating MBUS Clock"]
433    #[inline(always)]
434    #[must_use]
435    pub fn tvin_mclk_en(&mut self) -> TVIN_MCLK_EN_W<MBUS_MAT_CLK_GATING_SPEC> {
436        TVIN_MCLK_EN_W::new(self, 7)
437    }
438    #[doc = "Bit 8 - Gating MBUS Clock"]
439    #[inline(always)]
440    #[must_use]
441    pub fn csi_mclk_en(&mut self) -> CSI_MCLK_EN_W<MBUS_MAT_CLK_GATING_SPEC> {
442        CSI_MCLK_EN_W::new(self, 8)
443    }
444    #[doc = "Bit 10 - Gating MBUS Clock"]
445    #[inline(always)]
446    #[must_use]
447    pub fn g2d_mclk_en(&mut self) -> G2D_MCLK_EN_W<MBUS_MAT_CLK_GATING_SPEC> {
448        G2D_MCLK_EN_W::new(self, 10)
449    }
450    #[doc = "Bit 11 - Gating MBUS Clock"]
451    #[inline(always)]
452    #[must_use]
453    pub fn riscv_mclk_en(&mut self) -> RISCV_MCLK_EN_W<MBUS_MAT_CLK_GATING_SPEC> {
454        RISCV_MCLK_EN_W::new(self, 11)
455    }
456    #[doc = r" Writes raw bits to the register."]
457    #[doc = r""]
458    #[doc = r" # Safety"]
459    #[doc = r""]
460    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
461    #[inline(always)]
462    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
463        self.bits = bits;
464        self
465    }
466}
467#[doc = "MBUS Master Clock Gating Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mbus_mat_clk_gating::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mbus_mat_clk_gating::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
468pub struct MBUS_MAT_CLK_GATING_SPEC;
469impl crate::RegisterSpec for MBUS_MAT_CLK_GATING_SPEC {
470    type Ux = u32;
471}
472#[doc = "`read()` method returns [`mbus_mat_clk_gating::R`](R) reader structure"]
473impl crate::Readable for MBUS_MAT_CLK_GATING_SPEC {}
474#[doc = "`write(|w| ..)` method takes [`mbus_mat_clk_gating::W`](W) writer structure"]
475impl crate::Writable for MBUS_MAT_CLK_GATING_SPEC {
476    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
477    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
478}
479#[doc = "`reset()` method sets mbus_mat_clk_gating to value 0"]
480impl crate::Resettable for MBUS_MAT_CLK_GATING_SPEC {
481    const RESET_VALUE: Self::Ux = 0;
482}
d1_pac/ccu/mbus_mat_clk_gating.rs

d1_pac/ccu/
mbus_mat_clk_gating.rs
