d1_pac/ccu/
ledc_clk.rs

1#[doc = "Register `ledc_clk` reader"]
2pub type R = crate::R<LEDC_CLK_SPEC>;
3#[doc = "Register `ledc_clk` writer"]
4pub type W = crate::W<LEDC_CLK_SPEC>;
5#[doc = "Field `factor_m` reader - Factor M"]
6pub type FACTOR_M_R = crate::FieldReader;
7#[doc = "Field `factor_m` writer - Factor M"]
8pub type FACTOR_M_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `factor_n` reader - Factor N"]
10pub type FACTOR_N_R = crate::FieldReader<FACTOR_N_A>;
11#[doc = "Factor N\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13#[repr(u8)]
14pub enum FACTOR_N_A {
15    #[doc = "0: `0`"]
16    N1 = 0,
17    #[doc = "1: `1`"]
18    N2 = 1,
19    #[doc = "2: `10`"]
20    N4 = 2,
21    #[doc = "3: `11`"]
22    N8 = 3,
23}
24impl From<FACTOR_N_A> for u8 {
25    #[inline(always)]
26    fn from(variant: FACTOR_N_A) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for FACTOR_N_A {
31    type Ux = u8;
32}
33impl FACTOR_N_R {
34    #[doc = "Get enumerated values variant"]
35    #[inline(always)]
36    pub const fn variant(&self) -> FACTOR_N_A {
37        match self.bits {
38            0 => FACTOR_N_A::N1,
39            1 => FACTOR_N_A::N2,
40            2 => FACTOR_N_A::N4,
41            3 => FACTOR_N_A::N8,
42            _ => unreachable!(),
43        }
44    }
45    #[doc = "`0`"]
46    #[inline(always)]
47    pub fn is_n1(&self) -> bool {
48        *self == FACTOR_N_A::N1
49    }
50    #[doc = "`1`"]
51    #[inline(always)]
52    pub fn is_n2(&self) -> bool {
53        *self == FACTOR_N_A::N2
54    }
55    #[doc = "`10`"]
56    #[inline(always)]
57    pub fn is_n4(&self) -> bool {
58        *self == FACTOR_N_A::N4
59    }
60    #[doc = "`11`"]
61    #[inline(always)]
62    pub fn is_n8(&self) -> bool {
63        *self == FACTOR_N_A::N8
64    }
65}
66#[doc = "Field `factor_n` writer - Factor N"]
67pub type FACTOR_N_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, FACTOR_N_A>;
68impl<'a, REG> FACTOR_N_W<'a, REG>
69where
70    REG: crate::Writable + crate::RegisterSpec,
71    REG::Ux: From<u8>,
72{
73    #[doc = "`0`"]
74    #[inline(always)]
75    pub fn n1(self) -> &'a mut crate::W<REG> {
76        self.variant(FACTOR_N_A::N1)
77    }
78    #[doc = "`1`"]
79    #[inline(always)]
80    pub fn n2(self) -> &'a mut crate::W<REG> {
81        self.variant(FACTOR_N_A::N2)
82    }
83    #[doc = "`10`"]
84    #[inline(always)]
85    pub fn n4(self) -> &'a mut crate::W<REG> {
86        self.variant(FACTOR_N_A::N4)
87    }
88    #[doc = "`11`"]
89    #[inline(always)]
90    pub fn n8(self) -> &'a mut crate::W<REG> {
91        self.variant(FACTOR_N_A::N8)
92    }
93}
94#[doc = "Field `clk_src_sel` reader - Clock Source Select"]
95pub type CLK_SRC_SEL_R = crate::FieldReader<CLK_SRC_SEL_A>;
96#[doc = "Clock Source Select\n\nValue on reset: 0"]
97#[derive(Clone, Copy, Debug, PartialEq, Eq)]
98#[repr(u8)]
99pub enum CLK_SRC_SEL_A {
100    #[doc = "0: `0`"]
101    HOSC = 0,
102    #[doc = "1: `1`"]
103    PLL_PERI_1X = 1,
104}
105impl From<CLK_SRC_SEL_A> for u8 {
106    #[inline(always)]
107    fn from(variant: CLK_SRC_SEL_A) -> Self {
108        variant as _
109    }
110}
111impl crate::FieldSpec for CLK_SRC_SEL_A {
112    type Ux = u8;
113}
114impl CLK_SRC_SEL_R {
115    #[doc = "Get enumerated values variant"]
116    #[inline(always)]
117    pub const fn variant(&self) -> Option<CLK_SRC_SEL_A> {
118        match self.bits {
119            0 => Some(CLK_SRC_SEL_A::HOSC),
120            1 => Some(CLK_SRC_SEL_A::PLL_PERI_1X),
121            _ => None,
122        }
123    }
124    #[doc = "`0`"]
125    #[inline(always)]
126    pub fn is_hosc(&self) -> bool {
127        *self == CLK_SRC_SEL_A::HOSC
128    }
129    #[doc = "`1`"]
130    #[inline(always)]
131    pub fn is_pll_peri_1x(&self) -> bool {
132        *self == CLK_SRC_SEL_A::PLL_PERI_1X
133    }
134}
135#[doc = "Field `clk_src_sel` writer - Clock Source Select"]
136pub type CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CLK_SRC_SEL_A>;
137impl<'a, REG> CLK_SRC_SEL_W<'a, REG>
138where
139    REG: crate::Writable + crate::RegisterSpec,
140    REG::Ux: From<u8>,
141{
142    #[doc = "`0`"]
143    #[inline(always)]
144    pub fn hosc(self) -> &'a mut crate::W<REG> {
145        self.variant(CLK_SRC_SEL_A::HOSC)
146    }
147    #[doc = "`1`"]
148    #[inline(always)]
149    pub fn pll_peri_1x(self) -> &'a mut crate::W<REG> {
150        self.variant(CLK_SRC_SEL_A::PLL_PERI_1X)
151    }
152}
153#[doc = "Field `clk_gating` reader - Gating Clock"]
154pub type CLK_GATING_R = crate::BitReader<CLK_GATING_A>;
155#[doc = "Gating Clock\n\nValue on reset: 0"]
156#[derive(Clone, Copy, Debug, PartialEq, Eq)]
157pub enum CLK_GATING_A {
158    #[doc = "0: `0`"]
159    OFF = 0,
160    #[doc = "1: `1`"]
161    ON = 1,
162}
163impl From<CLK_GATING_A> for bool {
164    #[inline(always)]
165    fn from(variant: CLK_GATING_A) -> Self {
166        variant as u8 != 0
167    }
168}
169impl CLK_GATING_R {
170    #[doc = "Get enumerated values variant"]
171    #[inline(always)]
172    pub const fn variant(&self) -> CLK_GATING_A {
173        match self.bits {
174            false => CLK_GATING_A::OFF,
175            true => CLK_GATING_A::ON,
176        }
177    }
178    #[doc = "`0`"]
179    #[inline(always)]
180    pub fn is_off(&self) -> bool {
181        *self == CLK_GATING_A::OFF
182    }
183    #[doc = "`1`"]
184    #[inline(always)]
185    pub fn is_on(&self) -> bool {
186        *self == CLK_GATING_A::ON
187    }
188}
189#[doc = "Field `clk_gating` writer - Gating Clock"]
190pub type CLK_GATING_W<'a, REG> = crate::BitWriter<'a, REG, CLK_GATING_A>;
191impl<'a, REG> CLK_GATING_W<'a, REG>
192where
193    REG: crate::Writable + crate::RegisterSpec,
194{
195    #[doc = "`0`"]
196    #[inline(always)]
197    pub fn off(self) -> &'a mut crate::W<REG> {
198        self.variant(CLK_GATING_A::OFF)
199    }
200    #[doc = "`1`"]
201    #[inline(always)]
202    pub fn on(self) -> &'a mut crate::W<REG> {
203        self.variant(CLK_GATING_A::ON)
204    }
205}
206impl R {
207    #[doc = "Bits 0:3 - Factor M"]
208    #[inline(always)]
209    pub fn factor_m(&self) -> FACTOR_M_R {
210        FACTOR_M_R::new((self.bits & 0x0f) as u8)
211    }
212    #[doc = "Bits 8:9 - Factor N"]
213    #[inline(always)]
214    pub fn factor_n(&self) -> FACTOR_N_R {
215        FACTOR_N_R::new(((self.bits >> 8) & 3) as u8)
216    }
217    #[doc = "Bits 24:26 - Clock Source Select"]
218    #[inline(always)]
219    pub fn clk_src_sel(&self) -> CLK_SRC_SEL_R {
220        CLK_SRC_SEL_R::new(((self.bits >> 24) & 7) as u8)
221    }
222    #[doc = "Bit 31 - Gating Clock"]
223    #[inline(always)]
224    pub fn clk_gating(&self) -> CLK_GATING_R {
225        CLK_GATING_R::new(((self.bits >> 31) & 1) != 0)
226    }
227}
228impl W {
229    #[doc = "Bits 0:3 - Factor M"]
230    #[inline(always)]
231    #[must_use]
232    pub fn factor_m(&mut self) -> FACTOR_M_W<LEDC_CLK_SPEC> {
233        FACTOR_M_W::new(self, 0)
234    }
235    #[doc = "Bits 8:9 - Factor N"]
236    #[inline(always)]
237    #[must_use]
238    pub fn factor_n(&mut self) -> FACTOR_N_W<LEDC_CLK_SPEC> {
239        FACTOR_N_W::new(self, 8)
240    }
241    #[doc = "Bits 24:26 - Clock Source Select"]
242    #[inline(always)]
243    #[must_use]
244    pub fn clk_src_sel(&mut self) -> CLK_SRC_SEL_W<LEDC_CLK_SPEC> {
245        CLK_SRC_SEL_W::new(self, 24)
246    }
247    #[doc = "Bit 31 - Gating Clock"]
248    #[inline(always)]
249    #[must_use]
250    pub fn clk_gating(&mut self) -> CLK_GATING_W<LEDC_CLK_SPEC> {
251        CLK_GATING_W::new(self, 31)
252    }
253    #[doc = r" Writes raw bits to the register."]
254    #[doc = r""]
255    #[doc = r" # Safety"]
256    #[doc = r""]
257    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
258    #[inline(always)]
259    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
260        self.bits = bits;
261        self
262    }
263}
264#[doc = "LEDC Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ledc_clk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ledc_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
265pub struct LEDC_CLK_SPEC;
266impl crate::RegisterSpec for LEDC_CLK_SPEC {
267    type Ux = u32;
268}
269#[doc = "`read()` method returns [`ledc_clk::R`](R) reader structure"]
270impl crate::Readable for LEDC_CLK_SPEC {}
271#[doc = "`write(|w| ..)` method takes [`ledc_clk::W`](W) writer structure"]
272impl crate::Writable for LEDC_CLK_SPEC {
273    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
274    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
275}
276#[doc = "`reset()` method sets ledc_clk to value 0"]
277impl crate::Resettable for LEDC_CLK_SPEC {
278    const RESET_VALUE: Self::Ux = 0;
279}
d1_pac/ccu/ledc_clk.rs

d1_pac/ccu/
ledc_clk.rs
