d1_pac/ccu/
emac_25m_clk.rs

1#[doc = "Register `emac_25m_clk` reader"]
2pub type R = crate::R<EMAC_25M_CLK_SPEC>;
3#[doc = "Register `emac_25m_clk` writer"]
4pub type W = crate::W<EMAC_25M_CLK_SPEC>;
5#[doc = "Field `clk_gating` reader - Gating Special Clock"]
6pub type CLK_GATING_R = crate::BitReader<CLK_GATING_A>;
7#[doc = "Gating Special Clock\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum CLK_GATING_A {
10    #[doc = "0: `0`"]
11    OFF = 0,
12    #[doc = "1: `1`"]
13    ON = 1,
14}
15impl From<CLK_GATING_A> for bool {
16    #[inline(always)]
17    fn from(variant: CLK_GATING_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl CLK_GATING_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> CLK_GATING_A {
25        match self.bits {
26            false => CLK_GATING_A::OFF,
27            true => CLK_GATING_A::ON,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_off(&self) -> bool {
33        *self == CLK_GATING_A::OFF
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_on(&self) -> bool {
38        *self == CLK_GATING_A::ON
39    }
40}
41#[doc = "Field `clk_gating` writer - Gating Special Clock"]
42pub type CLK_GATING_W<'a, REG> = crate::BitWriter<'a, REG, CLK_GATING_A>;
43impl<'a, REG> CLK_GATING_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn off(self) -> &'a mut crate::W<REG> {
50        self.variant(CLK_GATING_A::OFF)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn on(self) -> &'a mut crate::W<REG> {
55        self.variant(CLK_GATING_A::ON)
56    }
57}
58#[doc = "Field `clk_src_gating` reader - Gating the Source Clock of Special Clock"]
59pub type CLK_SRC_GATING_R = crate::BitReader<CLK_SRC_GATING_A>;
60#[doc = "Gating the Source Clock of Special Clock\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum CLK_SRC_GATING_A {
63    #[doc = "0: `0`"]
64    OFF = 0,
65    #[doc = "1: `1`"]
66    ON = 1,
67}
68impl From<CLK_SRC_GATING_A> for bool {
69    #[inline(always)]
70    fn from(variant: CLK_SRC_GATING_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl CLK_SRC_GATING_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> CLK_SRC_GATING_A {
78        match self.bits {
79            false => CLK_SRC_GATING_A::OFF,
80            true => CLK_SRC_GATING_A::ON,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_off(&self) -> bool {
86        *self == CLK_SRC_GATING_A::OFF
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_on(&self) -> bool {
91        *self == CLK_SRC_GATING_A::ON
92    }
93}
94#[doc = "Field `clk_src_gating` writer - Gating the Source Clock of Special Clock"]
95pub type CLK_SRC_GATING_W<'a, REG> = crate::BitWriter<'a, REG, CLK_SRC_GATING_A>;
96impl<'a, REG> CLK_SRC_GATING_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn off(self) -> &'a mut crate::W<REG> {
103        self.variant(CLK_SRC_GATING_A::OFF)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn on(self) -> &'a mut crate::W<REG> {
108        self.variant(CLK_SRC_GATING_A::ON)
109    }
110}
111impl R {
112    #[doc = "Bit 31 - Gating Special Clock"]
113    #[inline(always)]
114    pub fn clk_gating(&self) -> CLK_GATING_R {
115        CLK_GATING_R::new(((self.bits >> 31) & 1) != 0)
116    }
117    #[doc = "Bit 31 - Gating the Source Clock of Special Clock"]
118    #[inline(always)]
119    pub fn clk_src_gating(&self) -> CLK_SRC_GATING_R {
120        CLK_SRC_GATING_R::new(((self.bits >> 31) & 1) != 0)
121    }
122}
123impl W {
124    #[doc = "Bit 31 - Gating Special Clock"]
125    #[inline(always)]
126    #[must_use]
127    pub fn clk_gating(&mut self) -> CLK_GATING_W<EMAC_25M_CLK_SPEC> {
128        CLK_GATING_W::new(self, 31)
129    }
130    #[doc = "Bit 31 - Gating the Source Clock of Special Clock"]
131    #[inline(always)]
132    #[must_use]
133    pub fn clk_src_gating(&mut self) -> CLK_SRC_GATING_W<EMAC_25M_CLK_SPEC> {
134        CLK_SRC_GATING_W::new(self, 31)
135    }
136    #[doc = r" Writes raw bits to the register."]
137    #[doc = r""]
138    #[doc = r" # Safety"]
139    #[doc = r""]
140    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
141    #[inline(always)]
142    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
143        self.bits = bits;
144        self
145    }
146}
147#[doc = "EMAC_25M Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emac_25m_clk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emac_25m_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
148pub struct EMAC_25M_CLK_SPEC;
149impl crate::RegisterSpec for EMAC_25M_CLK_SPEC {
150    type Ux = u32;
151}
152#[doc = "`read()` method returns [`emac_25m_clk::R`](R) reader structure"]
153impl crate::Readable for EMAC_25M_CLK_SPEC {}
154#[doc = "`write(|w| ..)` method takes [`emac_25m_clk::W`](W) writer structure"]
155impl crate::Writable for EMAC_25M_CLK_SPEC {
156    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
157    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
158}
159#[doc = "`reset()` method sets emac_25m_clk to value 0"]
160impl crate::Resettable for EMAC_25M_CLK_SPEC {
161    const RESET_VALUE: Self::Ux = 0;
162}
d1_pac/ccu/emac_25m_clk.rs

d1_pac/ccu/
emac_25m_clk.rs
