d1_pac/ccu/
dsi_clk.rs

1#[doc = "Register `dsi_clk` reader"]
2pub type R = crate::R<DSI_CLK_SPEC>;
3#[doc = "Register `dsi_clk` writer"]
4pub type W = crate::W<DSI_CLK_SPEC>;
5#[doc = "Field `factor_m` reader - Factor M"]
6pub type FACTOR_M_R = crate::FieldReader;
7#[doc = "Field `factor_m` writer - Factor M"]
8pub type FACTOR_M_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `clk_src_sel` reader - Clock Source Select"]
10pub type CLK_SRC_SEL_R = crate::FieldReader<CLK_SRC_SEL_A>;
11#[doc = "Clock Source Select\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13#[repr(u8)]
14pub enum CLK_SRC_SEL_A {
15    #[doc = "0: `0`"]
16    HOSC = 0,
17    #[doc = "1: `1`"]
18    PLL_PERI_1X = 1,
19    #[doc = "2: `10`"]
20    PLL_VIDEO0_2X = 2,
21    #[doc = "3: `11`"]
22    PLL_VIDEO1_2X = 3,
23    #[doc = "4: `100`"]
24    PLL_AUDIO1_DIV2 = 4,
25}
26impl From<CLK_SRC_SEL_A> for u8 {
27    #[inline(always)]
28    fn from(variant: CLK_SRC_SEL_A) -> Self {
29        variant as _
30    }
31}
32impl crate::FieldSpec for CLK_SRC_SEL_A {
33    type Ux = u8;
34}
35impl CLK_SRC_SEL_R {
36    #[doc = "Get enumerated values variant"]
37    #[inline(always)]
38    pub const fn variant(&self) -> Option<CLK_SRC_SEL_A> {
39        match self.bits {
40            0 => Some(CLK_SRC_SEL_A::HOSC),
41            1 => Some(CLK_SRC_SEL_A::PLL_PERI_1X),
42            2 => Some(CLK_SRC_SEL_A::PLL_VIDEO0_2X),
43            3 => Some(CLK_SRC_SEL_A::PLL_VIDEO1_2X),
44            4 => Some(CLK_SRC_SEL_A::PLL_AUDIO1_DIV2),
45            _ => None,
46        }
47    }
48    #[doc = "`0`"]
49    #[inline(always)]
50    pub fn is_hosc(&self) -> bool {
51        *self == CLK_SRC_SEL_A::HOSC
52    }
53    #[doc = "`1`"]
54    #[inline(always)]
55    pub fn is_pll_peri_1x(&self) -> bool {
56        *self == CLK_SRC_SEL_A::PLL_PERI_1X
57    }
58    #[doc = "`10`"]
59    #[inline(always)]
60    pub fn is_pll_video0_2x(&self) -> bool {
61        *self == CLK_SRC_SEL_A::PLL_VIDEO0_2X
62    }
63    #[doc = "`11`"]
64    #[inline(always)]
65    pub fn is_pll_video1_2x(&self) -> bool {
66        *self == CLK_SRC_SEL_A::PLL_VIDEO1_2X
67    }
68    #[doc = "`100`"]
69    #[inline(always)]
70    pub fn is_pll_audio1_div2(&self) -> bool {
71        *self == CLK_SRC_SEL_A::PLL_AUDIO1_DIV2
72    }
73}
74#[doc = "Field `clk_src_sel` writer - Clock Source Select"]
75pub type CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CLK_SRC_SEL_A>;
76impl<'a, REG> CLK_SRC_SEL_W<'a, REG>
77where
78    REG: crate::Writable + crate::RegisterSpec,
79    REG::Ux: From<u8>,
80{
81    #[doc = "`0`"]
82    #[inline(always)]
83    pub fn hosc(self) -> &'a mut crate::W<REG> {
84        self.variant(CLK_SRC_SEL_A::HOSC)
85    }
86    #[doc = "`1`"]
87    #[inline(always)]
88    pub fn pll_peri_1x(self) -> &'a mut crate::W<REG> {
89        self.variant(CLK_SRC_SEL_A::PLL_PERI_1X)
90    }
91    #[doc = "`10`"]
92    #[inline(always)]
93    pub fn pll_video0_2x(self) -> &'a mut crate::W<REG> {
94        self.variant(CLK_SRC_SEL_A::PLL_VIDEO0_2X)
95    }
96    #[doc = "`11`"]
97    #[inline(always)]
98    pub fn pll_video1_2x(self) -> &'a mut crate::W<REG> {
99        self.variant(CLK_SRC_SEL_A::PLL_VIDEO1_2X)
100    }
101    #[doc = "`100`"]
102    #[inline(always)]
103    pub fn pll_audio1_div2(self) -> &'a mut crate::W<REG> {
104        self.variant(CLK_SRC_SEL_A::PLL_AUDIO1_DIV2)
105    }
106}
107#[doc = "Field `clk_gating` reader - Gating Clock"]
108pub type CLK_GATING_R = crate::BitReader<CLK_GATING_A>;
109#[doc = "Gating Clock\n\nValue on reset: 0"]
110#[derive(Clone, Copy, Debug, PartialEq, Eq)]
111pub enum CLK_GATING_A {
112    #[doc = "0: `0`"]
113    OFF = 0,
114    #[doc = "1: `1`"]
115    ON = 1,
116}
117impl From<CLK_GATING_A> for bool {
118    #[inline(always)]
119    fn from(variant: CLK_GATING_A) -> Self {
120        variant as u8 != 0
121    }
122}
123impl CLK_GATING_R {
124    #[doc = "Get enumerated values variant"]
125    #[inline(always)]
126    pub const fn variant(&self) -> CLK_GATING_A {
127        match self.bits {
128            false => CLK_GATING_A::OFF,
129            true => CLK_GATING_A::ON,
130        }
131    }
132    #[doc = "`0`"]
133    #[inline(always)]
134    pub fn is_off(&self) -> bool {
135        *self == CLK_GATING_A::OFF
136    }
137    #[doc = "`1`"]
138    #[inline(always)]
139    pub fn is_on(&self) -> bool {
140        *self == CLK_GATING_A::ON
141    }
142}
143#[doc = "Field `clk_gating` writer - Gating Clock"]
144pub type CLK_GATING_W<'a, REG> = crate::BitWriter<'a, REG, CLK_GATING_A>;
145impl<'a, REG> CLK_GATING_W<'a, REG>
146where
147    REG: crate::Writable + crate::RegisterSpec,
148{
149    #[doc = "`0`"]
150    #[inline(always)]
151    pub fn off(self) -> &'a mut crate::W<REG> {
152        self.variant(CLK_GATING_A::OFF)
153    }
154    #[doc = "`1`"]
155    #[inline(always)]
156    pub fn on(self) -> &'a mut crate::W<REG> {
157        self.variant(CLK_GATING_A::ON)
158    }
159}
160impl R {
161    #[doc = "Bits 0:3 - Factor M"]
162    #[inline(always)]
163    pub fn factor_m(&self) -> FACTOR_M_R {
164        FACTOR_M_R::new((self.bits & 0x0f) as u8)
165    }
166    #[doc = "Bits 24:26 - Clock Source Select"]
167    #[inline(always)]
168    pub fn clk_src_sel(&self) -> CLK_SRC_SEL_R {
169        CLK_SRC_SEL_R::new(((self.bits >> 24) & 7) as u8)
170    }
171    #[doc = "Bit 31 - Gating Clock"]
172    #[inline(always)]
173    pub fn clk_gating(&self) -> CLK_GATING_R {
174        CLK_GATING_R::new(((self.bits >> 31) & 1) != 0)
175    }
176}
177impl W {
178    #[doc = "Bits 0:3 - Factor M"]
179    #[inline(always)]
180    #[must_use]
181    pub fn factor_m(&mut self) -> FACTOR_M_W<DSI_CLK_SPEC> {
182        FACTOR_M_W::new(self, 0)
183    }
184    #[doc = "Bits 24:26 - Clock Source Select"]
185    #[inline(always)]
186    #[must_use]
187    pub fn clk_src_sel(&mut self) -> CLK_SRC_SEL_W<DSI_CLK_SPEC> {
188        CLK_SRC_SEL_W::new(self, 24)
189    }
190    #[doc = "Bit 31 - Gating Clock"]
191    #[inline(always)]
192    #[must_use]
193    pub fn clk_gating(&mut self) -> CLK_GATING_W<DSI_CLK_SPEC> {
194        CLK_GATING_W::new(self, 31)
195    }
196    #[doc = r" Writes raw bits to the register."]
197    #[doc = r""]
198    #[doc = r" # Safety"]
199    #[doc = r""]
200    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
201    #[inline(always)]
202    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
203        self.bits = bits;
204        self
205    }
206}
207#[doc = "DSI Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsi_clk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dsi_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
208pub struct DSI_CLK_SPEC;
209impl crate::RegisterSpec for DSI_CLK_SPEC {
210    type Ux = u32;
211}
212#[doc = "`read()` method returns [`dsi_clk::R`](R) reader structure"]
213impl crate::Readable for DSI_CLK_SPEC {}
214#[doc = "`write(|w| ..)` method takes [`dsi_clk::W`](W) writer structure"]
215impl crate::Writable for DSI_CLK_SPEC {
216    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
217    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
218}
219#[doc = "`reset()` method sets dsi_clk to value 0"]
220impl crate::Resettable for DSI_CLK_SPEC {
221    const RESET_VALUE: Self::Ux = 0;
222}
d1_pac/ccu/dsi_clk.rs

d1_pac/ccu/
dsi_clk.rs
