d1_pac/ccu/
dram_clk.rs

1#[doc = "Register `dram_clk` reader"]
2pub type R = crate::R<DRAM_CLK_SPEC>;
3#[doc = "Register `dram_clk` writer"]
4pub type W = crate::W<DRAM_CLK_SPEC>;
5#[doc = "Field `dram_div1` reader - Factor M"]
6pub type DRAM_DIV1_R = crate::FieldReader;
7#[doc = "Field `dram_div1` writer - Factor M"]
8pub type DRAM_DIV1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `dram_div2` reader - Factor N"]
10pub type DRAM_DIV2_R = crate::FieldReader<DRAM_DIV2_A>;
11#[doc = "Factor N\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13#[repr(u8)]
14pub enum DRAM_DIV2_A {
15    #[doc = "0: `0`"]
16    N1 = 0,
17    #[doc = "1: `1`"]
18    N2 = 1,
19    #[doc = "2: `10`"]
20    N4 = 2,
21    #[doc = "3: `11`"]
22    N8 = 3,
23}
24impl From<DRAM_DIV2_A> for u8 {
25    #[inline(always)]
26    fn from(variant: DRAM_DIV2_A) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for DRAM_DIV2_A {
31    type Ux = u8;
32}
33impl DRAM_DIV2_R {
34    #[doc = "Get enumerated values variant"]
35    #[inline(always)]
36    pub const fn variant(&self) -> DRAM_DIV2_A {
37        match self.bits {
38            0 => DRAM_DIV2_A::N1,
39            1 => DRAM_DIV2_A::N2,
40            2 => DRAM_DIV2_A::N4,
41            3 => DRAM_DIV2_A::N8,
42            _ => unreachable!(),
43        }
44    }
45    #[doc = "`0`"]
46    #[inline(always)]
47    pub fn is_n1(&self) -> bool {
48        *self == DRAM_DIV2_A::N1
49    }
50    #[doc = "`1`"]
51    #[inline(always)]
52    pub fn is_n2(&self) -> bool {
53        *self == DRAM_DIV2_A::N2
54    }
55    #[doc = "`10`"]
56    #[inline(always)]
57    pub fn is_n4(&self) -> bool {
58        *self == DRAM_DIV2_A::N4
59    }
60    #[doc = "`11`"]
61    #[inline(always)]
62    pub fn is_n8(&self) -> bool {
63        *self == DRAM_DIV2_A::N8
64    }
65}
66#[doc = "Field `dram_div2` writer - Factor N"]
67pub type DRAM_DIV2_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DRAM_DIV2_A>;
68impl<'a, REG> DRAM_DIV2_W<'a, REG>
69where
70    REG: crate::Writable + crate::RegisterSpec,
71    REG::Ux: From<u8>,
72{
73    #[doc = "`0`"]
74    #[inline(always)]
75    pub fn n1(self) -> &'a mut crate::W<REG> {
76        self.variant(DRAM_DIV2_A::N1)
77    }
78    #[doc = "`1`"]
79    #[inline(always)]
80    pub fn n2(self) -> &'a mut crate::W<REG> {
81        self.variant(DRAM_DIV2_A::N2)
82    }
83    #[doc = "`10`"]
84    #[inline(always)]
85    pub fn n4(self) -> &'a mut crate::W<REG> {
86        self.variant(DRAM_DIV2_A::N4)
87    }
88    #[doc = "`11`"]
89    #[inline(always)]
90    pub fn n8(self) -> &'a mut crate::W<REG> {
91        self.variant(DRAM_DIV2_A::N8)
92    }
93}
94#[doc = "Field `clk_src_sel` reader - Clock Source Select"]
95pub type CLK_SRC_SEL_R = crate::FieldReader<CLK_SRC_SEL_A>;
96#[doc = "Clock Source Select\n\nValue on reset: 0"]
97#[derive(Clone, Copy, Debug, PartialEq, Eq)]
98#[repr(u8)]
99pub enum CLK_SRC_SEL_A {
100    #[doc = "0: `0`"]
101    PLL_DDR = 0,
102    #[doc = "1: `1`"]
103    PLL_AUDIO1_DIV2 = 1,
104    #[doc = "2: `10`"]
105    PLL_PERI_2X = 2,
106    #[doc = "3: `11`"]
107    PLL_PERI_800M = 3,
108}
109impl From<CLK_SRC_SEL_A> for u8 {
110    #[inline(always)]
111    fn from(variant: CLK_SRC_SEL_A) -> Self {
112        variant as _
113    }
114}
115impl crate::FieldSpec for CLK_SRC_SEL_A {
116    type Ux = u8;
117}
118impl CLK_SRC_SEL_R {
119    #[doc = "Get enumerated values variant"]
120    #[inline(always)]
121    pub const fn variant(&self) -> Option<CLK_SRC_SEL_A> {
122        match self.bits {
123            0 => Some(CLK_SRC_SEL_A::PLL_DDR),
124            1 => Some(CLK_SRC_SEL_A::PLL_AUDIO1_DIV2),
125            2 => Some(CLK_SRC_SEL_A::PLL_PERI_2X),
126            3 => Some(CLK_SRC_SEL_A::PLL_PERI_800M),
127            _ => None,
128        }
129    }
130    #[doc = "`0`"]
131    #[inline(always)]
132    pub fn is_pll_ddr(&self) -> bool {
133        *self == CLK_SRC_SEL_A::PLL_DDR
134    }
135    #[doc = "`1`"]
136    #[inline(always)]
137    pub fn is_pll_audio1_div2(&self) -> bool {
138        *self == CLK_SRC_SEL_A::PLL_AUDIO1_DIV2
139    }
140    #[doc = "`10`"]
141    #[inline(always)]
142    pub fn is_pll_peri_2x(&self) -> bool {
143        *self == CLK_SRC_SEL_A::PLL_PERI_2X
144    }
145    #[doc = "`11`"]
146    #[inline(always)]
147    pub fn is_pll_peri_800m(&self) -> bool {
148        *self == CLK_SRC_SEL_A::PLL_PERI_800M
149    }
150}
151#[doc = "Field `clk_src_sel` writer - Clock Source Select"]
152pub type CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CLK_SRC_SEL_A>;
153impl<'a, REG> CLK_SRC_SEL_W<'a, REG>
154where
155    REG: crate::Writable + crate::RegisterSpec,
156    REG::Ux: From<u8>,
157{
158    #[doc = "`0`"]
159    #[inline(always)]
160    pub fn pll_ddr(self) -> &'a mut crate::W<REG> {
161        self.variant(CLK_SRC_SEL_A::PLL_DDR)
162    }
163    #[doc = "`1`"]
164    #[inline(always)]
165    pub fn pll_audio1_div2(self) -> &'a mut crate::W<REG> {
166        self.variant(CLK_SRC_SEL_A::PLL_AUDIO1_DIV2)
167    }
168    #[doc = "`10`"]
169    #[inline(always)]
170    pub fn pll_peri_2x(self) -> &'a mut crate::W<REG> {
171        self.variant(CLK_SRC_SEL_A::PLL_PERI_2X)
172    }
173    #[doc = "`11`"]
174    #[inline(always)]
175    pub fn pll_peri_800m(self) -> &'a mut crate::W<REG> {
176        self.variant(CLK_SRC_SEL_A::PLL_PERI_800M)
177    }
178}
179#[doc = "Field `sdrclk_upd` reader - SDRCLK Configuration 0 Update"]
180pub type SDRCLK_UPD_R = crate::BitReader<SDRCLK_UPD_A>;
181#[doc = "SDRCLK Configuration 0 Update\n\nValue on reset: 0"]
182#[derive(Clone, Copy, Debug, PartialEq, Eq)]
183pub enum SDRCLK_UPD_A {
184    #[doc = "0: `0`"]
185    INVALID = 0,
186    #[doc = "1: `1`"]
187    VALID = 1,
188}
189impl From<SDRCLK_UPD_A> for bool {
190    #[inline(always)]
191    fn from(variant: SDRCLK_UPD_A) -> Self {
192        variant as u8 != 0
193    }
194}
195impl SDRCLK_UPD_R {
196    #[doc = "Get enumerated values variant"]
197    #[inline(always)]
198    pub const fn variant(&self) -> SDRCLK_UPD_A {
199        match self.bits {
200            false => SDRCLK_UPD_A::INVALID,
201            true => SDRCLK_UPD_A::VALID,
202        }
203    }
204    #[doc = "`0`"]
205    #[inline(always)]
206    pub fn is_invalid(&self) -> bool {
207        *self == SDRCLK_UPD_A::INVALID
208    }
209    #[doc = "`1`"]
210    #[inline(always)]
211    pub fn is_valid(&self) -> bool {
212        *self == SDRCLK_UPD_A::VALID
213    }
214}
215#[doc = "Field `sdrclk_upd` writer - SDRCLK Configuration 0 Update"]
216pub type SDRCLK_UPD_W<'a, REG> = crate::BitWriter<'a, REG, SDRCLK_UPD_A>;
217impl<'a, REG> SDRCLK_UPD_W<'a, REG>
218where
219    REG: crate::Writable + crate::RegisterSpec,
220{
221    #[doc = "`0`"]
222    #[inline(always)]
223    pub fn invalid(self) -> &'a mut crate::W<REG> {
224        self.variant(SDRCLK_UPD_A::INVALID)
225    }
226    #[doc = "`1`"]
227    #[inline(always)]
228    pub fn valid(self) -> &'a mut crate::W<REG> {
229        self.variant(SDRCLK_UPD_A::VALID)
230    }
231}
232#[doc = "Field `clk_gating` reader - Gating Clock"]
233pub type CLK_GATING_R = crate::BitReader<CLK_GATING_A>;
234#[doc = "Gating Clock\n\nValue on reset: 0"]
235#[derive(Clone, Copy, Debug, PartialEq, Eq)]
236pub enum CLK_GATING_A {
237    #[doc = "0: `0`"]
238    OFF = 0,
239    #[doc = "1: `1`"]
240    ON = 1,
241}
242impl From<CLK_GATING_A> for bool {
243    #[inline(always)]
244    fn from(variant: CLK_GATING_A) -> Self {
245        variant as u8 != 0
246    }
247}
248impl CLK_GATING_R {
249    #[doc = "Get enumerated values variant"]
250    #[inline(always)]
251    pub const fn variant(&self) -> CLK_GATING_A {
252        match self.bits {
253            false => CLK_GATING_A::OFF,
254            true => CLK_GATING_A::ON,
255        }
256    }
257    #[doc = "`0`"]
258    #[inline(always)]
259    pub fn is_off(&self) -> bool {
260        *self == CLK_GATING_A::OFF
261    }
262    #[doc = "`1`"]
263    #[inline(always)]
264    pub fn is_on(&self) -> bool {
265        *self == CLK_GATING_A::ON
266    }
267}
268#[doc = "Field `clk_gating` writer - Gating Clock"]
269pub type CLK_GATING_W<'a, REG> = crate::BitWriter<'a, REG, CLK_GATING_A>;
270impl<'a, REG> CLK_GATING_W<'a, REG>
271where
272    REG: crate::Writable + crate::RegisterSpec,
273{
274    #[doc = "`0`"]
275    #[inline(always)]
276    pub fn off(self) -> &'a mut crate::W<REG> {
277        self.variant(CLK_GATING_A::OFF)
278    }
279    #[doc = "`1`"]
280    #[inline(always)]
281    pub fn on(self) -> &'a mut crate::W<REG> {
282        self.variant(CLK_GATING_A::ON)
283    }
284}
285impl R {
286    #[doc = "Bits 0:1 - Factor M"]
287    #[inline(always)]
288    pub fn dram_div1(&self) -> DRAM_DIV1_R {
289        DRAM_DIV1_R::new((self.bits & 3) as u8)
290    }
291    #[doc = "Bits 8:9 - Factor N"]
292    #[inline(always)]
293    pub fn dram_div2(&self) -> DRAM_DIV2_R {
294        DRAM_DIV2_R::new(((self.bits >> 8) & 3) as u8)
295    }
296    #[doc = "Bits 24:26 - Clock Source Select"]
297    #[inline(always)]
298    pub fn clk_src_sel(&self) -> CLK_SRC_SEL_R {
299        CLK_SRC_SEL_R::new(((self.bits >> 24) & 7) as u8)
300    }
301    #[doc = "Bit 27 - SDRCLK Configuration 0 Update"]
302    #[inline(always)]
303    pub fn sdrclk_upd(&self) -> SDRCLK_UPD_R {
304        SDRCLK_UPD_R::new(((self.bits >> 27) & 1) != 0)
305    }
306    #[doc = "Bit 31 - Gating Clock"]
307    #[inline(always)]
308    pub fn clk_gating(&self) -> CLK_GATING_R {
309        CLK_GATING_R::new(((self.bits >> 31) & 1) != 0)
310    }
311}
312impl W {
313    #[doc = "Bits 0:1 - Factor M"]
314    #[inline(always)]
315    #[must_use]
316    pub fn dram_div1(&mut self) -> DRAM_DIV1_W<DRAM_CLK_SPEC> {
317        DRAM_DIV1_W::new(self, 0)
318    }
319    #[doc = "Bits 8:9 - Factor N"]
320    #[inline(always)]
321    #[must_use]
322    pub fn dram_div2(&mut self) -> DRAM_DIV2_W<DRAM_CLK_SPEC> {
323        DRAM_DIV2_W::new(self, 8)
324    }
325    #[doc = "Bits 24:26 - Clock Source Select"]
326    #[inline(always)]
327    #[must_use]
328    pub fn clk_src_sel(&mut self) -> CLK_SRC_SEL_W<DRAM_CLK_SPEC> {
329        CLK_SRC_SEL_W::new(self, 24)
330    }
331    #[doc = "Bit 27 - SDRCLK Configuration 0 Update"]
332    #[inline(always)]
333    #[must_use]
334    pub fn sdrclk_upd(&mut self) -> SDRCLK_UPD_W<DRAM_CLK_SPEC> {
335        SDRCLK_UPD_W::new(self, 27)
336    }
337    #[doc = "Bit 31 - Gating Clock"]
338    #[inline(always)]
339    #[must_use]
340    pub fn clk_gating(&mut self) -> CLK_GATING_W<DRAM_CLK_SPEC> {
341        CLK_GATING_W::new(self, 31)
342    }
343    #[doc = r" Writes raw bits to the register."]
344    #[doc = r""]
345    #[doc = r" # Safety"]
346    #[doc = r""]
347    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
348    #[inline(always)]
349    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
350        self.bits = bits;
351        self
352    }
353}
354#[doc = "DRAM Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dram_clk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dram_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
355pub struct DRAM_CLK_SPEC;
356impl crate::RegisterSpec for DRAM_CLK_SPEC {
357    type Ux = u32;
358}
359#[doc = "`read()` method returns [`dram_clk::R`](R) reader structure"]
360impl crate::Readable for DRAM_CLK_SPEC {}
361#[doc = "`write(|w| ..)` method takes [`dram_clk::W`](W) writer structure"]
362impl crate::Writable for DRAM_CLK_SPEC {
363    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
364    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
365}
366#[doc = "`reset()` method sets dram_clk to value 0"]
367impl crate::Resettable for DRAM_CLK_SPEC {
368    const RESET_VALUE: Self::Ux = 0;
369}
d1_pac/ccu/dram_clk.rs

d1_pac/ccu/
dram_clk.rs
