1#[doc = "Register `csi_clk` reader"]
2pub type R = crate::R<CSI_CLK_SPEC>;
3#[doc = "Register `csi_clk` writer"]
4pub type W = crate::W<CSI_CLK_SPEC>;
5#[doc = "Field `factor_m` reader - Factor M"]
6pub type FACTOR_M_R = crate::FieldReader;
7#[doc = "Field `factor_m` writer - Factor M"]
8pub type FACTOR_M_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `clk_src_sel` reader - Clock Source Select"]
10pub type CLK_SRC_SEL_R = crate::FieldReader<CLK_SRC_SEL_A>;
11#[doc = "Clock Source Select\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13#[repr(u8)]
14pub enum CLK_SRC_SEL_A {
15 #[doc = "0: `0`"]
16 PLL_PERI_2X = 0,
17 #[doc = "1: `1`"]
18 PLL_VIDEO0_2X = 1,
19 #[doc = "2: `10`"]
20 PLL_VIDEO1_2X = 2,
21}
22impl From<CLK_SRC_SEL_A> for u8 {
23 #[inline(always)]
24 fn from(variant: CLK_SRC_SEL_A) -> Self {
25 variant as _
26 }
27}
28impl crate::FieldSpec for CLK_SRC_SEL_A {
29 type Ux = u8;
30}
31impl CLK_SRC_SEL_R {
32 #[doc = "Get enumerated values variant"]
33 #[inline(always)]
34 pub const fn variant(&self) -> Option<CLK_SRC_SEL_A> {
35 match self.bits {
36 0 => Some(CLK_SRC_SEL_A::PLL_PERI_2X),
37 1 => Some(CLK_SRC_SEL_A::PLL_VIDEO0_2X),
38 2 => Some(CLK_SRC_SEL_A::PLL_VIDEO1_2X),
39 _ => None,
40 }
41 }
42 #[doc = "`0`"]
43 #[inline(always)]
44 pub fn is_pll_peri_2x(&self) -> bool {
45 *self == CLK_SRC_SEL_A::PLL_PERI_2X
46 }
47 #[doc = "`1`"]
48 #[inline(always)]
49 pub fn is_pll_video0_2x(&self) -> bool {
50 *self == CLK_SRC_SEL_A::PLL_VIDEO0_2X
51 }
52 #[doc = "`10`"]
53 #[inline(always)]
54 pub fn is_pll_video1_2x(&self) -> bool {
55 *self == CLK_SRC_SEL_A::PLL_VIDEO1_2X
56 }
57}
58#[doc = "Field `clk_src_sel` writer - Clock Source Select"]
59pub type CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CLK_SRC_SEL_A>;
60impl<'a, REG> CLK_SRC_SEL_W<'a, REG>
61where
62 REG: crate::Writable + crate::RegisterSpec,
63 REG::Ux: From<u8>,
64{
65 #[doc = "`0`"]
66 #[inline(always)]
67 pub fn pll_peri_2x(self) -> &'a mut crate::W<REG> {
68 self.variant(CLK_SRC_SEL_A::PLL_PERI_2X)
69 }
70 #[doc = "`1`"]
71 #[inline(always)]
72 pub fn pll_video0_2x(self) -> &'a mut crate::W<REG> {
73 self.variant(CLK_SRC_SEL_A::PLL_VIDEO0_2X)
74 }
75 #[doc = "`10`"]
76 #[inline(always)]
77 pub fn pll_video1_2x(self) -> &'a mut crate::W<REG> {
78 self.variant(CLK_SRC_SEL_A::PLL_VIDEO1_2X)
79 }
80}
81#[doc = "Field `clk_gating` reader - Gating Clock"]
82pub type CLK_GATING_R = crate::BitReader<CLK_GATING_A>;
83#[doc = "Gating Clock\n\nValue on reset: 0"]
84#[derive(Clone, Copy, Debug, PartialEq, Eq)]
85pub enum CLK_GATING_A {
86 #[doc = "0: `0`"]
87 OFF = 0,
88 #[doc = "1: `1`"]
89 ON = 1,
90}
91impl From<CLK_GATING_A> for bool {
92 #[inline(always)]
93 fn from(variant: CLK_GATING_A) -> Self {
94 variant as u8 != 0
95 }
96}
97impl CLK_GATING_R {
98 #[doc = "Get enumerated values variant"]
99 #[inline(always)]
100 pub const fn variant(&self) -> CLK_GATING_A {
101 match self.bits {
102 false => CLK_GATING_A::OFF,
103 true => CLK_GATING_A::ON,
104 }
105 }
106 #[doc = "`0`"]
107 #[inline(always)]
108 pub fn is_off(&self) -> bool {
109 *self == CLK_GATING_A::OFF
110 }
111 #[doc = "`1`"]
112 #[inline(always)]
113 pub fn is_on(&self) -> bool {
114 *self == CLK_GATING_A::ON
115 }
116}
117#[doc = "Field `clk_gating` writer - Gating Clock"]
118pub type CLK_GATING_W<'a, REG> = crate::BitWriter<'a, REG, CLK_GATING_A>;
119impl<'a, REG> CLK_GATING_W<'a, REG>
120where
121 REG: crate::Writable + crate::RegisterSpec,
122{
123 #[doc = "`0`"]
124 #[inline(always)]
125 pub fn off(self) -> &'a mut crate::W<REG> {
126 self.variant(CLK_GATING_A::OFF)
127 }
128 #[doc = "`1`"]
129 #[inline(always)]
130 pub fn on(self) -> &'a mut crate::W<REG> {
131 self.variant(CLK_GATING_A::ON)
132 }
133}
134impl R {
135 #[doc = "Bits 0:3 - Factor M"]
136 #[inline(always)]
137 pub fn factor_m(&self) -> FACTOR_M_R {
138 FACTOR_M_R::new((self.bits & 0x0f) as u8)
139 }
140 #[doc = "Bits 24:26 - Clock Source Select"]
141 #[inline(always)]
142 pub fn clk_src_sel(&self) -> CLK_SRC_SEL_R {
143 CLK_SRC_SEL_R::new(((self.bits >> 24) & 7) as u8)
144 }
145 #[doc = "Bit 31 - Gating Clock"]
146 #[inline(always)]
147 pub fn clk_gating(&self) -> CLK_GATING_R {
148 CLK_GATING_R::new(((self.bits >> 31) & 1) != 0)
149 }
150}
151impl W {
152 #[doc = "Bits 0:3 - Factor M"]
153 #[inline(always)]
154 #[must_use]
155 pub fn factor_m(&mut self) -> FACTOR_M_W<CSI_CLK_SPEC> {
156 FACTOR_M_W::new(self, 0)
157 }
158 #[doc = "Bits 24:26 - Clock Source Select"]
159 #[inline(always)]
160 #[must_use]
161 pub fn clk_src_sel(&mut self) -> CLK_SRC_SEL_W<CSI_CLK_SPEC> {
162 CLK_SRC_SEL_W::new(self, 24)
163 }
164 #[doc = "Bit 31 - Gating Clock"]
165 #[inline(always)]
166 #[must_use]
167 pub fn clk_gating(&mut self) -> CLK_GATING_W<CSI_CLK_SPEC> {
168 CLK_GATING_W::new(self, 31)
169 }
170 #[doc = r" Writes raw bits to the register."]
171 #[doc = r""]
172 #[doc = r" # Safety"]
173 #[doc = r""]
174 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
175 #[inline(always)]
176 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
177 self.bits = bits;
178 self
179 }
180}
181#[doc = "CSI Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csi_clk::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csi_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
182pub struct CSI_CLK_SPEC;
183impl crate::RegisterSpec for CSI_CLK_SPEC {
184 type Ux = u32;
185}
186#[doc = "`read()` method returns [`csi_clk::R`](R) reader structure"]
187impl crate::Readable for CSI_CLK_SPEC {}
188#[doc = "`write(|w| ..)` method takes [`csi_clk::W`](W) writer structure"]
189impl crate::Writable for CSI_CLK_SPEC {
190 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
191 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
192}
193#[doc = "`reset()` method sets csi_clk to value 0"]
194impl crate::Resettable for CSI_CLK_SPEC {
195 const RESET_VALUE: Self::Ux = 0;
196}