d1_pac/ccu/
clk27m_fan.rs

1#[doc = "Register `clk27m_fan` reader"]
2pub type R = crate::R<CLK27M_FAN_SPEC>;
3#[doc = "Register `clk27m_fan` writer"]
4pub type W = crate::W<CLK27M_FAN_SPEC>;
5#[doc = "Field `div0` reader - Factor M"]
6pub type DIV0_R = crate::FieldReader;
7#[doc = "Field `div0` writer - Factor M"]
8pub type DIV0_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `div1` reader - Factor N"]
10pub type DIV1_R = crate::FieldReader;
11#[doc = "Field `div1` writer - Factor N"]
12pub type DIV1_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `clk_src_sel` reader - Clock Source Select"]
14pub type CLK_SRC_SEL_R = crate::FieldReader<CLK_SRC_SEL_A>;
15#[doc = "Clock Source Select\n\nValue on reset: 0"]
16#[derive(Clone, Copy, Debug, PartialEq, Eq)]
17#[repr(u8)]
18pub enum CLK_SRC_SEL_A {
19    #[doc = "0: `0`"]
20    PLL_VIDEO0_1X = 0,
21    #[doc = "1: `1`"]
22    PLL_VIDEO1_1X = 1,
23}
24impl From<CLK_SRC_SEL_A> for u8 {
25    #[inline(always)]
26    fn from(variant: CLK_SRC_SEL_A) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for CLK_SRC_SEL_A {
31    type Ux = u8;
32}
33impl CLK_SRC_SEL_R {
34    #[doc = "Get enumerated values variant"]
35    #[inline(always)]
36    pub const fn variant(&self) -> Option<CLK_SRC_SEL_A> {
37        match self.bits {
38            0 => Some(CLK_SRC_SEL_A::PLL_VIDEO0_1X),
39            1 => Some(CLK_SRC_SEL_A::PLL_VIDEO1_1X),
40            _ => None,
41        }
42    }
43    #[doc = "`0`"]
44    #[inline(always)]
45    pub fn is_pll_video0_1x(&self) -> bool {
46        *self == CLK_SRC_SEL_A::PLL_VIDEO0_1X
47    }
48    #[doc = "`1`"]
49    #[inline(always)]
50    pub fn is_pll_video1_1x(&self) -> bool {
51        *self == CLK_SRC_SEL_A::PLL_VIDEO1_1X
52    }
53}
54#[doc = "Field `clk_src_sel` writer - Clock Source Select"]
55pub type CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CLK_SRC_SEL_A>;
56impl<'a, REG> CLK_SRC_SEL_W<'a, REG>
57where
58    REG: crate::Writable + crate::RegisterSpec,
59    REG::Ux: From<u8>,
60{
61    #[doc = "`0`"]
62    #[inline(always)]
63    pub fn pll_video0_1x(self) -> &'a mut crate::W<REG> {
64        self.variant(CLK_SRC_SEL_A::PLL_VIDEO0_1X)
65    }
66    #[doc = "`1`"]
67    #[inline(always)]
68    pub fn pll_video1_1x(self) -> &'a mut crate::W<REG> {
69        self.variant(CLK_SRC_SEL_A::PLL_VIDEO1_1X)
70    }
71}
72#[doc = "Field `gating` reader - Gating for CLK27M"]
73pub type GATING_R = crate::BitReader<GATING_A>;
74#[doc = "Gating for CLK27M\n\nValue on reset: 0"]
75#[derive(Clone, Copy, Debug, PartialEq, Eq)]
76pub enum GATING_A {
77    #[doc = "0: `0`"]
78    OFF = 0,
79    #[doc = "1: `1`"]
80    ON = 1,
81}
82impl From<GATING_A> for bool {
83    #[inline(always)]
84    fn from(variant: GATING_A) -> Self {
85        variant as u8 != 0
86    }
87}
88impl GATING_R {
89    #[doc = "Get enumerated values variant"]
90    #[inline(always)]
91    pub const fn variant(&self) -> GATING_A {
92        match self.bits {
93            false => GATING_A::OFF,
94            true => GATING_A::ON,
95        }
96    }
97    #[doc = "`0`"]
98    #[inline(always)]
99    pub fn is_off(&self) -> bool {
100        *self == GATING_A::OFF
101    }
102    #[doc = "`1`"]
103    #[inline(always)]
104    pub fn is_on(&self) -> bool {
105        *self == GATING_A::ON
106    }
107}
108#[doc = "Field `gating` writer - Gating for CLK27M"]
109pub type GATING_W<'a, REG> = crate::BitWriter<'a, REG, GATING_A>;
110impl<'a, REG> GATING_W<'a, REG>
111where
112    REG: crate::Writable + crate::RegisterSpec,
113{
114    #[doc = "`0`"]
115    #[inline(always)]
116    pub fn off(self) -> &'a mut crate::W<REG> {
117        self.variant(GATING_A::OFF)
118    }
119    #[doc = "`1`"]
120    #[inline(always)]
121    pub fn on(self) -> &'a mut crate::W<REG> {
122        self.variant(GATING_A::ON)
123    }
124}
125impl R {
126    #[doc = "Bits 0:4 - Factor M"]
127    #[inline(always)]
128    pub fn div0(&self) -> DIV0_R {
129        DIV0_R::new((self.bits & 0x1f) as u8)
130    }
131    #[doc = "Bits 8:9 - Factor N"]
132    #[inline(always)]
133    pub fn div1(&self) -> DIV1_R {
134        DIV1_R::new(((self.bits >> 8) & 3) as u8)
135    }
136    #[doc = "Bits 24:25 - Clock Source Select"]
137    #[inline(always)]
138    pub fn clk_src_sel(&self) -> CLK_SRC_SEL_R {
139        CLK_SRC_SEL_R::new(((self.bits >> 24) & 3) as u8)
140    }
141    #[doc = "Bit 31 - Gating for CLK27M"]
142    #[inline(always)]
143    pub fn gating(&self) -> GATING_R {
144        GATING_R::new(((self.bits >> 31) & 1) != 0)
145    }
146}
147impl W {
148    #[doc = "Bits 0:4 - Factor M"]
149    #[inline(always)]
150    #[must_use]
151    pub fn div0(&mut self) -> DIV0_W<CLK27M_FAN_SPEC> {
152        DIV0_W::new(self, 0)
153    }
154    #[doc = "Bits 8:9 - Factor N"]
155    #[inline(always)]
156    #[must_use]
157    pub fn div1(&mut self) -> DIV1_W<CLK27M_FAN_SPEC> {
158        DIV1_W::new(self, 8)
159    }
160    #[doc = "Bits 24:25 - Clock Source Select"]
161    #[inline(always)]
162    #[must_use]
163    pub fn clk_src_sel(&mut self) -> CLK_SRC_SEL_W<CLK27M_FAN_SPEC> {
164        CLK_SRC_SEL_W::new(self, 24)
165    }
166    #[doc = "Bit 31 - Gating for CLK27M"]
167    #[inline(always)]
168    #[must_use]
169    pub fn gating(&mut self) -> GATING_W<CLK27M_FAN_SPEC> {
170        GATING_W::new(self, 31)
171    }
172    #[doc = r" Writes raw bits to the register."]
173    #[doc = r""]
174    #[doc = r" # Safety"]
175    #[doc = r""]
176    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
177    #[inline(always)]
178    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
179        self.bits = bits;
180        self
181    }
182}
183#[doc = "CLK27M FANOUT Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk27m_fan::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk27m_fan::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
184pub struct CLK27M_FAN_SPEC;
185impl crate::RegisterSpec for CLK27M_FAN_SPEC {
186    type Ux = u32;
187}
188#[doc = "`read()` method returns [`clk27m_fan::R`](R) reader structure"]
189impl crate::Readable for CLK27M_FAN_SPEC {}
190#[doc = "`write(|w| ..)` method takes [`clk27m_fan::W`](W) writer structure"]
191impl crate::Writable for CLK27M_FAN_SPEC {
192    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
193    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
194}
195#[doc = "`reset()` method sets clk27m_fan to value 0"]
196impl crate::Resettable for CLK27M_FAN_SPEC {
197    const RESET_VALUE: Self::Ux = 0;
198}
d1_pac/ccu/clk27m_fan.rs

d1_pac/ccu/
clk27m_fan.rs
