d1_pac/ccu/
ccu_fan.rs

1#[doc = "Register `ccu_fan` reader"]
2pub type R = crate::R<CCU_FAN_SPEC>;
3#[doc = "Register `ccu_fan` writer"]
4pub type W = crate::W<CCU_FAN_SPEC>;
5#[doc = "Field `clk_fanout_sel[0-2]` reader - "]
6pub type CLK_FANOUT_SEL_R = crate::FieldReader<CLK_FANOUT_SEL_A>;
7#[doc = "\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum CLK_FANOUT_SEL_A {
11    #[doc = "0: `0`"]
12    CLK32K = 0,
13    #[doc = "1: `1`"]
14    CLK12M = 1,
15    #[doc = "2: `10`"]
16    CLK16M = 2,
17    #[doc = "3: `11`"]
18    CLK24M = 3,
19    #[doc = "4: `100`"]
20    CLK25M = 4,
21    #[doc = "5: `101`"]
22    CLK27M = 5,
23    #[doc = "6: `110`"]
24    PCLK = 6,
25}
26impl From<CLK_FANOUT_SEL_A> for u8 {
27    #[inline(always)]
28    fn from(variant: CLK_FANOUT_SEL_A) -> Self {
29        variant as _
30    }
31}
32impl crate::FieldSpec for CLK_FANOUT_SEL_A {
33    type Ux = u8;
34}
35impl CLK_FANOUT_SEL_R {
36    #[doc = "Get enumerated values variant"]
37    #[inline(always)]
38    pub const fn variant(&self) -> Option<CLK_FANOUT_SEL_A> {
39        match self.bits {
40            0 => Some(CLK_FANOUT_SEL_A::CLK32K),
41            1 => Some(CLK_FANOUT_SEL_A::CLK12M),
42            2 => Some(CLK_FANOUT_SEL_A::CLK16M),
43            3 => Some(CLK_FANOUT_SEL_A::CLK24M),
44            4 => Some(CLK_FANOUT_SEL_A::CLK25M),
45            5 => Some(CLK_FANOUT_SEL_A::CLK27M),
46            6 => Some(CLK_FANOUT_SEL_A::PCLK),
47            _ => None,
48        }
49    }
50    #[doc = "`0`"]
51    #[inline(always)]
52    pub fn is_clk32k(&self) -> bool {
53        *self == CLK_FANOUT_SEL_A::CLK32K
54    }
55    #[doc = "`1`"]
56    #[inline(always)]
57    pub fn is_clk12m(&self) -> bool {
58        *self == CLK_FANOUT_SEL_A::CLK12M
59    }
60    #[doc = "`10`"]
61    #[inline(always)]
62    pub fn is_clk16m(&self) -> bool {
63        *self == CLK_FANOUT_SEL_A::CLK16M
64    }
65    #[doc = "`11`"]
66    #[inline(always)]
67    pub fn is_clk24m(&self) -> bool {
68        *self == CLK_FANOUT_SEL_A::CLK24M
69    }
70    #[doc = "`100`"]
71    #[inline(always)]
72    pub fn is_clk25m(&self) -> bool {
73        *self == CLK_FANOUT_SEL_A::CLK25M
74    }
75    #[doc = "`101`"]
76    #[inline(always)]
77    pub fn is_clk27m(&self) -> bool {
78        *self == CLK_FANOUT_SEL_A::CLK27M
79    }
80    #[doc = "`110`"]
81    #[inline(always)]
82    pub fn is_pclk(&self) -> bool {
83        *self == CLK_FANOUT_SEL_A::PCLK
84    }
85}
86#[doc = "Field `clk_fanout_sel[0-2]` writer - "]
87pub type CLK_FANOUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3, CLK_FANOUT_SEL_A>;
88impl<'a, REG> CLK_FANOUT_SEL_W<'a, REG>
89where
90    REG: crate::Writable + crate::RegisterSpec,
91    REG::Ux: From<u8>,
92{
93    #[doc = "`0`"]
94    #[inline(always)]
95    pub fn clk32k(self) -> &'a mut crate::W<REG> {
96        self.variant(CLK_FANOUT_SEL_A::CLK32K)
97    }
98    #[doc = "`1`"]
99    #[inline(always)]
100    pub fn clk12m(self) -> &'a mut crate::W<REG> {
101        self.variant(CLK_FANOUT_SEL_A::CLK12M)
102    }
103    #[doc = "`10`"]
104    #[inline(always)]
105    pub fn clk16m(self) -> &'a mut crate::W<REG> {
106        self.variant(CLK_FANOUT_SEL_A::CLK16M)
107    }
108    #[doc = "`11`"]
109    #[inline(always)]
110    pub fn clk24m(self) -> &'a mut crate::W<REG> {
111        self.variant(CLK_FANOUT_SEL_A::CLK24M)
112    }
113    #[doc = "`100`"]
114    #[inline(always)]
115    pub fn clk25m(self) -> &'a mut crate::W<REG> {
116        self.variant(CLK_FANOUT_SEL_A::CLK25M)
117    }
118    #[doc = "`101`"]
119    #[inline(always)]
120    pub fn clk27m(self) -> &'a mut crate::W<REG> {
121        self.variant(CLK_FANOUT_SEL_A::CLK27M)
122    }
123    #[doc = "`110`"]
124    #[inline(always)]
125    pub fn pclk(self) -> &'a mut crate::W<REG> {
126        self.variant(CLK_FANOUT_SEL_A::PCLK)
127    }
128}
129#[doc = "Field `clk_fanout_en[0-2]` reader - Gating for CLK_FANOUT"]
130pub type CLK_FANOUT_EN_R = crate::BitReader<CLK_FANOUT_EN_A>;
131#[doc = "Gating for CLK_FANOUT\n\nValue on reset: 0"]
132#[derive(Clone, Copy, Debug, PartialEq, Eq)]
133pub enum CLK_FANOUT_EN_A {
134    #[doc = "0: `0`"]
135    OFF = 0,
136    #[doc = "1: `1`"]
137    ON = 1,
138}
139impl From<CLK_FANOUT_EN_A> for bool {
140    #[inline(always)]
141    fn from(variant: CLK_FANOUT_EN_A) -> Self {
142        variant as u8 != 0
143    }
144}
145impl CLK_FANOUT_EN_R {
146    #[doc = "Get enumerated values variant"]
147    #[inline(always)]
148    pub const fn variant(&self) -> CLK_FANOUT_EN_A {
149        match self.bits {
150            false => CLK_FANOUT_EN_A::OFF,
151            true => CLK_FANOUT_EN_A::ON,
152        }
153    }
154    #[doc = "`0`"]
155    #[inline(always)]
156    pub fn is_off(&self) -> bool {
157        *self == CLK_FANOUT_EN_A::OFF
158    }
159    #[doc = "`1`"]
160    #[inline(always)]
161    pub fn is_on(&self) -> bool {
162        *self == CLK_FANOUT_EN_A::ON
163    }
164}
165#[doc = "Field `clk_fanout_en[0-2]` writer - Gating for CLK_FANOUT"]
166pub type CLK_FANOUT_EN_W<'a, REG> = crate::BitWriter<'a, REG, CLK_FANOUT_EN_A>;
167impl<'a, REG> CLK_FANOUT_EN_W<'a, REG>
168where
169    REG: crate::Writable + crate::RegisterSpec,
170{
171    #[doc = "`0`"]
172    #[inline(always)]
173    pub fn off(self) -> &'a mut crate::W<REG> {
174        self.variant(CLK_FANOUT_EN_A::OFF)
175    }
176    #[doc = "`1`"]
177    #[inline(always)]
178    pub fn on(self) -> &'a mut crate::W<REG> {
179        self.variant(CLK_FANOUT_EN_A::ON)
180    }
181}
182impl R {
183    #[doc = "\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `clk_fanout0_sel` field"]
184    #[inline(always)]
185    pub fn clk_fanout_sel(&self, n: u8) -> CLK_FANOUT_SEL_R {
186        #[allow(clippy::no_effect)]
187        [(); 3][n as usize];
188        CLK_FANOUT_SEL_R::new(((self.bits >> (n * 3)) & 7) as u8)
189    }
190    #[doc = "Bits 0:2 - clk_fanout0_sel"]
191    #[inline(always)]
192    pub fn clk_fanout0_sel(&self) -> CLK_FANOUT_SEL_R {
193        CLK_FANOUT_SEL_R::new((self.bits & 7) as u8)
194    }
195    #[doc = "Bits 3:5 - clk_fanout1_sel"]
196    #[inline(always)]
197    pub fn clk_fanout1_sel(&self) -> CLK_FANOUT_SEL_R {
198        CLK_FANOUT_SEL_R::new(((self.bits >> 3) & 7) as u8)
199    }
200    #[doc = "Bits 6:8 - clk_fanout2_sel"]
201    #[inline(always)]
202    pub fn clk_fanout2_sel(&self) -> CLK_FANOUT_SEL_R {
203        CLK_FANOUT_SEL_R::new(((self.bits >> 6) & 7) as u8)
204    }
205    #[doc = "Gating for CLK_FANOUT\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `clk_fanout0_en` field"]
206    #[inline(always)]
207    pub fn clk_fanout_en(&self, n: u8) -> CLK_FANOUT_EN_R {
208        #[allow(clippy::no_effect)]
209        [(); 3][n as usize];
210        CLK_FANOUT_EN_R::new(((self.bits >> (n + 21)) & 1) != 0)
211    }
212    #[doc = "Bit 21 - Gating for CLK_FANOUT"]
213    #[inline(always)]
214    pub fn clk_fanout0_en(&self) -> CLK_FANOUT_EN_R {
215        CLK_FANOUT_EN_R::new(((self.bits >> 21) & 1) != 0)
216    }
217    #[doc = "Bit 22 - Gating for CLK_FANOUT"]
218    #[inline(always)]
219    pub fn clk_fanout1_en(&self) -> CLK_FANOUT_EN_R {
220        CLK_FANOUT_EN_R::new(((self.bits >> 22) & 1) != 0)
221    }
222    #[doc = "Bit 23 - Gating for CLK_FANOUT"]
223    #[inline(always)]
224    pub fn clk_fanout2_en(&self) -> CLK_FANOUT_EN_R {
225        CLK_FANOUT_EN_R::new(((self.bits >> 23) & 1) != 0)
226    }
227}
228impl W {
229    #[doc = "\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `clk_fanout0_sel` field"]
230    #[inline(always)]
231    #[must_use]
232    pub fn clk_fanout_sel(&mut self, n: u8) -> CLK_FANOUT_SEL_W<CCU_FAN_SPEC> {
233        #[allow(clippy::no_effect)]
234        [(); 3][n as usize];
235        CLK_FANOUT_SEL_W::new(self, n * 3)
236    }
237    #[doc = "Bits 0:2 - clk_fanout0_sel"]
238    #[inline(always)]
239    #[must_use]
240    pub fn clk_fanout0_sel(&mut self) -> CLK_FANOUT_SEL_W<CCU_FAN_SPEC> {
241        CLK_FANOUT_SEL_W::new(self, 0)
242    }
243    #[doc = "Bits 3:5 - clk_fanout1_sel"]
244    #[inline(always)]
245    #[must_use]
246    pub fn clk_fanout1_sel(&mut self) -> CLK_FANOUT_SEL_W<CCU_FAN_SPEC> {
247        CLK_FANOUT_SEL_W::new(self, 3)
248    }
249    #[doc = "Bits 6:8 - clk_fanout2_sel"]
250    #[inline(always)]
251    #[must_use]
252    pub fn clk_fanout2_sel(&mut self) -> CLK_FANOUT_SEL_W<CCU_FAN_SPEC> {
253        CLK_FANOUT_SEL_W::new(self, 6)
254    }
255    #[doc = "Gating for CLK_FANOUT\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `clk_fanout0_en` field"]
256    #[inline(always)]
257    #[must_use]
258    pub fn clk_fanout_en(&mut self, n: u8) -> CLK_FANOUT_EN_W<CCU_FAN_SPEC> {
259        #[allow(clippy::no_effect)]
260        [(); 3][n as usize];
261        CLK_FANOUT_EN_W::new(self, n + 21)
262    }
263    #[doc = "Bit 21 - Gating for CLK_FANOUT"]
264    #[inline(always)]
265    #[must_use]
266    pub fn clk_fanout0_en(&mut self) -> CLK_FANOUT_EN_W<CCU_FAN_SPEC> {
267        CLK_FANOUT_EN_W::new(self, 21)
268    }
269    #[doc = "Bit 22 - Gating for CLK_FANOUT"]
270    #[inline(always)]
271    #[must_use]
272    pub fn clk_fanout1_en(&mut self) -> CLK_FANOUT_EN_W<CCU_FAN_SPEC> {
273        CLK_FANOUT_EN_W::new(self, 22)
274    }
275    #[doc = "Bit 23 - Gating for CLK_FANOUT"]
276    #[inline(always)]
277    #[must_use]
278    pub fn clk_fanout2_en(&mut self) -> CLK_FANOUT_EN_W<CCU_FAN_SPEC> {
279        CLK_FANOUT_EN_W::new(self, 23)
280    }
281    #[doc = r" Writes raw bits to the register."]
282    #[doc = r""]
283    #[doc = r" # Safety"]
284    #[doc = r""]
285    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
286    #[inline(always)]
287    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
288        self.bits = bits;
289        self
290    }
291}
292#[doc = "CCU FANOUT Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccu_fan::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccu_fan::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
293pub struct CCU_FAN_SPEC;
294impl crate::RegisterSpec for CCU_FAN_SPEC {
295    type Ux = u32;
296}
297#[doc = "`read()` method returns [`ccu_fan::R`](R) reader structure"]
298impl crate::Readable for CCU_FAN_SPEC {}
299#[doc = "`write(|w| ..)` method takes [`ccu_fan::W`](W) writer structure"]
300impl crate::Writable for CCU_FAN_SPEC {
301    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
302    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
303}
304#[doc = "`reset()` method sets ccu_fan to value 0"]
305impl crate::Resettable for CCU_FAN_SPEC {
306    const RESET_VALUE: Self::Ux = 0;
307}
d1_pac/ccu/ccu_fan.rs

d1_pac/ccu/
ccu_fan.rs
