d1_pac/ccu/
avs_clk.rs

1#[doc = "Register `avs_clk` reader"]
2pub type R = crate::R<AVS_CLK_SPEC>;
3#[doc = "Register `avs_clk` writer"]
4pub type W = crate::W<AVS_CLK_SPEC>;
5#[doc = "Field `clk_gating` reader - Gating Clock"]
6pub type CLK_GATING_R = crate::BitReader<CLK_GATING_A>;
7#[doc = "Gating Clock\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum CLK_GATING_A {
10    #[doc = "0: `0`"]
11    OFF = 0,
12    #[doc = "1: `1`"]
13    ON = 1,
14}
15impl From<CLK_GATING_A> for bool {
16    #[inline(always)]
17    fn from(variant: CLK_GATING_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl CLK_GATING_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> CLK_GATING_A {
25        match self.bits {
26            false => CLK_GATING_A::OFF,
27            true => CLK_GATING_A::ON,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_off(&self) -> bool {
33        *self == CLK_GATING_A::OFF
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_on(&self) -> bool {
38        *self == CLK_GATING_A::ON
39    }
40}
41#[doc = "Field `clk_gating` writer - Gating Clock"]
42pub type CLK_GATING_W<'a, REG> = crate::BitWriter<'a, REG, CLK_GATING_A>;
43impl<'a, REG> CLK_GATING_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn off(self) -> &'a mut crate::W<REG> {
50        self.variant(CLK_GATING_A::OFF)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn on(self) -> &'a mut crate::W<REG> {
55        self.variant(CLK_GATING_A::ON)
56    }
57}
58impl R {
59    #[doc = "Bit 31 - Gating Clock"]
60    #[inline(always)]
61    pub fn clk_gating(&self) -> CLK_GATING_R {
62        CLK_GATING_R::new(((self.bits >> 31) & 1) != 0)
63    }
64}
65impl W {
66    #[doc = "Bit 31 - Gating Clock"]
67    #[inline(always)]
68    #[must_use]
69    pub fn clk_gating(&mut self) -> CLK_GATING_W<AVS_CLK_SPEC> {
70        CLK_GATING_W::new(self, 31)
71    }
72    #[doc = r" Writes raw bits to the register."]
73    #[doc = r""]
74    #[doc = r" # Safety"]
75    #[doc = r""]
76    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
77    #[inline(always)]
78    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
79        self.bits = bits;
80        self
81    }
82}
83#[doc = "AVS Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`avs_clk::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`avs_clk::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
84pub struct AVS_CLK_SPEC;
85impl crate::RegisterSpec for AVS_CLK_SPEC {
86    type Ux = u32;
87}
88#[doc = "`read()` method returns [`avs_clk::R`](R) reader structure"]
89impl crate::Readable for AVS_CLK_SPEC {}
90#[doc = "`write(|w| ..)` method takes [`avs_clk::W`](W) writer structure"]
91impl crate::Writable for AVS_CLK_SPEC {
92    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
93    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
94}
95#[doc = "`reset()` method sets avs_clk to value 0"]
96impl crate::Resettable for AVS_CLK_SPEC {
97    const RESET_VALUE: Self::Ux = 0;
98}
d1_pac/ccu/avs_clk.rs

d1_pac/ccu/
avs_clk.rs
