d1_pac/audio_codec/
adc_vol_ctrl1.rs

1#[doc = "Register `adc_vol_ctrl1` reader"]
2pub type R = crate::R<ADC_VOL_CTRL1_SPEC>;
3#[doc = "Register `adc_vol_ctrl1` writer"]
4pub type W = crate::W<ADC_VOL_CTRL1_SPEC>;
5#[doc = "Field `adc_vol[1-3]` reader - ADC\\[i\\] channel volume (-119.25 dB To 71.25 dB, 0.75 dB/Step)"]
6pub type ADC_VOL_R = crate::FieldReader<ADC_VOL_A>;
7#[doc = "ADC\\[i\\] channel volume (-119.25 dB To 71.25 dB, 0.75 dB/Step)\n\nValue on reset: 160"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum ADC_VOL_A {
11    #[doc = "0: Mute"]
12    M_UTE = 0,
13    #[doc = "1: -119.25 dB ..."]
14    N_119_25DB = 1,
15    #[doc = "160: 0 dB"]
16    _0DB = 160,
17    #[doc = "255: 71.25 dB"]
18    _71_25DB = 255,
19}
20impl From<ADC_VOL_A> for u8 {
21    #[inline(always)]
22    fn from(variant: ADC_VOL_A) -> Self {
23        variant as _
24    }
25}
26impl crate::FieldSpec for ADC_VOL_A {
27    type Ux = u8;
28}
29impl ADC_VOL_R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> Option<ADC_VOL_A> {
33        match self.bits {
34            0 => Some(ADC_VOL_A::M_UTE),
35            1 => Some(ADC_VOL_A::N_119_25DB),
36            160 => Some(ADC_VOL_A::_0DB),
37            255 => Some(ADC_VOL_A::_71_25DB),
38            _ => None,
39        }
40    }
41    #[doc = "Mute"]
42    #[inline(always)]
43    pub fn is_m_ute(&self) -> bool {
44        *self == ADC_VOL_A::M_UTE
45    }
46    #[doc = "-119.25 dB ..."]
47    #[inline(always)]
48    pub fn is_n_119_25db(&self) -> bool {
49        *self == ADC_VOL_A::N_119_25DB
50    }
51    #[doc = "0 dB"]
52    #[inline(always)]
53    pub fn is_0db(&self) -> bool {
54        *self == ADC_VOL_A::_0DB
55    }
56    #[doc = "71.25 dB"]
57    #[inline(always)]
58    pub fn is_71_25db(&self) -> bool {
59        *self == ADC_VOL_A::_71_25DB
60    }
61}
62#[doc = "Field `adc_vol[1-3]` writer - ADC\\[i\\] channel volume (-119.25 dB To 71.25 dB, 0.75 dB/Step)"]
63pub type ADC_VOL_W<'a, REG> = crate::FieldWriter<'a, REG, 8, ADC_VOL_A>;
64impl<'a, REG> ADC_VOL_W<'a, REG>
65where
66    REG: crate::Writable + crate::RegisterSpec,
67    REG::Ux: From<u8>,
68{
69    #[doc = "Mute"]
70    #[inline(always)]
71    pub fn m_ute(self) -> &'a mut crate::W<REG> {
72        self.variant(ADC_VOL_A::M_UTE)
73    }
74    #[doc = "-119.25 dB ..."]
75    #[inline(always)]
76    pub fn n_119_25db(self) -> &'a mut crate::W<REG> {
77        self.variant(ADC_VOL_A::N_119_25DB)
78    }
79    #[doc = "0 dB"]
80    #[inline(always)]
81    pub fn _0db(self) -> &'a mut crate::W<REG> {
82        self.variant(ADC_VOL_A::_0DB)
83    }
84    #[doc = "71.25 dB"]
85    #[inline(always)]
86    pub fn _71_25db(self) -> &'a mut crate::W<REG> {
87        self.variant(ADC_VOL_A::_71_25DB)
88    }
89}
90impl R {
91    #[doc = "ADC\\[i\\] channel volume (-119.25 dB To 71.25 dB, 0.75 dB/Step)\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `adc1_vol` field"]
92    #[inline(always)]
93    pub fn adc_vol(&self, n: u8) -> ADC_VOL_R {
94        #[allow(clippy::no_effect)]
95        [(); 3][n as usize];
96        ADC_VOL_R::new(((self.bits >> (n * 8)) & 0xff) as u8)
97    }
98    #[doc = "Bits 0:7 - ADC\\[i\\] channel volume (-119.25 dB To 71.25 dB, 0.75 dB/Step)"]
99    #[inline(always)]
100    pub fn adc1_vol(&self) -> ADC_VOL_R {
101        ADC_VOL_R::new((self.bits & 0xff) as u8)
102    }
103    #[doc = "Bits 8:15 - ADC\\[i\\] channel volume (-119.25 dB To 71.25 dB, 0.75 dB/Step)"]
104    #[inline(always)]
105    pub fn adc2_vol(&self) -> ADC_VOL_R {
106        ADC_VOL_R::new(((self.bits >> 8) & 0xff) as u8)
107    }
108    #[doc = "Bits 16:23 - ADC\\[i\\] channel volume (-119.25 dB To 71.25 dB, 0.75 dB/Step)"]
109    #[inline(always)]
110    pub fn adc3_vol(&self) -> ADC_VOL_R {
111        ADC_VOL_R::new(((self.bits >> 16) & 0xff) as u8)
112    }
113}
114impl W {
115    #[doc = "ADC\\[i\\] channel volume (-119.25 dB To 71.25 dB, 0.75 dB/Step)\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `adc1_vol` field"]
116    #[inline(always)]
117    #[must_use]
118    pub fn adc_vol(&mut self, n: u8) -> ADC_VOL_W<ADC_VOL_CTRL1_SPEC> {
119        #[allow(clippy::no_effect)]
120        [(); 3][n as usize];
121        ADC_VOL_W::new(self, n * 8)
122    }
123    #[doc = "Bits 0:7 - ADC\\[i\\] channel volume (-119.25 dB To 71.25 dB, 0.75 dB/Step)"]
124    #[inline(always)]
125    #[must_use]
126    pub fn adc1_vol(&mut self) -> ADC_VOL_W<ADC_VOL_CTRL1_SPEC> {
127        ADC_VOL_W::new(self, 0)
128    }
129    #[doc = "Bits 8:15 - ADC\\[i\\] channel volume (-119.25 dB To 71.25 dB, 0.75 dB/Step)"]
130    #[inline(always)]
131    #[must_use]
132    pub fn adc2_vol(&mut self) -> ADC_VOL_W<ADC_VOL_CTRL1_SPEC> {
133        ADC_VOL_W::new(self, 8)
134    }
135    #[doc = "Bits 16:23 - ADC\\[i\\] channel volume (-119.25 dB To 71.25 dB, 0.75 dB/Step)"]
136    #[inline(always)]
137    #[must_use]
138    pub fn adc3_vol(&mut self) -> ADC_VOL_W<ADC_VOL_CTRL1_SPEC> {
139        ADC_VOL_W::new(self, 16)
140    }
141    #[doc = r" Writes raw bits to the register."]
142    #[doc = r""]
143    #[doc = r" # Safety"]
144    #[doc = r""]
145    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
146    #[inline(always)]
147    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
148        self.bits = bits;
149        self
150    }
151}
152#[doc = "ADC Volume Control1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc_vol_ctrl1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc_vol_ctrl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
153pub struct ADC_VOL_CTRL1_SPEC;
154impl crate::RegisterSpec for ADC_VOL_CTRL1_SPEC {
155    type Ux = u32;
156}
157#[doc = "`read()` method returns [`adc_vol_ctrl1::R`](R) reader structure"]
158impl crate::Readable for ADC_VOL_CTRL1_SPEC {}
159#[doc = "`write(|w| ..)` method takes [`adc_vol_ctrl1::W`](W) writer structure"]
160impl crate::Writable for ADC_VOL_CTRL1_SPEC {
161    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
162    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
163}
164#[doc = "`reset()` method sets adc_vol_ctrl1 to value 0xa0a0_a0a0"]
165impl crate::Resettable for ADC_VOL_CTRL1_SPEC {
166    const RESET_VALUE: Self::Ux = 0xa0a0_a0a0;
167}
d1_pac/audio_codec/adc_vol_ctrl1.rs

d1_pac/audio_codec/
adc_vol_ctrl1.rs
