d1_pac/audio_codec/
adc_dig_ctrl.rs

1#[doc = "Register `adc_dig_ctrl` reader"]
2pub type R = crate::R<ADC_DIG_CTRL_SPEC>;
3#[doc = "Register `adc_dig_ctrl` writer"]
4pub type W = crate::W<ADC_DIG_CTRL_SPEC>;
5#[doc = "Field `adc_channel_en` reader - Bit 3: ADC4 enabled\n\nBit 2: ADC3 enabled\n\nBit 1: ADC2 enabled\n\nBit 0: ADC1 enabled"]
6pub type ADC_CHANNEL_EN_R = crate::FieldReader;
7#[doc = "Field `adc_channel_en` writer - Bit 3: ADC4 enabled\n\nBit 2: ADC3 enabled\n\nBit 1: ADC2 enabled\n\nBit 0: ADC1 enabled"]
8pub type ADC_CHANNEL_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9#[doc = "Field `adc1_2_vol_en` reader - ADC1/2 Volume Control Enable"]
10pub type ADC1_2_VOL_EN_R = crate::BitReader<ADC1_2_VOL_EN_A>;
11#[doc = "ADC1/2 Volume Control Enable\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13pub enum ADC1_2_VOL_EN_A {
14    #[doc = "0: Disabled"]
15    DISABLED = 0,
16    #[doc = "1: Enabled"]
17    ENABLED = 1,
18}
19impl From<ADC1_2_VOL_EN_A> for bool {
20    #[inline(always)]
21    fn from(variant: ADC1_2_VOL_EN_A) -> Self {
22        variant as u8 != 0
23    }
24}
25impl ADC1_2_VOL_EN_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> ADC1_2_VOL_EN_A {
29        match self.bits {
30            false => ADC1_2_VOL_EN_A::DISABLED,
31            true => ADC1_2_VOL_EN_A::ENABLED,
32        }
33    }
34    #[doc = "Disabled"]
35    #[inline(always)]
36    pub fn is_disabled(&self) -> bool {
37        *self == ADC1_2_VOL_EN_A::DISABLED
38    }
39    #[doc = "Enabled"]
40    #[inline(always)]
41    pub fn is_enabled(&self) -> bool {
42        *self == ADC1_2_VOL_EN_A::ENABLED
43    }
44}
45#[doc = "Field `adc1_2_vol_en` writer - ADC1/2 Volume Control Enable"]
46pub type ADC1_2_VOL_EN_W<'a, REG> = crate::BitWriter<'a, REG, ADC1_2_VOL_EN_A>;
47impl<'a, REG> ADC1_2_VOL_EN_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "Disabled"]
52    #[inline(always)]
53    pub fn disabled(self) -> &'a mut crate::W<REG> {
54        self.variant(ADC1_2_VOL_EN_A::DISABLED)
55    }
56    #[doc = "Enabled"]
57    #[inline(always)]
58    pub fn enabled(self) -> &'a mut crate::W<REG> {
59        self.variant(ADC1_2_VOL_EN_A::ENABLED)
60    }
61}
62#[doc = "Field `adc3_vol_en` reader - ADC3 Volume Control Enable"]
63pub type ADC3_VOL_EN_R = crate::BitReader<ADC3_VOL_EN_A>;
64#[doc = "ADC3 Volume Control Enable\n\nValue on reset: 0"]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum ADC3_VOL_EN_A {
67    #[doc = "0: Disabled"]
68    DISABLED = 0,
69    #[doc = "1: Enabled"]
70    ENABLED = 1,
71}
72impl From<ADC3_VOL_EN_A> for bool {
73    #[inline(always)]
74    fn from(variant: ADC3_VOL_EN_A) -> Self {
75        variant as u8 != 0
76    }
77}
78impl ADC3_VOL_EN_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub const fn variant(&self) -> ADC3_VOL_EN_A {
82        match self.bits {
83            false => ADC3_VOL_EN_A::DISABLED,
84            true => ADC3_VOL_EN_A::ENABLED,
85        }
86    }
87    #[doc = "Disabled"]
88    #[inline(always)]
89    pub fn is_disabled(&self) -> bool {
90        *self == ADC3_VOL_EN_A::DISABLED
91    }
92    #[doc = "Enabled"]
93    #[inline(always)]
94    pub fn is_enabled(&self) -> bool {
95        *self == ADC3_VOL_EN_A::ENABLED
96    }
97}
98#[doc = "Field `adc3_vol_en` writer - ADC3 Volume Control Enable"]
99pub type ADC3_VOL_EN_W<'a, REG> = crate::BitWriter<'a, REG, ADC3_VOL_EN_A>;
100impl<'a, REG> ADC3_VOL_EN_W<'a, REG>
101where
102    REG: crate::Writable + crate::RegisterSpec,
103{
104    #[doc = "Disabled"]
105    #[inline(always)]
106    pub fn disabled(self) -> &'a mut crate::W<REG> {
107        self.variant(ADC3_VOL_EN_A::DISABLED)
108    }
109    #[doc = "Enabled"]
110    #[inline(always)]
111    pub fn enabled(self) -> &'a mut crate::W<REG> {
112        self.variant(ADC3_VOL_EN_A::ENABLED)
113    }
114}
115impl R {
116    #[doc = "Bits 0:2 - Bit 3: ADC4 enabled\n\nBit 2: ADC3 enabled\n\nBit 1: ADC2 enabled\n\nBit 0: ADC1 enabled"]
117    #[inline(always)]
118    pub fn adc_channel_en(&self) -> ADC_CHANNEL_EN_R {
119        ADC_CHANNEL_EN_R::new((self.bits & 7) as u8)
120    }
121    #[doc = "Bit 16 - ADC1/2 Volume Control Enable"]
122    #[inline(always)]
123    pub fn adc1_2_vol_en(&self) -> ADC1_2_VOL_EN_R {
124        ADC1_2_VOL_EN_R::new(((self.bits >> 16) & 1) != 0)
125    }
126    #[doc = "Bit 17 - ADC3 Volume Control Enable"]
127    #[inline(always)]
128    pub fn adc3_vol_en(&self) -> ADC3_VOL_EN_R {
129        ADC3_VOL_EN_R::new(((self.bits >> 17) & 1) != 0)
130    }
131}
132impl W {
133    #[doc = "Bits 0:2 - Bit 3: ADC4 enabled\n\nBit 2: ADC3 enabled\n\nBit 1: ADC2 enabled\n\nBit 0: ADC1 enabled"]
134    #[inline(always)]
135    #[must_use]
136    pub fn adc_channel_en(&mut self) -> ADC_CHANNEL_EN_W<ADC_DIG_CTRL_SPEC> {
137        ADC_CHANNEL_EN_W::new(self, 0)
138    }
139    #[doc = "Bit 16 - ADC1/2 Volume Control Enable"]
140    #[inline(always)]
141    #[must_use]
142    pub fn adc1_2_vol_en(&mut self) -> ADC1_2_VOL_EN_W<ADC_DIG_CTRL_SPEC> {
143        ADC1_2_VOL_EN_W::new(self, 16)
144    }
145    #[doc = "Bit 17 - ADC3 Volume Control Enable"]
146    #[inline(always)]
147    #[must_use]
148    pub fn adc3_vol_en(&mut self) -> ADC3_VOL_EN_W<ADC_DIG_CTRL_SPEC> {
149        ADC3_VOL_EN_W::new(self, 17)
150    }
151    #[doc = r" Writes raw bits to the register."]
152    #[doc = r""]
153    #[doc = r" # Safety"]
154    #[doc = r""]
155    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
156    #[inline(always)]
157    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
158        self.bits = bits;
159        self
160    }
161}
162#[doc = "ADC Digtial Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`adc_dig_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`adc_dig_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
163pub struct ADC_DIG_CTRL_SPEC;
164impl crate::RegisterSpec for ADC_DIG_CTRL_SPEC {
165    type Ux = u32;
166}
167#[doc = "`read()` method returns [`adc_dig_ctrl::R`](R) reader structure"]
168impl crate::Readable for ADC_DIG_CTRL_SPEC {}
169#[doc = "`write(|w| ..)` method takes [`adc_dig_ctrl::W`](W) writer structure"]
170impl crate::Writable for ADC_DIG_CTRL_SPEC {
171    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
172    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
173}
174#[doc = "`reset()` method sets adc_dig_ctrl to value 0"]
175impl crate::Resettable for ADC_DIG_CTRL_SPEC {
176    const RESET_VALUE: Self::Ux = 0;
177}
d1_pac/audio_codec/adc_dig_ctrl.rs

d1_pac/audio_codec/
adc_dig_ctrl.rs
