d1_pac/audio_codec/
ac_dac_fifoc.rs

1#[doc = "Register `ac_dac_fifoc` reader"]
2pub type R = crate::R<AC_DAC_FIFOC_SPEC>;
3#[doc = "Register `ac_dac_fifoc` writer"]
4pub type W = crate::W<AC_DAC_FIFOC_SPEC>;
5#[doc = "Field `fifo_flush` reader - DAC FIFO Flush"]
6pub type FIFO_FLUSH_R = crate::BitReader<FIFO_FLUSH_A>;
7#[doc = "DAC FIFO Flush\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum FIFO_FLUSH_A {
10    #[doc = "0: `0`"]
11    SELF_CLEAR = 0,
12    #[doc = "1: `1`"]
13    FLUSH = 1,
14}
15impl From<FIFO_FLUSH_A> for bool {
16    #[inline(always)]
17    fn from(variant: FIFO_FLUSH_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl FIFO_FLUSH_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> FIFO_FLUSH_A {
25        match self.bits {
26            false => FIFO_FLUSH_A::SELF_CLEAR,
27            true => FIFO_FLUSH_A::FLUSH,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_self_clear(&self) -> bool {
33        *self == FIFO_FLUSH_A::SELF_CLEAR
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_flush(&self) -> bool {
38        *self == FIFO_FLUSH_A::FLUSH
39    }
40}
41#[doc = "Field `fifo_flush` writer - DAC FIFO Flush"]
42pub type FIFO_FLUSH_W<'a, REG> = crate::BitWriter<'a, REG, FIFO_FLUSH_A>;
43impl<'a, REG> FIFO_FLUSH_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn self_clear(self) -> &'a mut crate::W<REG> {
50        self.variant(FIFO_FLUSH_A::SELF_CLEAR)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn flush(self) -> &'a mut crate::W<REG> {
55        self.variant(FIFO_FLUSH_A::FLUSH)
56    }
57}
58#[doc = "Field `fifo_overrun_irq_en` reader - DAC FIFO Overrun IRQ Enable"]
59pub type FIFO_OVERRUN_IRQ_EN_R = crate::BitReader<FIFO_OVERRUN_IRQ_EN_A>;
60#[doc = "DAC FIFO Overrun IRQ Enable\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum FIFO_OVERRUN_IRQ_EN_A {
63    #[doc = "0: `0`"]
64    DISABLE = 0,
65    #[doc = "1: `1`"]
66    ENABLE = 1,
67}
68impl From<FIFO_OVERRUN_IRQ_EN_A> for bool {
69    #[inline(always)]
70    fn from(variant: FIFO_OVERRUN_IRQ_EN_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl FIFO_OVERRUN_IRQ_EN_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> FIFO_OVERRUN_IRQ_EN_A {
78        match self.bits {
79            false => FIFO_OVERRUN_IRQ_EN_A::DISABLE,
80            true => FIFO_OVERRUN_IRQ_EN_A::ENABLE,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_disable(&self) -> bool {
86        *self == FIFO_OVERRUN_IRQ_EN_A::DISABLE
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_enable(&self) -> bool {
91        *self == FIFO_OVERRUN_IRQ_EN_A::ENABLE
92    }
93}
94#[doc = "Field `fifo_overrun_irq_en` writer - DAC FIFO Overrun IRQ Enable"]
95pub type FIFO_OVERRUN_IRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, FIFO_OVERRUN_IRQ_EN_A>;
96impl<'a, REG> FIFO_OVERRUN_IRQ_EN_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn disable(self) -> &'a mut crate::W<REG> {
103        self.variant(FIFO_OVERRUN_IRQ_EN_A::DISABLE)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn enable(self) -> &'a mut crate::W<REG> {
108        self.variant(FIFO_OVERRUN_IRQ_EN_A::ENABLE)
109    }
110}
111#[doc = "Field `fifo_underrun_irq_en` reader - DAC FIFO Underrun IRQ Enable"]
112pub type FIFO_UNDERRUN_IRQ_EN_R = crate::BitReader<FIFO_UNDERRUN_IRQ_EN_A>;
113#[doc = "DAC FIFO Underrun IRQ Enable\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum FIFO_UNDERRUN_IRQ_EN_A {
116    #[doc = "0: `0`"]
117    DISABLE = 0,
118    #[doc = "1: `1`"]
119    ENABLE = 1,
120}
121impl From<FIFO_UNDERRUN_IRQ_EN_A> for bool {
122    #[inline(always)]
123    fn from(variant: FIFO_UNDERRUN_IRQ_EN_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl FIFO_UNDERRUN_IRQ_EN_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> FIFO_UNDERRUN_IRQ_EN_A {
131        match self.bits {
132            false => FIFO_UNDERRUN_IRQ_EN_A::DISABLE,
133            true => FIFO_UNDERRUN_IRQ_EN_A::ENABLE,
134        }
135    }
136    #[doc = "`0`"]
137    #[inline(always)]
138    pub fn is_disable(&self) -> bool {
139        *self == FIFO_UNDERRUN_IRQ_EN_A::DISABLE
140    }
141    #[doc = "`1`"]
142    #[inline(always)]
143    pub fn is_enable(&self) -> bool {
144        *self == FIFO_UNDERRUN_IRQ_EN_A::ENABLE
145    }
146}
147#[doc = "Field `fifo_underrun_irq_en` writer - DAC FIFO Underrun IRQ Enable"]
148pub type FIFO_UNDERRUN_IRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, FIFO_UNDERRUN_IRQ_EN_A>;
149impl<'a, REG> FIFO_UNDERRUN_IRQ_EN_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "`0`"]
154    #[inline(always)]
155    pub fn disable(self) -> &'a mut crate::W<REG> {
156        self.variant(FIFO_UNDERRUN_IRQ_EN_A::DISABLE)
157    }
158    #[doc = "`1`"]
159    #[inline(always)]
160    pub fn enable(self) -> &'a mut crate::W<REG> {
161        self.variant(FIFO_UNDERRUN_IRQ_EN_A::ENABLE)
162    }
163}
164#[doc = "Field `dac_irq_en` reader - DAC FIFO Empty IRQ Enable"]
165pub type DAC_IRQ_EN_R = crate::BitReader<DAC_IRQ_EN_A>;
166#[doc = "DAC FIFO Empty IRQ Enable\n\nValue on reset: 0"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum DAC_IRQ_EN_A {
169    #[doc = "0: `0`"]
170    DISABLE = 0,
171    #[doc = "1: `1`"]
172    ENABLE = 1,
173}
174impl From<DAC_IRQ_EN_A> for bool {
175    #[inline(always)]
176    fn from(variant: DAC_IRQ_EN_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl DAC_IRQ_EN_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> DAC_IRQ_EN_A {
184        match self.bits {
185            false => DAC_IRQ_EN_A::DISABLE,
186            true => DAC_IRQ_EN_A::ENABLE,
187        }
188    }
189    #[doc = "`0`"]
190    #[inline(always)]
191    pub fn is_disable(&self) -> bool {
192        *self == DAC_IRQ_EN_A::DISABLE
193    }
194    #[doc = "`1`"]
195    #[inline(always)]
196    pub fn is_enable(&self) -> bool {
197        *self == DAC_IRQ_EN_A::ENABLE
198    }
199}
200#[doc = "Field `dac_irq_en` writer - DAC FIFO Empty IRQ Enable"]
201pub type DAC_IRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, DAC_IRQ_EN_A>;
202impl<'a, REG> DAC_IRQ_EN_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "`0`"]
207    #[inline(always)]
208    pub fn disable(self) -> &'a mut crate::W<REG> {
209        self.variant(DAC_IRQ_EN_A::DISABLE)
210    }
211    #[doc = "`1`"]
212    #[inline(always)]
213    pub fn enable(self) -> &'a mut crate::W<REG> {
214        self.variant(DAC_IRQ_EN_A::ENABLE)
215    }
216}
217#[doc = "Field `dac_drq_en` reader - DAC FIFO Empty DRQ Enable"]
218pub type DAC_DRQ_EN_R = crate::BitReader<DAC_DRQ_EN_A>;
219#[doc = "DAC FIFO Empty DRQ Enable\n\nValue on reset: 0"]
220#[derive(Clone, Copy, Debug, PartialEq, Eq)]
221pub enum DAC_DRQ_EN_A {
222    #[doc = "0: `0`"]
223    DISABLE = 0,
224    #[doc = "1: `1`"]
225    ENABLE = 1,
226}
227impl From<DAC_DRQ_EN_A> for bool {
228    #[inline(always)]
229    fn from(variant: DAC_DRQ_EN_A) -> Self {
230        variant as u8 != 0
231    }
232}
233impl DAC_DRQ_EN_R {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> DAC_DRQ_EN_A {
237        match self.bits {
238            false => DAC_DRQ_EN_A::DISABLE,
239            true => DAC_DRQ_EN_A::ENABLE,
240        }
241    }
242    #[doc = "`0`"]
243    #[inline(always)]
244    pub fn is_disable(&self) -> bool {
245        *self == DAC_DRQ_EN_A::DISABLE
246    }
247    #[doc = "`1`"]
248    #[inline(always)]
249    pub fn is_enable(&self) -> bool {
250        *self == DAC_DRQ_EN_A::ENABLE
251    }
252}
253#[doc = "Field `dac_drq_en` writer - DAC FIFO Empty DRQ Enable"]
254pub type DAC_DRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, DAC_DRQ_EN_A>;
255impl<'a, REG> DAC_DRQ_EN_W<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258{
259    #[doc = "`0`"]
260    #[inline(always)]
261    pub fn disable(self) -> &'a mut crate::W<REG> {
262        self.variant(DAC_DRQ_EN_A::DISABLE)
263    }
264    #[doc = "`1`"]
265    #[inline(always)]
266    pub fn enable(self) -> &'a mut crate::W<REG> {
267        self.variant(DAC_DRQ_EN_A::ENABLE)
268    }
269}
270#[doc = "Field `tx_sample_bits` reader - Transmitting Audio Sample Resolution"]
271pub type TX_SAMPLE_BITS_R = crate::BitReader<TX_SAMPLE_BITS_A>;
272#[doc = "Transmitting Audio Sample Resolution\n\nValue on reset: 0"]
273#[derive(Clone, Copy, Debug, PartialEq, Eq)]
274pub enum TX_SAMPLE_BITS_A {
275    #[doc = "0: `0`"]
276    BITS_16 = 0,
277    #[doc = "1: `1`"]
278    BITS_20 = 1,
279}
280impl From<TX_SAMPLE_BITS_A> for bool {
281    #[inline(always)]
282    fn from(variant: TX_SAMPLE_BITS_A) -> Self {
283        variant as u8 != 0
284    }
285}
286impl TX_SAMPLE_BITS_R {
287    #[doc = "Get enumerated values variant"]
288    #[inline(always)]
289    pub const fn variant(&self) -> TX_SAMPLE_BITS_A {
290        match self.bits {
291            false => TX_SAMPLE_BITS_A::BITS_16,
292            true => TX_SAMPLE_BITS_A::BITS_20,
293        }
294    }
295    #[doc = "`0`"]
296    #[inline(always)]
297    pub fn is_bits_16(&self) -> bool {
298        *self == TX_SAMPLE_BITS_A::BITS_16
299    }
300    #[doc = "`1`"]
301    #[inline(always)]
302    pub fn is_bits_20(&self) -> bool {
303        *self == TX_SAMPLE_BITS_A::BITS_20
304    }
305}
306#[doc = "Field `tx_sample_bits` writer - Transmitting Audio Sample Resolution"]
307pub type TX_SAMPLE_BITS_W<'a, REG> = crate::BitWriter<'a, REG, TX_SAMPLE_BITS_A>;
308impl<'a, REG> TX_SAMPLE_BITS_W<'a, REG>
309where
310    REG: crate::Writable + crate::RegisterSpec,
311{
312    #[doc = "`0`"]
313    #[inline(always)]
314    pub fn bits_16(self) -> &'a mut crate::W<REG> {
315        self.variant(TX_SAMPLE_BITS_A::BITS_16)
316    }
317    #[doc = "`1`"]
318    #[inline(always)]
319    pub fn bits_20(self) -> &'a mut crate::W<REG> {
320        self.variant(TX_SAMPLE_BITS_A::BITS_20)
321    }
322}
323#[doc = "Field `dac_mono_en` reader - DAC Mono Enable"]
324pub type DAC_MONO_EN_R = crate::BitReader<DAC_MONO_EN_A>;
325#[doc = "DAC Mono Enable\n\nValue on reset: 0"]
326#[derive(Clone, Copy, Debug, PartialEq, Eq)]
327pub enum DAC_MONO_EN_A {
328    #[doc = "0: `0`"]
329    STEREO = 0,
330    #[doc = "1: `1`"]
331    MONO = 1,
332}
333impl From<DAC_MONO_EN_A> for bool {
334    #[inline(always)]
335    fn from(variant: DAC_MONO_EN_A) -> Self {
336        variant as u8 != 0
337    }
338}
339impl DAC_MONO_EN_R {
340    #[doc = "Get enumerated values variant"]
341    #[inline(always)]
342    pub const fn variant(&self) -> DAC_MONO_EN_A {
343        match self.bits {
344            false => DAC_MONO_EN_A::STEREO,
345            true => DAC_MONO_EN_A::MONO,
346        }
347    }
348    #[doc = "`0`"]
349    #[inline(always)]
350    pub fn is_stereo(&self) -> bool {
351        *self == DAC_MONO_EN_A::STEREO
352    }
353    #[doc = "`1`"]
354    #[inline(always)]
355    pub fn is_mono(&self) -> bool {
356        *self == DAC_MONO_EN_A::MONO
357    }
358}
359#[doc = "Field `dac_mono_en` writer - DAC Mono Enable"]
360pub type DAC_MONO_EN_W<'a, REG> = crate::BitWriter<'a, REG, DAC_MONO_EN_A>;
361impl<'a, REG> DAC_MONO_EN_W<'a, REG>
362where
363    REG: crate::Writable + crate::RegisterSpec,
364{
365    #[doc = "`0`"]
366    #[inline(always)]
367    pub fn stereo(self) -> &'a mut crate::W<REG> {
368        self.variant(DAC_MONO_EN_A::STEREO)
369    }
370    #[doc = "`1`"]
371    #[inline(always)]
372    pub fn mono(self) -> &'a mut crate::W<REG> {
373        self.variant(DAC_MONO_EN_A::MONO)
374    }
375}
376#[doc = "Field `dac_drq_clr_cnt` reader - DAC DRQ clear count"]
377pub type DAC_DRQ_CLR_CNT_R = crate::FieldReader<DAC_DRQ_CLR_CNT_A>;
378#[doc = "DAC DRQ clear count\n\nValue on reset: 0"]
379#[derive(Clone, Copy, Debug, PartialEq, Eq)]
380#[repr(u8)]
381pub enum DAC_DRQ_CLR_CNT_A {
382    #[doc = "0: `0`"]
383    WLEVEL = 0,
384    #[doc = "1: `1`"]
385    N4 = 1,
386    #[doc = "2: `10`"]
387    N8 = 2,
388    #[doc = "3: `11`"]
389    N16 = 3,
390}
391impl From<DAC_DRQ_CLR_CNT_A> for u8 {
392    #[inline(always)]
393    fn from(variant: DAC_DRQ_CLR_CNT_A) -> Self {
394        variant as _
395    }
396}
397impl crate::FieldSpec for DAC_DRQ_CLR_CNT_A {
398    type Ux = u8;
399}
400impl DAC_DRQ_CLR_CNT_R {
401    #[doc = "Get enumerated values variant"]
402    #[inline(always)]
403    pub const fn variant(&self) -> Option<DAC_DRQ_CLR_CNT_A> {
404        match self.bits {
405            0 => Some(DAC_DRQ_CLR_CNT_A::WLEVEL),
406            1 => Some(DAC_DRQ_CLR_CNT_A::N4),
407            2 => Some(DAC_DRQ_CLR_CNT_A::N8),
408            3 => Some(DAC_DRQ_CLR_CNT_A::N16),
409            _ => None,
410        }
411    }
412    #[doc = "`0`"]
413    #[inline(always)]
414    pub fn is_wlevel(&self) -> bool {
415        *self == DAC_DRQ_CLR_CNT_A::WLEVEL
416    }
417    #[doc = "`1`"]
418    #[inline(always)]
419    pub fn is_n4(&self) -> bool {
420        *self == DAC_DRQ_CLR_CNT_A::N4
421    }
422    #[doc = "`10`"]
423    #[inline(always)]
424    pub fn is_n8(&self) -> bool {
425        *self == DAC_DRQ_CLR_CNT_A::N8
426    }
427    #[doc = "`11`"]
428    #[inline(always)]
429    pub fn is_n16(&self) -> bool {
430        *self == DAC_DRQ_CLR_CNT_A::N16
431    }
432}
433#[doc = "Field `dac_drq_clr_cnt` writer - DAC DRQ clear count"]
434pub type DAC_DRQ_CLR_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 7, DAC_DRQ_CLR_CNT_A>;
435impl<'a, REG> DAC_DRQ_CLR_CNT_W<'a, REG>
436where
437    REG: crate::Writable + crate::RegisterSpec,
438    REG::Ux: From<u8>,
439{
440    #[doc = "`0`"]
441    #[inline(always)]
442    pub fn wlevel(self) -> &'a mut crate::W<REG> {
443        self.variant(DAC_DRQ_CLR_CNT_A::WLEVEL)
444    }
445    #[doc = "`1`"]
446    #[inline(always)]
447    pub fn n4(self) -> &'a mut crate::W<REG> {
448        self.variant(DAC_DRQ_CLR_CNT_A::N4)
449    }
450    #[doc = "`10`"]
451    #[inline(always)]
452    pub fn n8(self) -> &'a mut crate::W<REG> {
453        self.variant(DAC_DRQ_CLR_CNT_A::N8)
454    }
455    #[doc = "`11`"]
456    #[inline(always)]
457    pub fn n16(self) -> &'a mut crate::W<REG> {
458        self.variant(DAC_DRQ_CLR_CNT_A::N16)
459    }
460}
461#[doc = "Field `tx_trig_level` reader - TX FIFO Empty Trigger Level"]
462pub type TX_TRIG_LEVEL_R = crate::FieldReader;
463#[doc = "Field `tx_trig_level` writer - TX FIFO Empty Trigger Level"]
464pub type TX_TRIG_LEVEL_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
465#[doc = "Field `fifo_mode` reader - "]
466pub type FIFO_MODE_R = crate::FieldReader<FIFO_MODE_A>;
467#[doc = "\n\nValue on reset: 0"]
468#[derive(Clone, Copy, Debug, PartialEq, Eq)]
469#[repr(u8)]
470pub enum FIFO_MODE_A {
471    #[doc = "0: `0`"]
472    BIG_ENDIAN = 0,
473    #[doc = "1: `1`"]
474    LITTLE_ENDIAN = 1,
475}
476impl From<FIFO_MODE_A> for u8 {
477    #[inline(always)]
478    fn from(variant: FIFO_MODE_A) -> Self {
479        variant as _
480    }
481}
482impl crate::FieldSpec for FIFO_MODE_A {
483    type Ux = u8;
484}
485impl FIFO_MODE_R {
486    #[doc = "Get enumerated values variant"]
487    #[inline(always)]
488    pub const fn variant(&self) -> Option<FIFO_MODE_A> {
489        match self.bits {
490            0 => Some(FIFO_MODE_A::BIG_ENDIAN),
491            1 => Some(FIFO_MODE_A::LITTLE_ENDIAN),
492            _ => None,
493        }
494    }
495    #[doc = "`0`"]
496    #[inline(always)]
497    pub fn is_big_endian(&self) -> bool {
498        *self == FIFO_MODE_A::BIG_ENDIAN
499    }
500    #[doc = "`1`"]
501    #[inline(always)]
502    pub fn is_little_endian(&self) -> bool {
503        *self == FIFO_MODE_A::LITTLE_ENDIAN
504    }
505}
506#[doc = "Field `fifo_mode` writer - "]
507pub type FIFO_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, FIFO_MODE_A>;
508impl<'a, REG> FIFO_MODE_W<'a, REG>
509where
510    REG: crate::Writable + crate::RegisterSpec,
511    REG::Ux: From<u8>,
512{
513    #[doc = "`0`"]
514    #[inline(always)]
515    pub fn big_endian(self) -> &'a mut crate::W<REG> {
516        self.variant(FIFO_MODE_A::BIG_ENDIAN)
517    }
518    #[doc = "`1`"]
519    #[inline(always)]
520    pub fn little_endian(self) -> &'a mut crate::W<REG> {
521        self.variant(FIFO_MODE_A::LITTLE_ENDIAN)
522    }
523}
524#[doc = "Field `send_last` reader - Audio sample select when TX FIFO underrun"]
525pub type SEND_LAST_R = crate::BitReader<SEND_LAST_A>;
526#[doc = "Audio sample select when TX FIFO underrun\n\nValue on reset: 0"]
527#[derive(Clone, Copy, Debug, PartialEq, Eq)]
528pub enum SEND_LAST_A {
529    #[doc = "0: `0`"]
530    ZERO = 0,
531    #[doc = "1: `1`"]
532    LAST = 1,
533}
534impl From<SEND_LAST_A> for bool {
535    #[inline(always)]
536    fn from(variant: SEND_LAST_A) -> Self {
537        variant as u8 != 0
538    }
539}
540impl SEND_LAST_R {
541    #[doc = "Get enumerated values variant"]
542    #[inline(always)]
543    pub const fn variant(&self) -> SEND_LAST_A {
544        match self.bits {
545            false => SEND_LAST_A::ZERO,
546            true => SEND_LAST_A::LAST,
547        }
548    }
549    #[doc = "`0`"]
550    #[inline(always)]
551    pub fn is_zero(&self) -> bool {
552        *self == SEND_LAST_A::ZERO
553    }
554    #[doc = "`1`"]
555    #[inline(always)]
556    pub fn is_last(&self) -> bool {
557        *self == SEND_LAST_A::LAST
558    }
559}
560#[doc = "Field `send_last` writer - Audio sample select when TX FIFO underrun"]
561pub type SEND_LAST_W<'a, REG> = crate::BitWriter<'a, REG, SEND_LAST_A>;
562impl<'a, REG> SEND_LAST_W<'a, REG>
563where
564    REG: crate::Writable + crate::RegisterSpec,
565{
566    #[doc = "`0`"]
567    #[inline(always)]
568    pub fn zero(self) -> &'a mut crate::W<REG> {
569        self.variant(SEND_LAST_A::ZERO)
570    }
571    #[doc = "`1`"]
572    #[inline(always)]
573    pub fn last(self) -> &'a mut crate::W<REG> {
574        self.variant(SEND_LAST_A::LAST)
575    }
576}
577#[doc = "Field `fir_ver` reader - FIR Version"]
578pub type FIR_VER_R = crate::BitReader<FIR_VER_A>;
579#[doc = "FIR Version\n\nValue on reset: 0"]
580#[derive(Clone, Copy, Debug, PartialEq, Eq)]
581pub enum FIR_VER_A {
582    #[doc = "0: `0`"]
583    TAP_64 = 0,
584    #[doc = "1: `1`"]
585    TAP_32 = 1,
586}
587impl From<FIR_VER_A> for bool {
588    #[inline(always)]
589    fn from(variant: FIR_VER_A) -> Self {
590        variant as u8 != 0
591    }
592}
593impl FIR_VER_R {
594    #[doc = "Get enumerated values variant"]
595    #[inline(always)]
596    pub const fn variant(&self) -> FIR_VER_A {
597        match self.bits {
598            false => FIR_VER_A::TAP_64,
599            true => FIR_VER_A::TAP_32,
600        }
601    }
602    #[doc = "`0`"]
603    #[inline(always)]
604    pub fn is_tap_64(&self) -> bool {
605        *self == FIR_VER_A::TAP_64
606    }
607    #[doc = "`1`"]
608    #[inline(always)]
609    pub fn is_tap_32(&self) -> bool {
610        *self == FIR_VER_A::TAP_32
611    }
612}
613#[doc = "Field `fir_ver` writer - FIR Version"]
614pub type FIR_VER_W<'a, REG> = crate::BitWriter<'a, REG, FIR_VER_A>;
615impl<'a, REG> FIR_VER_W<'a, REG>
616where
617    REG: crate::Writable + crate::RegisterSpec,
618{
619    #[doc = "`0`"]
620    #[inline(always)]
621    pub fn tap_64(self) -> &'a mut crate::W<REG> {
622        self.variant(FIR_VER_A::TAP_64)
623    }
624    #[doc = "`1`"]
625    #[inline(always)]
626    pub fn tap_32(self) -> &'a mut crate::W<REG> {
627        self.variant(FIR_VER_A::TAP_32)
628    }
629}
630#[doc = "Field `dac_fs` reader - Sample Rate of DAC"]
631pub type DAC_FS_R = crate::FieldReader<DAC_FS_A>;
632#[doc = "Sample Rate of DAC\n\nValue on reset: 0"]
633#[derive(Clone, Copy, Debug, PartialEq, Eq)]
634#[repr(u8)]
635pub enum DAC_FS_A {
636    #[doc = "0: `0`"]
637    FS48K = 0,
638    #[doc = "1: `1`"]
639    FS32K = 1,
640    #[doc = "2: `10`"]
641    FS24K = 2,
642    #[doc = "3: `11`"]
643    FS16K = 3,
644    #[doc = "4: `100`"]
645    FS12K = 4,
646    #[doc = "5: `101`"]
647    FS8K = 5,
648    #[doc = "6: `110`"]
649    FS192K = 6,
650    #[doc = "7: `111`"]
651    FS96K = 7,
652}
653impl From<DAC_FS_A> for u8 {
654    #[inline(always)]
655    fn from(variant: DAC_FS_A) -> Self {
656        variant as _
657    }
658}
659impl crate::FieldSpec for DAC_FS_A {
660    type Ux = u8;
661}
662impl DAC_FS_R {
663    #[doc = "Get enumerated values variant"]
664    #[inline(always)]
665    pub const fn variant(&self) -> DAC_FS_A {
666        match self.bits {
667            0 => DAC_FS_A::FS48K,
668            1 => DAC_FS_A::FS32K,
669            2 => DAC_FS_A::FS24K,
670            3 => DAC_FS_A::FS16K,
671            4 => DAC_FS_A::FS12K,
672            5 => DAC_FS_A::FS8K,
673            6 => DAC_FS_A::FS192K,
674            7 => DAC_FS_A::FS96K,
675            _ => unreachable!(),
676        }
677    }
678    #[doc = "`0`"]
679    #[inline(always)]
680    pub fn is_fs48k(&self) -> bool {
681        *self == DAC_FS_A::FS48K
682    }
683    #[doc = "`1`"]
684    #[inline(always)]
685    pub fn is_fs32k(&self) -> bool {
686        *self == DAC_FS_A::FS32K
687    }
688    #[doc = "`10`"]
689    #[inline(always)]
690    pub fn is_fs24k(&self) -> bool {
691        *self == DAC_FS_A::FS24K
692    }
693    #[doc = "`11`"]
694    #[inline(always)]
695    pub fn is_fs16k(&self) -> bool {
696        *self == DAC_FS_A::FS16K
697    }
698    #[doc = "`100`"]
699    #[inline(always)]
700    pub fn is_fs12k(&self) -> bool {
701        *self == DAC_FS_A::FS12K
702    }
703    #[doc = "`101`"]
704    #[inline(always)]
705    pub fn is_fs8k(&self) -> bool {
706        *self == DAC_FS_A::FS8K
707    }
708    #[doc = "`110`"]
709    #[inline(always)]
710    pub fn is_fs192k(&self) -> bool {
711        *self == DAC_FS_A::FS192K
712    }
713    #[doc = "`111`"]
714    #[inline(always)]
715    pub fn is_fs96k(&self) -> bool {
716        *self == DAC_FS_A::FS96K
717    }
718}
719#[doc = "Field `dac_fs` writer - Sample Rate of DAC"]
720pub type DAC_FS_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 3, DAC_FS_A>;
721impl<'a, REG> DAC_FS_W<'a, REG>
722where
723    REG: crate::Writable + crate::RegisterSpec,
724    REG::Ux: From<u8>,
725{
726    #[doc = "`0`"]
727    #[inline(always)]
728    pub fn fs48k(self) -> &'a mut crate::W<REG> {
729        self.variant(DAC_FS_A::FS48K)
730    }
731    #[doc = "`1`"]
732    #[inline(always)]
733    pub fn fs32k(self) -> &'a mut crate::W<REG> {
734        self.variant(DAC_FS_A::FS32K)
735    }
736    #[doc = "`10`"]
737    #[inline(always)]
738    pub fn fs24k(self) -> &'a mut crate::W<REG> {
739        self.variant(DAC_FS_A::FS24K)
740    }
741    #[doc = "`11`"]
742    #[inline(always)]
743    pub fn fs16k(self) -> &'a mut crate::W<REG> {
744        self.variant(DAC_FS_A::FS16K)
745    }
746    #[doc = "`100`"]
747    #[inline(always)]
748    pub fn fs12k(self) -> &'a mut crate::W<REG> {
749        self.variant(DAC_FS_A::FS12K)
750    }
751    #[doc = "`101`"]
752    #[inline(always)]
753    pub fn fs8k(self) -> &'a mut crate::W<REG> {
754        self.variant(DAC_FS_A::FS8K)
755    }
756    #[doc = "`110`"]
757    #[inline(always)]
758    pub fn fs192k(self) -> &'a mut crate::W<REG> {
759        self.variant(DAC_FS_A::FS192K)
760    }
761    #[doc = "`111`"]
762    #[inline(always)]
763    pub fn fs96k(self) -> &'a mut crate::W<REG> {
764        self.variant(DAC_FS_A::FS96K)
765    }
766}
767impl R {
768    #[doc = "Bit 0 - DAC FIFO Flush"]
769    #[inline(always)]
770    pub fn fifo_flush(&self) -> FIFO_FLUSH_R {
771        FIFO_FLUSH_R::new((self.bits & 1) != 0)
772    }
773    #[doc = "Bit 1 - DAC FIFO Overrun IRQ Enable"]
774    #[inline(always)]
775    pub fn fifo_overrun_irq_en(&self) -> FIFO_OVERRUN_IRQ_EN_R {
776        FIFO_OVERRUN_IRQ_EN_R::new(((self.bits >> 1) & 1) != 0)
777    }
778    #[doc = "Bit 2 - DAC FIFO Underrun IRQ Enable"]
779    #[inline(always)]
780    pub fn fifo_underrun_irq_en(&self) -> FIFO_UNDERRUN_IRQ_EN_R {
781        FIFO_UNDERRUN_IRQ_EN_R::new(((self.bits >> 2) & 1) != 0)
782    }
783    #[doc = "Bit 3 - DAC FIFO Empty IRQ Enable"]
784    #[inline(always)]
785    pub fn dac_irq_en(&self) -> DAC_IRQ_EN_R {
786        DAC_IRQ_EN_R::new(((self.bits >> 3) & 1) != 0)
787    }
788    #[doc = "Bit 4 - DAC FIFO Empty DRQ Enable"]
789    #[inline(always)]
790    pub fn dac_drq_en(&self) -> DAC_DRQ_EN_R {
791        DAC_DRQ_EN_R::new(((self.bits >> 4) & 1) != 0)
792    }
793    #[doc = "Bit 5 - Transmitting Audio Sample Resolution"]
794    #[inline(always)]
795    pub fn tx_sample_bits(&self) -> TX_SAMPLE_BITS_R {
796        TX_SAMPLE_BITS_R::new(((self.bits >> 5) & 1) != 0)
797    }
798    #[doc = "Bit 6 - DAC Mono Enable"]
799    #[inline(always)]
800    pub fn dac_mono_en(&self) -> DAC_MONO_EN_R {
801        DAC_MONO_EN_R::new(((self.bits >> 6) & 1) != 0)
802    }
803    #[doc = "Bits 8:14 - DAC DRQ clear count"]
804    #[inline(always)]
805    pub fn dac_drq_clr_cnt(&self) -> DAC_DRQ_CLR_CNT_R {
806        DAC_DRQ_CLR_CNT_R::new(((self.bits >> 8) & 0x7f) as u8)
807    }
808    #[doc = "Bits 8:14 - TX FIFO Empty Trigger Level"]
809    #[inline(always)]
810    pub fn tx_trig_level(&self) -> TX_TRIG_LEVEL_R {
811        TX_TRIG_LEVEL_R::new(((self.bits >> 8) & 0x7f) as u8)
812    }
813    #[doc = "Bits 24:25"]
814    #[inline(always)]
815    pub fn fifo_mode(&self) -> FIFO_MODE_R {
816        FIFO_MODE_R::new(((self.bits >> 24) & 3) as u8)
817    }
818    #[doc = "Bit 26 - Audio sample select when TX FIFO underrun"]
819    #[inline(always)]
820    pub fn send_last(&self) -> SEND_LAST_R {
821        SEND_LAST_R::new(((self.bits >> 26) & 1) != 0)
822    }
823    #[doc = "Bit 28 - FIR Version"]
824    #[inline(always)]
825    pub fn fir_ver(&self) -> FIR_VER_R {
826        FIR_VER_R::new(((self.bits >> 28) & 1) != 0)
827    }
828    #[doc = "Bits 29:31 - Sample Rate of DAC"]
829    #[inline(always)]
830    pub fn dac_fs(&self) -> DAC_FS_R {
831        DAC_FS_R::new(((self.bits >> 29) & 7) as u8)
832    }
833}
834impl W {
835    #[doc = "Bit 0 - DAC FIFO Flush"]
836    #[inline(always)]
837    #[must_use]
838    pub fn fifo_flush(&mut self) -> FIFO_FLUSH_W<AC_DAC_FIFOC_SPEC> {
839        FIFO_FLUSH_W::new(self, 0)
840    }
841    #[doc = "Bit 1 - DAC FIFO Overrun IRQ Enable"]
842    #[inline(always)]
843    #[must_use]
844    pub fn fifo_overrun_irq_en(&mut self) -> FIFO_OVERRUN_IRQ_EN_W<AC_DAC_FIFOC_SPEC> {
845        FIFO_OVERRUN_IRQ_EN_W::new(self, 1)
846    }
847    #[doc = "Bit 2 - DAC FIFO Underrun IRQ Enable"]
848    #[inline(always)]
849    #[must_use]
850    pub fn fifo_underrun_irq_en(&mut self) -> FIFO_UNDERRUN_IRQ_EN_W<AC_DAC_FIFOC_SPEC> {
851        FIFO_UNDERRUN_IRQ_EN_W::new(self, 2)
852    }
853    #[doc = "Bit 3 - DAC FIFO Empty IRQ Enable"]
854    #[inline(always)]
855    #[must_use]
856    pub fn dac_irq_en(&mut self) -> DAC_IRQ_EN_W<AC_DAC_FIFOC_SPEC> {
857        DAC_IRQ_EN_W::new(self, 3)
858    }
859    #[doc = "Bit 4 - DAC FIFO Empty DRQ Enable"]
860    #[inline(always)]
861    #[must_use]
862    pub fn dac_drq_en(&mut self) -> DAC_DRQ_EN_W<AC_DAC_FIFOC_SPEC> {
863        DAC_DRQ_EN_W::new(self, 4)
864    }
865    #[doc = "Bit 5 - Transmitting Audio Sample Resolution"]
866    #[inline(always)]
867    #[must_use]
868    pub fn tx_sample_bits(&mut self) -> TX_SAMPLE_BITS_W<AC_DAC_FIFOC_SPEC> {
869        TX_SAMPLE_BITS_W::new(self, 5)
870    }
871    #[doc = "Bit 6 - DAC Mono Enable"]
872    #[inline(always)]
873    #[must_use]
874    pub fn dac_mono_en(&mut self) -> DAC_MONO_EN_W<AC_DAC_FIFOC_SPEC> {
875        DAC_MONO_EN_W::new(self, 6)
876    }
877    #[doc = "Bits 8:14 - DAC DRQ clear count"]
878    #[inline(always)]
879    #[must_use]
880    pub fn dac_drq_clr_cnt(&mut self) -> DAC_DRQ_CLR_CNT_W<AC_DAC_FIFOC_SPEC> {
881        DAC_DRQ_CLR_CNT_W::new(self, 8)
882    }
883    #[doc = "Bits 8:14 - TX FIFO Empty Trigger Level"]
884    #[inline(always)]
885    #[must_use]
886    pub fn tx_trig_level(&mut self) -> TX_TRIG_LEVEL_W<AC_DAC_FIFOC_SPEC> {
887        TX_TRIG_LEVEL_W::new(self, 8)
888    }
889    #[doc = "Bits 24:25"]
890    #[inline(always)]
891    #[must_use]
892    pub fn fifo_mode(&mut self) -> FIFO_MODE_W<AC_DAC_FIFOC_SPEC> {
893        FIFO_MODE_W::new(self, 24)
894    }
895    #[doc = "Bit 26 - Audio sample select when TX FIFO underrun"]
896    #[inline(always)]
897    #[must_use]
898    pub fn send_last(&mut self) -> SEND_LAST_W<AC_DAC_FIFOC_SPEC> {
899        SEND_LAST_W::new(self, 26)
900    }
901    #[doc = "Bit 28 - FIR Version"]
902    #[inline(always)]
903    #[must_use]
904    pub fn fir_ver(&mut self) -> FIR_VER_W<AC_DAC_FIFOC_SPEC> {
905        FIR_VER_W::new(self, 28)
906    }
907    #[doc = "Bits 29:31 - Sample Rate of DAC"]
908    #[inline(always)]
909    #[must_use]
910    pub fn dac_fs(&mut self) -> DAC_FS_W<AC_DAC_FIFOC_SPEC> {
911        DAC_FS_W::new(self, 29)
912    }
913    #[doc = r" Writes raw bits to the register."]
914    #[doc = r""]
915    #[doc = r" # Safety"]
916    #[doc = r""]
917    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
918    #[inline(always)]
919    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
920        self.bits = bits;
921        self
922    }
923}
924#[doc = "DAC FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ac_dac_fifoc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ac_dac_fifoc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
925pub struct AC_DAC_FIFOC_SPEC;
926impl crate::RegisterSpec for AC_DAC_FIFOC_SPEC {
927    type Ux = u32;
928}
929#[doc = "`read()` method returns [`ac_dac_fifoc::R`](R) reader structure"]
930impl crate::Readable for AC_DAC_FIFOC_SPEC {}
931#[doc = "`write(|w| ..)` method takes [`ac_dac_fifoc::W`](W) writer structure"]
932impl crate::Writable for AC_DAC_FIFOC_SPEC {
933    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
934    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
935}
936#[doc = "`reset()` method sets ac_dac_fifoc to value 0"]
937impl crate::Resettable for AC_DAC_FIFOC_SPEC {
938    const RESET_VALUE: Self::Ux = 0;
939}
d1_pac/audio_codec/ac_dac_fifoc.rs

d1_pac/audio_codec/
ac_dac_fifoc.rs
