d1_pac/audio_codec/
ac_dac_dpc.rs

1#[doc = "Register `ac_dac_dpc` reader"]
2pub type R = crate::R<AC_DAC_DPC_SPEC>;
3#[doc = "Register `ac_dac_dpc` writer"]
4pub type W = crate::W<AC_DAC_DPC_SPEC>;
5#[doc = "Field `hub_en` reader - Audio Hub Enable\n\nThe bit takes effect only when the EN_DA is set to 1.\n\nSystem Domain: Audio Codec/I2S0/I2S1/I2S2/OWA TXFIFO Hub Enable."]
6pub type HUB_EN_R = crate::BitReader<HUB_EN_A>;
7#[doc = "Audio Hub Enable\n\nThe bit takes effect only when the EN_DA is set to 1.\n\nSystem Domain: Audio Codec/I2S0/I2S1/I2S2/OWA TXFIFO Hub Enable.\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum HUB_EN_A {
10    #[doc = "0: `0`"]
11    DISABLE = 0,
12    #[doc = "1: `1`"]
13    ENABLE = 1,
14}
15impl From<HUB_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: HUB_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl HUB_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> HUB_EN_A {
25        match self.bits {
26            false => HUB_EN_A::DISABLE,
27            true => HUB_EN_A::ENABLE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == HUB_EN_A::DISABLE
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == HUB_EN_A::ENABLE
39    }
40}
41#[doc = "Field `hub_en` writer - Audio Hub Enable\n\nThe bit takes effect only when the EN_DA is set to 1.\n\nSystem Domain: Audio Codec/I2S0/I2S1/I2S2/OWA TXFIFO Hub Enable."]
42pub type HUB_EN_W<'a, REG> = crate::BitWriter<'a, REG, HUB_EN_A>;
43impl<'a, REG> HUB_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(HUB_EN_A::DISABLE)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(HUB_EN_A::ENABLE)
56    }
57}
58#[doc = "Field `dvol` reader - Digital Volume Control: DVC\n\nATT = DVC\\[5:0\\] * (-1.16 dB)\n\n64 steps, -1.16 dB/step"]
59pub type DVOL_R = crate::FieldReader;
60#[doc = "Field `dvol` writer - Digital Volume Control: DVC\n\nATT = DVC\\[5:0\\] * (-1.16 dB)\n\n64 steps, -1.16 dB/step"]
61pub type DVOL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
62#[doc = "Field `hpf_en` reader - High Pass Filter Enable"]
63pub type HPF_EN_R = crate::BitReader<HPF_EN_A>;
64#[doc = "High Pass Filter Enable\n\nValue on reset: 0"]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum HPF_EN_A {
67    #[doc = "0: `0`"]
68    DISABLE = 0,
69    #[doc = "1: `1`"]
70    ENABLE = 1,
71}
72impl From<HPF_EN_A> for bool {
73    #[inline(always)]
74    fn from(variant: HPF_EN_A) -> Self {
75        variant as u8 != 0
76    }
77}
78impl HPF_EN_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub const fn variant(&self) -> HPF_EN_A {
82        match self.bits {
83            false => HPF_EN_A::DISABLE,
84            true => HPF_EN_A::ENABLE,
85        }
86    }
87    #[doc = "`0`"]
88    #[inline(always)]
89    pub fn is_disable(&self) -> bool {
90        *self == HPF_EN_A::DISABLE
91    }
92    #[doc = "`1`"]
93    #[inline(always)]
94    pub fn is_enable(&self) -> bool {
95        *self == HPF_EN_A::ENABLE
96    }
97}
98#[doc = "Field `hpf_en` writer - High Pass Filter Enable"]
99pub type HPF_EN_W<'a, REG> = crate::BitWriter<'a, REG, HPF_EN_A>;
100impl<'a, REG> HPF_EN_W<'a, REG>
101where
102    REG: crate::Writable + crate::RegisterSpec,
103{
104    #[doc = "`0`"]
105    #[inline(always)]
106    pub fn disable(self) -> &'a mut crate::W<REG> {
107        self.variant(HPF_EN_A::DISABLE)
108    }
109    #[doc = "`1`"]
110    #[inline(always)]
111    pub fn enable(self) -> &'a mut crate::W<REG> {
112        self.variant(HPF_EN_A::ENABLE)
113    }
114}
115#[doc = "Field `dwa` reader - DWA Function Disable"]
116pub type DWA_R = crate::BitReader<DWA_A>;
117#[doc = "DWA Function Disable\n\nValue on reset: 0"]
118#[derive(Clone, Copy, Debug, PartialEq, Eq)]
119pub enum DWA_A {
120    #[doc = "0: `0`"]
121    DISABLE = 0,
122    #[doc = "1: `1`"]
123    ENABLE = 1,
124}
125impl From<DWA_A> for bool {
126    #[inline(always)]
127    fn from(variant: DWA_A) -> Self {
128        variant as u8 != 0
129    }
130}
131impl DWA_R {
132    #[doc = "Get enumerated values variant"]
133    #[inline(always)]
134    pub const fn variant(&self) -> DWA_A {
135        match self.bits {
136            false => DWA_A::DISABLE,
137            true => DWA_A::ENABLE,
138        }
139    }
140    #[doc = "`0`"]
141    #[inline(always)]
142    pub fn is_disable(&self) -> bool {
143        *self == DWA_A::DISABLE
144    }
145    #[doc = "`1`"]
146    #[inline(always)]
147    pub fn is_enable(&self) -> bool {
148        *self == DWA_A::ENABLE
149    }
150}
151#[doc = "Field `dwa` writer - DWA Function Disable"]
152pub type DWA_W<'a, REG> = crate::BitWriter<'a, REG, DWA_A>;
153impl<'a, REG> DWA_W<'a, REG>
154where
155    REG: crate::Writable + crate::RegisterSpec,
156{
157    #[doc = "`0`"]
158    #[inline(always)]
159    pub fn disable(self) -> &'a mut crate::W<REG> {
160        self.variant(DWA_A::DISABLE)
161    }
162    #[doc = "`1`"]
163    #[inline(always)]
164    pub fn enable(self) -> &'a mut crate::W<REG> {
165        self.variant(DWA_A::ENABLE)
166    }
167}
168#[doc = "Field `modqu` reader - Internal DAC Quantization Levels.\n\nLevels = \\[7*(21 + MODQU\\[3:0\\])\\]/128\n\nDefault levels = 7*21/128 = 1.15"]
169pub type MODQU_R = crate::FieldReader;
170#[doc = "Field `modqu` writer - Internal DAC Quantization Levels.\n\nLevels = \\[7*(21 + MODQU\\[3:0\\])\\]/128\n\nDefault levels = 7*21/128 = 1.15"]
171pub type MODQU_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
172#[doc = "Field `en_da` reader - DAC Digital Part Enable"]
173pub type EN_DA_R = crate::BitReader<EN_DA_A>;
174#[doc = "DAC Digital Part Enable\n\nValue on reset: 0"]
175#[derive(Clone, Copy, Debug, PartialEq, Eq)]
176pub enum EN_DA_A {
177    #[doc = "0: `0`"]
178    DISABLE = 0,
179    #[doc = "1: `1`"]
180    ENABLE = 1,
181}
182impl From<EN_DA_A> for bool {
183    #[inline(always)]
184    fn from(variant: EN_DA_A) -> Self {
185        variant as u8 != 0
186    }
187}
188impl EN_DA_R {
189    #[doc = "Get enumerated values variant"]
190    #[inline(always)]
191    pub const fn variant(&self) -> EN_DA_A {
192        match self.bits {
193            false => EN_DA_A::DISABLE,
194            true => EN_DA_A::ENABLE,
195        }
196    }
197    #[doc = "`0`"]
198    #[inline(always)]
199    pub fn is_disable(&self) -> bool {
200        *self == EN_DA_A::DISABLE
201    }
202    #[doc = "`1`"]
203    #[inline(always)]
204    pub fn is_enable(&self) -> bool {
205        *self == EN_DA_A::ENABLE
206    }
207}
208#[doc = "Field `en_da` writer - DAC Digital Part Enable"]
209pub type EN_DA_W<'a, REG> = crate::BitWriter<'a, REG, EN_DA_A>;
210impl<'a, REG> EN_DA_W<'a, REG>
211where
212    REG: crate::Writable + crate::RegisterSpec,
213{
214    #[doc = "`0`"]
215    #[inline(always)]
216    pub fn disable(self) -> &'a mut crate::W<REG> {
217        self.variant(EN_DA_A::DISABLE)
218    }
219    #[doc = "`1`"]
220    #[inline(always)]
221    pub fn enable(self) -> &'a mut crate::W<REG> {
222        self.variant(EN_DA_A::ENABLE)
223    }
224}
225impl R {
226    #[doc = "Bit 0 - Audio Hub Enable\n\nThe bit takes effect only when the EN_DA is set to 1.\n\nSystem Domain: Audio Codec/I2S0/I2S1/I2S2/OWA TXFIFO Hub Enable."]
227    #[inline(always)]
228    pub fn hub_en(&self) -> HUB_EN_R {
229        HUB_EN_R::new((self.bits & 1) != 0)
230    }
231    #[doc = "Bits 12:17 - Digital Volume Control: DVC\n\nATT = DVC\\[5:0\\] * (-1.16 dB)\n\n64 steps, -1.16 dB/step"]
232    #[inline(always)]
233    pub fn dvol(&self) -> DVOL_R {
234        DVOL_R::new(((self.bits >> 12) & 0x3f) as u8)
235    }
236    #[doc = "Bit 18 - High Pass Filter Enable"]
237    #[inline(always)]
238    pub fn hpf_en(&self) -> HPF_EN_R {
239        HPF_EN_R::new(((self.bits >> 18) & 1) != 0)
240    }
241    #[doc = "Bit 24 - DWA Function Disable"]
242    #[inline(always)]
243    pub fn dwa(&self) -> DWA_R {
244        DWA_R::new(((self.bits >> 24) & 1) != 0)
245    }
246    #[doc = "Bits 25:28 - Internal DAC Quantization Levels.\n\nLevels = \\[7*(21 + MODQU\\[3:0\\])\\]/128\n\nDefault levels = 7*21/128 = 1.15"]
247    #[inline(always)]
248    pub fn modqu(&self) -> MODQU_R {
249        MODQU_R::new(((self.bits >> 25) & 0x0f) as u8)
250    }
251    #[doc = "Bit 31 - DAC Digital Part Enable"]
252    #[inline(always)]
253    pub fn en_da(&self) -> EN_DA_R {
254        EN_DA_R::new(((self.bits >> 31) & 1) != 0)
255    }
256}
257impl W {
258    #[doc = "Bit 0 - Audio Hub Enable\n\nThe bit takes effect only when the EN_DA is set to 1.\n\nSystem Domain: Audio Codec/I2S0/I2S1/I2S2/OWA TXFIFO Hub Enable."]
259    #[inline(always)]
260    #[must_use]
261    pub fn hub_en(&mut self) -> HUB_EN_W<AC_DAC_DPC_SPEC> {
262        HUB_EN_W::new(self, 0)
263    }
264    #[doc = "Bits 12:17 - Digital Volume Control: DVC\n\nATT = DVC\\[5:0\\] * (-1.16 dB)\n\n64 steps, -1.16 dB/step"]
265    #[inline(always)]
266    #[must_use]
267    pub fn dvol(&mut self) -> DVOL_W<AC_DAC_DPC_SPEC> {
268        DVOL_W::new(self, 12)
269    }
270    #[doc = "Bit 18 - High Pass Filter Enable"]
271    #[inline(always)]
272    #[must_use]
273    pub fn hpf_en(&mut self) -> HPF_EN_W<AC_DAC_DPC_SPEC> {
274        HPF_EN_W::new(self, 18)
275    }
276    #[doc = "Bit 24 - DWA Function Disable"]
277    #[inline(always)]
278    #[must_use]
279    pub fn dwa(&mut self) -> DWA_W<AC_DAC_DPC_SPEC> {
280        DWA_W::new(self, 24)
281    }
282    #[doc = "Bits 25:28 - Internal DAC Quantization Levels.\n\nLevels = \\[7*(21 + MODQU\\[3:0\\])\\]/128\n\nDefault levels = 7*21/128 = 1.15"]
283    #[inline(always)]
284    #[must_use]
285    pub fn modqu(&mut self) -> MODQU_W<AC_DAC_DPC_SPEC> {
286        MODQU_W::new(self, 25)
287    }
288    #[doc = "Bit 31 - DAC Digital Part Enable"]
289    #[inline(always)]
290    #[must_use]
291    pub fn en_da(&mut self) -> EN_DA_W<AC_DAC_DPC_SPEC> {
292        EN_DA_W::new(self, 31)
293    }
294    #[doc = r" Writes raw bits to the register."]
295    #[doc = r""]
296    #[doc = r" # Safety"]
297    #[doc = r""]
298    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
299    #[inline(always)]
300    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
301        self.bits = bits;
302        self
303    }
304}
305#[doc = "DAC Digital Part Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ac_dac_dpc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ac_dac_dpc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
306pub struct AC_DAC_DPC_SPEC;
307impl crate::RegisterSpec for AC_DAC_DPC_SPEC {
308    type Ux = u32;
309}
310#[doc = "`read()` method returns [`ac_dac_dpc::R`](R) reader structure"]
311impl crate::Readable for AC_DAC_DPC_SPEC {}
312#[doc = "`write(|w| ..)` method takes [`ac_dac_dpc::W`](W) writer structure"]
313impl crate::Writable for AC_DAC_DPC_SPEC {
314    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
315    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
316}
317#[doc = "`reset()` method sets ac_dac_dpc to value 0"]
318impl crate::Resettable for AC_DAC_DPC_SPEC {
319    const RESET_VALUE: Self::Ux = 0;
320}
d1_pac/audio_codec/ac_dac_dpc.rs

d1_pac/audio_codec/
ac_dac_dpc.rs
