d1_pac/audio_codec/
ac_dac_dg.rs

1#[doc = "Register `ac_dac_dg` reader"]
2pub type R = crate::R<AC_DAC_DG_SPEC>;
3#[doc = "Register `ac_dac_dg` writer"]
4pub type W = crate::W<AC_DAC_DG_SPEC>;
5#[doc = "Field `adda_loop_mode` reader - ADDA Loop Mode Select"]
6pub type ADDA_LOOP_MODE_R = crate::FieldReader<ADDA_LOOP_MODE_A>;
7#[doc = "ADDA Loop Mode Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum ADDA_LOOP_MODE_A {
11    #[doc = "0: `0`"]
12    DISABLE = 0,
13    #[doc = "1: ADDA LOOP MODE DACL/DACR is connected to ADC1/ADC2"]
14    ADC12 = 1,
15    #[doc = "2: ADDA LOOP MODE DACL/DACR is connected to ADC3"]
16    ADC3 = 2,
17}
18impl From<ADDA_LOOP_MODE_A> for u8 {
19    #[inline(always)]
20    fn from(variant: ADDA_LOOP_MODE_A) -> Self {
21        variant as _
22    }
23}
24impl crate::FieldSpec for ADDA_LOOP_MODE_A {
25    type Ux = u8;
26}
27impl ADDA_LOOP_MODE_R {
28    #[doc = "Get enumerated values variant"]
29    #[inline(always)]
30    pub const fn variant(&self) -> Option<ADDA_LOOP_MODE_A> {
31        match self.bits {
32            0 => Some(ADDA_LOOP_MODE_A::DISABLE),
33            1 => Some(ADDA_LOOP_MODE_A::ADC12),
34            2 => Some(ADDA_LOOP_MODE_A::ADC3),
35            _ => None,
36        }
37    }
38    #[doc = "`0`"]
39    #[inline(always)]
40    pub fn is_disable(&self) -> bool {
41        *self == ADDA_LOOP_MODE_A::DISABLE
42    }
43    #[doc = "ADDA LOOP MODE DACL/DACR is connected to ADC1/ADC2"]
44    #[inline(always)]
45    pub fn is_adc12(&self) -> bool {
46        *self == ADDA_LOOP_MODE_A::ADC12
47    }
48    #[doc = "ADDA LOOP MODE DACL/DACR is connected to ADC3"]
49    #[inline(always)]
50    pub fn is_adc3(&self) -> bool {
51        *self == ADDA_LOOP_MODE_A::ADC3
52    }
53}
54#[doc = "Field `adda_loop_mode` writer - ADDA Loop Mode Select"]
55pub type ADDA_LOOP_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3, ADDA_LOOP_MODE_A>;
56impl<'a, REG> ADDA_LOOP_MODE_W<'a, REG>
57where
58    REG: crate::Writable + crate::RegisterSpec,
59    REG::Ux: From<u8>,
60{
61    #[doc = "`0`"]
62    #[inline(always)]
63    pub fn disable(self) -> &'a mut crate::W<REG> {
64        self.variant(ADDA_LOOP_MODE_A::DISABLE)
65    }
66    #[doc = "ADDA LOOP MODE DACL/DACR is connected to ADC1/ADC2"]
67    #[inline(always)]
68    pub fn adc12(self) -> &'a mut crate::W<REG> {
69        self.variant(ADDA_LOOP_MODE_A::ADC12)
70    }
71    #[doc = "ADDA LOOP MODE DACL/DACR is connected to ADC3"]
72    #[inline(always)]
73    pub fn adc3(self) -> &'a mut crate::W<REG> {
74        self.variant(ADDA_LOOP_MODE_A::ADC3)
75    }
76}
77#[doc = "Field `da_swp` reader - DAC Output Channel Swap Enable"]
78pub type DA_SWP_R = crate::BitReader<DA_SWP_A>;
79#[doc = "DAC Output Channel Swap Enable\n\nValue on reset: 0"]
80#[derive(Clone, Copy, Debug, PartialEq, Eq)]
81pub enum DA_SWP_A {
82    #[doc = "0: `0`"]
83    DISABLE = 0,
84    #[doc = "1: `1`"]
85    ENABLE = 1,
86}
87impl From<DA_SWP_A> for bool {
88    #[inline(always)]
89    fn from(variant: DA_SWP_A) -> Self {
90        variant as u8 != 0
91    }
92}
93impl DA_SWP_R {
94    #[doc = "Get enumerated values variant"]
95    #[inline(always)]
96    pub const fn variant(&self) -> DA_SWP_A {
97        match self.bits {
98            false => DA_SWP_A::DISABLE,
99            true => DA_SWP_A::ENABLE,
100        }
101    }
102    #[doc = "`0`"]
103    #[inline(always)]
104    pub fn is_disable(&self) -> bool {
105        *self == DA_SWP_A::DISABLE
106    }
107    #[doc = "`1`"]
108    #[inline(always)]
109    pub fn is_enable(&self) -> bool {
110        *self == DA_SWP_A::ENABLE
111    }
112}
113#[doc = "Field `da_swp` writer - DAC Output Channel Swap Enable"]
114pub type DA_SWP_W<'a, REG> = crate::BitWriter<'a, REG, DA_SWP_A>;
115impl<'a, REG> DA_SWP_W<'a, REG>
116where
117    REG: crate::Writable + crate::RegisterSpec,
118{
119    #[doc = "`0`"]
120    #[inline(always)]
121    pub fn disable(self) -> &'a mut crate::W<REG> {
122        self.variant(DA_SWP_A::DISABLE)
123    }
124    #[doc = "`1`"]
125    #[inline(always)]
126    pub fn enable(self) -> &'a mut crate::W<REG> {
127        self.variant(DA_SWP_A::ENABLE)
128    }
129}
130#[doc = "Field `codec_clk_select` reader - CODEC Clock Source Select"]
131pub type CODEC_CLK_SELECT_R = crate::BitReader<CODEC_CLK_SELECT_A>;
132#[doc = "CODEC Clock Source Select\n\nValue on reset: 0"]
133#[derive(Clone, Copy, Debug, PartialEq, Eq)]
134pub enum CODEC_CLK_SELECT_A {
135    #[doc = "0: CODEC clock from PLL"]
136    PLL = 0,
137    #[doc = "1: CODEC clock from OSC (for Debug)"]
138    OSC = 1,
139}
140impl From<CODEC_CLK_SELECT_A> for bool {
141    #[inline(always)]
142    fn from(variant: CODEC_CLK_SELECT_A) -> Self {
143        variant as u8 != 0
144    }
145}
146impl CODEC_CLK_SELECT_R {
147    #[doc = "Get enumerated values variant"]
148    #[inline(always)]
149    pub const fn variant(&self) -> CODEC_CLK_SELECT_A {
150        match self.bits {
151            false => CODEC_CLK_SELECT_A::PLL,
152            true => CODEC_CLK_SELECT_A::OSC,
153        }
154    }
155    #[doc = "CODEC clock from PLL"]
156    #[inline(always)]
157    pub fn is_pll(&self) -> bool {
158        *self == CODEC_CLK_SELECT_A::PLL
159    }
160    #[doc = "CODEC clock from OSC (for Debug)"]
161    #[inline(always)]
162    pub fn is_osc(&self) -> bool {
163        *self == CODEC_CLK_SELECT_A::OSC
164    }
165}
166#[doc = "Field `codec_clk_select` writer - CODEC Clock Source Select"]
167pub type CODEC_CLK_SELECT_W<'a, REG> = crate::BitWriter<'a, REG, CODEC_CLK_SELECT_A>;
168impl<'a, REG> CODEC_CLK_SELECT_W<'a, REG>
169where
170    REG: crate::Writable + crate::RegisterSpec,
171{
172    #[doc = "CODEC clock from PLL"]
173    #[inline(always)]
174    pub fn pll(self) -> &'a mut crate::W<REG> {
175        self.variant(CODEC_CLK_SELECT_A::PLL)
176    }
177    #[doc = "CODEC clock from OSC (for Debug)"]
178    #[inline(always)]
179    pub fn osc(self) -> &'a mut crate::W<REG> {
180        self.variant(CODEC_CLK_SELECT_A::OSC)
181    }
182}
183#[doc = "Field `dac_pattern_select` reader - DAC Pattern Select"]
184pub type DAC_PATTERN_SELECT_R = crate::FieldReader<DAC_PATTERN_SELECT_A>;
185#[doc = "DAC Pattern Select\n\nValue on reset: 0"]
186#[derive(Clone, Copy, Debug, PartialEq, Eq)]
187#[repr(u8)]
188pub enum DAC_PATTERN_SELECT_A {
189    #[doc = "0: Normal (Audio sample from TX FIFO)"]
190    NORMAL = 0,
191    #[doc = "1: -6 dB Sin wave"]
192    SIN6 = 1,
193    #[doc = "2: -60 dB Sin wave"]
194    SIN60 = 2,
195    #[doc = "3: Silent wave"]
196    SILENT = 3,
197}
198impl From<DAC_PATTERN_SELECT_A> for u8 {
199    #[inline(always)]
200    fn from(variant: DAC_PATTERN_SELECT_A) -> Self {
201        variant as _
202    }
203}
204impl crate::FieldSpec for DAC_PATTERN_SELECT_A {
205    type Ux = u8;
206}
207impl DAC_PATTERN_SELECT_R {
208    #[doc = "Get enumerated values variant"]
209    #[inline(always)]
210    pub const fn variant(&self) -> DAC_PATTERN_SELECT_A {
211        match self.bits {
212            0 => DAC_PATTERN_SELECT_A::NORMAL,
213            1 => DAC_PATTERN_SELECT_A::SIN6,
214            2 => DAC_PATTERN_SELECT_A::SIN60,
215            3 => DAC_PATTERN_SELECT_A::SILENT,
216            _ => unreachable!(),
217        }
218    }
219    #[doc = "Normal (Audio sample from TX FIFO)"]
220    #[inline(always)]
221    pub fn is_normal(&self) -> bool {
222        *self == DAC_PATTERN_SELECT_A::NORMAL
223    }
224    #[doc = "-6 dB Sin wave"]
225    #[inline(always)]
226    pub fn is_sin6(&self) -> bool {
227        *self == DAC_PATTERN_SELECT_A::SIN6
228    }
229    #[doc = "-60 dB Sin wave"]
230    #[inline(always)]
231    pub fn is_sin60(&self) -> bool {
232        *self == DAC_PATTERN_SELECT_A::SIN60
233    }
234    #[doc = "Silent wave"]
235    #[inline(always)]
236    pub fn is_silent(&self) -> bool {
237        *self == DAC_PATTERN_SELECT_A::SILENT
238    }
239}
240#[doc = "Field `dac_pattern_select` writer - DAC Pattern Select"]
241pub type DAC_PATTERN_SELECT_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, DAC_PATTERN_SELECT_A>;
242impl<'a, REG> DAC_PATTERN_SELECT_W<'a, REG>
243where
244    REG: crate::Writable + crate::RegisterSpec,
245    REG::Ux: From<u8>,
246{
247    #[doc = "Normal (Audio sample from TX FIFO)"]
248    #[inline(always)]
249    pub fn normal(self) -> &'a mut crate::W<REG> {
250        self.variant(DAC_PATTERN_SELECT_A::NORMAL)
251    }
252    #[doc = "-6 dB Sin wave"]
253    #[inline(always)]
254    pub fn sin6(self) -> &'a mut crate::W<REG> {
255        self.variant(DAC_PATTERN_SELECT_A::SIN6)
256    }
257    #[doc = "-60 dB Sin wave"]
258    #[inline(always)]
259    pub fn sin60(self) -> &'a mut crate::W<REG> {
260        self.variant(DAC_PATTERN_SELECT_A::SIN60)
261    }
262    #[doc = "Silent wave"]
263    #[inline(always)]
264    pub fn silent(self) -> &'a mut crate::W<REG> {
265        self.variant(DAC_PATTERN_SELECT_A::SILENT)
266    }
267}
268#[doc = "Field `dac_modu_select` reader - DAC Modulator Debug Mode"]
269pub type DAC_MODU_SELECT_R = crate::BitReader<DAC_MODU_SELECT_A>;
270#[doc = "DAC Modulator Debug Mode\n\nValue on reset: 0"]
271#[derive(Clone, Copy, Debug, PartialEq, Eq)]
272pub enum DAC_MODU_SELECT_A {
273    #[doc = "0: `0`"]
274    NORMAL = 0,
275    #[doc = "1: `1`"]
276    DEBUG = 1,
277}
278impl From<DAC_MODU_SELECT_A> for bool {
279    #[inline(always)]
280    fn from(variant: DAC_MODU_SELECT_A) -> Self {
281        variant as u8 != 0
282    }
283}
284impl DAC_MODU_SELECT_R {
285    #[doc = "Get enumerated values variant"]
286    #[inline(always)]
287    pub const fn variant(&self) -> DAC_MODU_SELECT_A {
288        match self.bits {
289            false => DAC_MODU_SELECT_A::NORMAL,
290            true => DAC_MODU_SELECT_A::DEBUG,
291        }
292    }
293    #[doc = "`0`"]
294    #[inline(always)]
295    pub fn is_normal(&self) -> bool {
296        *self == DAC_MODU_SELECT_A::NORMAL
297    }
298    #[doc = "`1`"]
299    #[inline(always)]
300    pub fn is_debug(&self) -> bool {
301        *self == DAC_MODU_SELECT_A::DEBUG
302    }
303}
304#[doc = "Field `dac_modu_select` writer - DAC Modulator Debug Mode"]
305pub type DAC_MODU_SELECT_W<'a, REG> = crate::BitWriter<'a, REG, DAC_MODU_SELECT_A>;
306impl<'a, REG> DAC_MODU_SELECT_W<'a, REG>
307where
308    REG: crate::Writable + crate::RegisterSpec,
309{
310    #[doc = "`0`"]
311    #[inline(always)]
312    pub fn normal(self) -> &'a mut crate::W<REG> {
313        self.variant(DAC_MODU_SELECT_A::NORMAL)
314    }
315    #[doc = "`1`"]
316    #[inline(always)]
317    pub fn debug(self) -> &'a mut crate::W<REG> {
318        self.variant(DAC_MODU_SELECT_A::DEBUG)
319    }
320}
321impl R {
322    #[doc = "Bits 0:2 - ADDA Loop Mode Select"]
323    #[inline(always)]
324    pub fn adda_loop_mode(&self) -> ADDA_LOOP_MODE_R {
325        ADDA_LOOP_MODE_R::new((self.bits & 7) as u8)
326    }
327    #[doc = "Bit 6 - DAC Output Channel Swap Enable"]
328    #[inline(always)]
329    pub fn da_swp(&self) -> DA_SWP_R {
330        DA_SWP_R::new(((self.bits >> 6) & 1) != 0)
331    }
332    #[doc = "Bit 8 - CODEC Clock Source Select"]
333    #[inline(always)]
334    pub fn codec_clk_select(&self) -> CODEC_CLK_SELECT_R {
335        CODEC_CLK_SELECT_R::new(((self.bits >> 8) & 1) != 0)
336    }
337    #[doc = "Bits 9:10 - DAC Pattern Select"]
338    #[inline(always)]
339    pub fn dac_pattern_select(&self) -> DAC_PATTERN_SELECT_R {
340        DAC_PATTERN_SELECT_R::new(((self.bits >> 9) & 3) as u8)
341    }
342    #[doc = "Bit 11 - DAC Modulator Debug Mode"]
343    #[inline(always)]
344    pub fn dac_modu_select(&self) -> DAC_MODU_SELECT_R {
345        DAC_MODU_SELECT_R::new(((self.bits >> 11) & 1) != 0)
346    }
347}
348impl W {
349    #[doc = "Bits 0:2 - ADDA Loop Mode Select"]
350    #[inline(always)]
351    #[must_use]
352    pub fn adda_loop_mode(&mut self) -> ADDA_LOOP_MODE_W<AC_DAC_DG_SPEC> {
353        ADDA_LOOP_MODE_W::new(self, 0)
354    }
355    #[doc = "Bit 6 - DAC Output Channel Swap Enable"]
356    #[inline(always)]
357    #[must_use]
358    pub fn da_swp(&mut self) -> DA_SWP_W<AC_DAC_DG_SPEC> {
359        DA_SWP_W::new(self, 6)
360    }
361    #[doc = "Bit 8 - CODEC Clock Source Select"]
362    #[inline(always)]
363    #[must_use]
364    pub fn codec_clk_select(&mut self) -> CODEC_CLK_SELECT_W<AC_DAC_DG_SPEC> {
365        CODEC_CLK_SELECT_W::new(self, 8)
366    }
367    #[doc = "Bits 9:10 - DAC Pattern Select"]
368    #[inline(always)]
369    #[must_use]
370    pub fn dac_pattern_select(&mut self) -> DAC_PATTERN_SELECT_W<AC_DAC_DG_SPEC> {
371        DAC_PATTERN_SELECT_W::new(self, 9)
372    }
373    #[doc = "Bit 11 - DAC Modulator Debug Mode"]
374    #[inline(always)]
375    #[must_use]
376    pub fn dac_modu_select(&mut self) -> DAC_MODU_SELECT_W<AC_DAC_DG_SPEC> {
377        DAC_MODU_SELECT_W::new(self, 11)
378    }
379    #[doc = r" Writes raw bits to the register."]
380    #[doc = r""]
381    #[doc = r" # Safety"]
382    #[doc = r""]
383    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
384    #[inline(always)]
385    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
386        self.bits = bits;
387        self
388    }
389}
390#[doc = "DAC Debug Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ac_dac_dg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ac_dac_dg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
391pub struct AC_DAC_DG_SPEC;
392impl crate::RegisterSpec for AC_DAC_DG_SPEC {
393    type Ux = u32;
394}
395#[doc = "`read()` method returns [`ac_dac_dg::R`](R) reader structure"]
396impl crate::Readable for AC_DAC_DG_SPEC {}
397#[doc = "`write(|w| ..)` method takes [`ac_dac_dg::W`](W) writer structure"]
398impl crate::Writable for AC_DAC_DG_SPEC {
399    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
400    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
401}
402#[doc = "`reset()` method sets ac_dac_dg to value 0"]
403impl crate::Resettable for AC_DAC_DG_SPEC {
404    const RESET_VALUE: Self::Ux = 0;
405}
d1_pac/audio_codec/ac_dac_dg.rs

d1_pac/audio_codec/
ac_dac_dg.rs
