d1_pac/audio_codec/
ac_adc_fifoc.rs

1#[doc = "Register `ac_adc_fifoc` reader"]
2pub type R = crate::R<AC_ADC_FIFOC_SPEC>;
3#[doc = "Register `ac_adc_fifoc` writer"]
4pub type W = crate::W<AC_ADC_FIFOC_SPEC>;
5#[doc = "Field `adc_fifo_flush` reader - ADC FIFO Flush\n\nWrite '1' to flush TX FIFO, self clear to '0'."]
6pub type ADC_FIFO_FLUSH_R = crate::BitReader;
7#[doc = "Field `adc_fifo_flush` writer - ADC FIFO Flush\n\nWrite '1' to flush TX FIFO, self clear to '0'."]
8pub type ADC_FIFO_FLUSH_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `adc_overrun_irq_en` reader - ADC FIFO Overrun IRQ Enable"]
10pub type ADC_OVERRUN_IRQ_EN_R = crate::BitReader<ADC_OVERRUN_IRQ_EN_A>;
11#[doc = "ADC FIFO Overrun IRQ Enable\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13pub enum ADC_OVERRUN_IRQ_EN_A {
14    #[doc = "0: Disabled"]
15    DISABLED = 0,
16    #[doc = "1: Enabled"]
17    ENABLED = 1,
18}
19impl From<ADC_OVERRUN_IRQ_EN_A> for bool {
20    #[inline(always)]
21    fn from(variant: ADC_OVERRUN_IRQ_EN_A) -> Self {
22        variant as u8 != 0
23    }
24}
25impl ADC_OVERRUN_IRQ_EN_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> ADC_OVERRUN_IRQ_EN_A {
29        match self.bits {
30            false => ADC_OVERRUN_IRQ_EN_A::DISABLED,
31            true => ADC_OVERRUN_IRQ_EN_A::ENABLED,
32        }
33    }
34    #[doc = "Disabled"]
35    #[inline(always)]
36    pub fn is_disabled(&self) -> bool {
37        *self == ADC_OVERRUN_IRQ_EN_A::DISABLED
38    }
39    #[doc = "Enabled"]
40    #[inline(always)]
41    pub fn is_enabled(&self) -> bool {
42        *self == ADC_OVERRUN_IRQ_EN_A::ENABLED
43    }
44}
45#[doc = "Field `adc_overrun_irq_en` writer - ADC FIFO Overrun IRQ Enable"]
46pub type ADC_OVERRUN_IRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, ADC_OVERRUN_IRQ_EN_A>;
47impl<'a, REG> ADC_OVERRUN_IRQ_EN_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "Disabled"]
52    #[inline(always)]
53    pub fn disabled(self) -> &'a mut crate::W<REG> {
54        self.variant(ADC_OVERRUN_IRQ_EN_A::DISABLED)
55    }
56    #[doc = "Enabled"]
57    #[inline(always)]
58    pub fn enabled(self) -> &'a mut crate::W<REG> {
59        self.variant(ADC_OVERRUN_IRQ_EN_A::ENABLED)
60    }
61}
62#[doc = "Field `adc_irq_en` reader - ADC FIFO Data Available IRQ Enable"]
63pub type ADC_IRQ_EN_R = crate::BitReader<ADC_IRQ_EN_A>;
64#[doc = "ADC FIFO Data Available IRQ Enable\n\nValue on reset: 0"]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum ADC_IRQ_EN_A {
67    #[doc = "0: Disabled"]
68    DISABLED = 0,
69    #[doc = "1: Enabled"]
70    ENABLED = 1,
71}
72impl From<ADC_IRQ_EN_A> for bool {
73    #[inline(always)]
74    fn from(variant: ADC_IRQ_EN_A) -> Self {
75        variant as u8 != 0
76    }
77}
78impl ADC_IRQ_EN_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub const fn variant(&self) -> ADC_IRQ_EN_A {
82        match self.bits {
83            false => ADC_IRQ_EN_A::DISABLED,
84            true => ADC_IRQ_EN_A::ENABLED,
85        }
86    }
87    #[doc = "Disabled"]
88    #[inline(always)]
89    pub fn is_disabled(&self) -> bool {
90        *self == ADC_IRQ_EN_A::DISABLED
91    }
92    #[doc = "Enabled"]
93    #[inline(always)]
94    pub fn is_enabled(&self) -> bool {
95        *self == ADC_IRQ_EN_A::ENABLED
96    }
97}
98#[doc = "Field `adc_irq_en` writer - ADC FIFO Data Available IRQ Enable"]
99pub type ADC_IRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, ADC_IRQ_EN_A>;
100impl<'a, REG> ADC_IRQ_EN_W<'a, REG>
101where
102    REG: crate::Writable + crate::RegisterSpec,
103{
104    #[doc = "Disabled"]
105    #[inline(always)]
106    pub fn disabled(self) -> &'a mut crate::W<REG> {
107        self.variant(ADC_IRQ_EN_A::DISABLED)
108    }
109    #[doc = "Enabled"]
110    #[inline(always)]
111    pub fn enabled(self) -> &'a mut crate::W<REG> {
112        self.variant(ADC_IRQ_EN_A::ENABLED)
113    }
114}
115#[doc = "Field `adc_drq_en` reader - ADC FIFO Data Available DRQ Enable"]
116pub type ADC_DRQ_EN_R = crate::BitReader<ADC_DRQ_EN_A>;
117#[doc = "ADC FIFO Data Available DRQ Enable\n\nValue on reset: 0"]
118#[derive(Clone, Copy, Debug, PartialEq, Eq)]
119pub enum ADC_DRQ_EN_A {
120    #[doc = "0: Disabled"]
121    DISABLED = 0,
122    #[doc = "1: Enabled"]
123    ENABLED = 1,
124}
125impl From<ADC_DRQ_EN_A> for bool {
126    #[inline(always)]
127    fn from(variant: ADC_DRQ_EN_A) -> Self {
128        variant as u8 != 0
129    }
130}
131impl ADC_DRQ_EN_R {
132    #[doc = "Get enumerated values variant"]
133    #[inline(always)]
134    pub const fn variant(&self) -> ADC_DRQ_EN_A {
135        match self.bits {
136            false => ADC_DRQ_EN_A::DISABLED,
137            true => ADC_DRQ_EN_A::ENABLED,
138        }
139    }
140    #[doc = "Disabled"]
141    #[inline(always)]
142    pub fn is_disabled(&self) -> bool {
143        *self == ADC_DRQ_EN_A::DISABLED
144    }
145    #[doc = "Enabled"]
146    #[inline(always)]
147    pub fn is_enabled(&self) -> bool {
148        *self == ADC_DRQ_EN_A::ENABLED
149    }
150}
151#[doc = "Field `adc_drq_en` writer - ADC FIFO Data Available DRQ Enable"]
152pub type ADC_DRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, ADC_DRQ_EN_A>;
153impl<'a, REG> ADC_DRQ_EN_W<'a, REG>
154where
155    REG: crate::Writable + crate::RegisterSpec,
156{
157    #[doc = "Disabled"]
158    #[inline(always)]
159    pub fn disabled(self) -> &'a mut crate::W<REG> {
160        self.variant(ADC_DRQ_EN_A::DISABLED)
161    }
162    #[doc = "Enabled"]
163    #[inline(always)]
164    pub fn enabled(self) -> &'a mut crate::W<REG> {
165        self.variant(ADC_DRQ_EN_A::ENABLED)
166    }
167}
168#[doc = "Field `rx_fifo_trg_level` reader - RX FIFO Trigger Level (RXTL\\[5:0\\])\n\nInterrupt and DMA request trigger level for RX FIFO normal condition IRQ/DRQ generated when WLEVEL > RXTL\\[5:0\\]"]
169pub type RX_FIFO_TRG_LEVEL_R = crate::FieldReader;
170#[doc = "Field `rx_fifo_trg_level` writer - RX FIFO Trigger Level (RXTL\\[5:0\\])\n\nInterrupt and DMA request trigger level for RX FIFO normal condition IRQ/DRQ generated when WLEVEL > RXTL\\[5:0\\]"]
171pub type RX_FIFO_TRG_LEVEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
172#[doc = "Field `rx_sample_bits` reader - Receiving Audio Sample Resolution"]
173pub type RX_SAMPLE_BITS_R = crate::BitReader<RX_SAMPLE_BITS_A>;
174#[doc = "Receiving Audio Sample Resolution\n\nValue on reset: 0"]
175#[derive(Clone, Copy, Debug, PartialEq, Eq)]
176pub enum RX_SAMPLE_BITS_A {
177    #[doc = "0: 16 bits"]
178    _16_BITS = 0,
179    #[doc = "1: 20 bits"]
180    _20_BITS = 1,
181}
182impl From<RX_SAMPLE_BITS_A> for bool {
183    #[inline(always)]
184    fn from(variant: RX_SAMPLE_BITS_A) -> Self {
185        variant as u8 != 0
186    }
187}
188impl RX_SAMPLE_BITS_R {
189    #[doc = "Get enumerated values variant"]
190    #[inline(always)]
191    pub const fn variant(&self) -> RX_SAMPLE_BITS_A {
192        match self.bits {
193            false => RX_SAMPLE_BITS_A::_16_BITS,
194            true => RX_SAMPLE_BITS_A::_20_BITS,
195        }
196    }
197    #[doc = "16 bits"]
198    #[inline(always)]
199    pub fn is_16_bits(&self) -> bool {
200        *self == RX_SAMPLE_BITS_A::_16_BITS
201    }
202    #[doc = "20 bits"]
203    #[inline(always)]
204    pub fn is_20_bits(&self) -> bool {
205        *self == RX_SAMPLE_BITS_A::_20_BITS
206    }
207}
208#[doc = "Field `rx_sample_bits` writer - Receiving Audio Sample Resolution"]
209pub type RX_SAMPLE_BITS_W<'a, REG> = crate::BitWriter<'a, REG, RX_SAMPLE_BITS_A>;
210impl<'a, REG> RX_SAMPLE_BITS_W<'a, REG>
211where
212    REG: crate::Writable + crate::RegisterSpec,
213{
214    #[doc = "16 bits"]
215    #[inline(always)]
216    pub fn _16_bits(self) -> &'a mut crate::W<REG> {
217        self.variant(RX_SAMPLE_BITS_A::_16_BITS)
218    }
219    #[doc = "20 bits"]
220    #[inline(always)]
221    pub fn _20_bits(self) -> &'a mut crate::W<REG> {
222        self.variant(RX_SAMPLE_BITS_A::_20_BITS)
223    }
224}
225#[doc = "Field `rx_sync_en` reader - Audiocodec RX Synchronize Enable"]
226pub type RX_SYNC_EN_R = crate::BitReader<RX_SYNC_EN_A>;
227#[doc = "Audiocodec RX Synchronize Enable\n\nValue on reset: 0"]
228#[derive(Clone, Copy, Debug, PartialEq, Eq)]
229pub enum RX_SYNC_EN_A {
230    #[doc = "0: Disabled"]
231    DISABLED = 0,
232    #[doc = "1: Enabled"]
233    ENABLED = 1,
234}
235impl From<RX_SYNC_EN_A> for bool {
236    #[inline(always)]
237    fn from(variant: RX_SYNC_EN_A) -> Self {
238        variant as u8 != 0
239    }
240}
241impl RX_SYNC_EN_R {
242    #[doc = "Get enumerated values variant"]
243    #[inline(always)]
244    pub const fn variant(&self) -> RX_SYNC_EN_A {
245        match self.bits {
246            false => RX_SYNC_EN_A::DISABLED,
247            true => RX_SYNC_EN_A::ENABLED,
248        }
249    }
250    #[doc = "Disabled"]
251    #[inline(always)]
252    pub fn is_disabled(&self) -> bool {
253        *self == RX_SYNC_EN_A::DISABLED
254    }
255    #[doc = "Enabled"]
256    #[inline(always)]
257    pub fn is_enabled(&self) -> bool {
258        *self == RX_SYNC_EN_A::ENABLED
259    }
260}
261#[doc = "Field `rx_sync_en` writer - Audiocodec RX Synchronize Enable"]
262pub type RX_SYNC_EN_W<'a, REG> = crate::BitWriter<'a, REG, RX_SYNC_EN_A>;
263impl<'a, REG> RX_SYNC_EN_W<'a, REG>
264where
265    REG: crate::Writable + crate::RegisterSpec,
266{
267    #[doc = "Disabled"]
268    #[inline(always)]
269    pub fn disabled(self) -> &'a mut crate::W<REG> {
270        self.variant(RX_SYNC_EN_A::DISABLED)
271    }
272    #[doc = "Enabled"]
273    #[inline(always)]
274    pub fn enabled(self) -> &'a mut crate::W<REG> {
275        self.variant(RX_SYNC_EN_A::ENABLED)
276    }
277}
278#[doc = "Field `rx_sync_en_start` reader - The bit takes effect only when RX_SYNC_EN is set to 1. System Domain: Audio codec/I2S0/I2S1/I2S2/DMIC/OWA RX Synchronize Enable Start."]
279pub type RX_SYNC_EN_START_R = crate::BitReader<RX_SYNC_EN_START_A>;
280#[doc = "The bit takes effect only when RX_SYNC_EN is set to 1. System Domain: Audio codec/I2S0/I2S1/I2S2/DMIC/OWA RX Synchronize Enable Start.\n\nValue on reset: 0"]
281#[derive(Clone, Copy, Debug, PartialEq, Eq)]
282pub enum RX_SYNC_EN_START_A {
283    #[doc = "0: Disabled"]
284    DISABLED = 0,
285    #[doc = "1: Enabled"]
286    ENABLED = 1,
287}
288impl From<RX_SYNC_EN_START_A> for bool {
289    #[inline(always)]
290    fn from(variant: RX_SYNC_EN_START_A) -> Self {
291        variant as u8 != 0
292    }
293}
294impl RX_SYNC_EN_START_R {
295    #[doc = "Get enumerated values variant"]
296    #[inline(always)]
297    pub const fn variant(&self) -> RX_SYNC_EN_START_A {
298        match self.bits {
299            false => RX_SYNC_EN_START_A::DISABLED,
300            true => RX_SYNC_EN_START_A::ENABLED,
301        }
302    }
303    #[doc = "Disabled"]
304    #[inline(always)]
305    pub fn is_disabled(&self) -> bool {
306        *self == RX_SYNC_EN_START_A::DISABLED
307    }
308    #[doc = "Enabled"]
309    #[inline(always)]
310    pub fn is_enabled(&self) -> bool {
311        *self == RX_SYNC_EN_START_A::ENABLED
312    }
313}
314#[doc = "Field `rx_sync_en_start` writer - The bit takes effect only when RX_SYNC_EN is set to 1. System Domain: Audio codec/I2S0/I2S1/I2S2/DMIC/OWA RX Synchronize Enable Start."]
315pub type RX_SYNC_EN_START_W<'a, REG> = crate::BitWriter<'a, REG, RX_SYNC_EN_START_A>;
316impl<'a, REG> RX_SYNC_EN_START_W<'a, REG>
317where
318    REG: crate::Writable + crate::RegisterSpec,
319{
320    #[doc = "Disabled"]
321    #[inline(always)]
322    pub fn disabled(self) -> &'a mut crate::W<REG> {
323        self.variant(RX_SYNC_EN_START_A::DISABLED)
324    }
325    #[doc = "Enabled"]
326    #[inline(always)]
327    pub fn enabled(self) -> &'a mut crate::W<REG> {
328        self.variant(RX_SYNC_EN_START_A::ENABLED)
329    }
330}
331#[doc = "Field `rx_fifo_mode` reader - RX FIFO Output Mode (Mode 0, 1) \n\nFor 20-bit received audio sample:\n\nMode 0: RXDATA\\[31:0\\] = {FIFO_O\\[19:0\\], 12'h0}\n\nMode 1: RXDATA\\[31:0\\] = {12{FIFO_O\\[19\\]}, FIFO_O\\[19:0\\]}\n\nFor 16-bit received audio sample:\n\nMode 0: RXDATA\\[31:0\\] = {FIFO_O\\[19:4\\], 16'h0}\n\nMode 1: RXDATA\\[31:0\\] = {16{FIFO_O\\[19\\]}, FIFO_O\\[19:4\\]}"]
332pub type RX_FIFO_MODE_R = crate::BitReader<RX_FIFO_MODE_A>;
333#[doc = "RX FIFO Output Mode (Mode 0, 1) \n\nFor 20-bit received audio sample:\n\nMode 0: RXDATA\\[31:0\\] = {FIFO_O\\[19:0\\], 12'h0}\n\nMode 1: RXDATA\\[31:0\\] = {12{FIFO_O\\[19\\]}, FIFO_O\\[19:0\\]}\n\nFor 16-bit received audio sample:\n\nMode 0: RXDATA\\[31:0\\] = {FIFO_O\\[19:4\\], 16'h0}\n\nMode 1: RXDATA\\[31:0\\] = {16{FIFO_O\\[19\\]}, FIFO_O\\[19:4\\]}\n\nValue on reset: 0"]
334#[derive(Clone, Copy, Debug, PartialEq, Eq)]
335pub enum RX_FIFO_MODE_A {
336    #[doc = "0: Expanding '0' at LSB of TX FIFO register"]
337    E_XPANDING_ZERO = 0,
338    #[doc = "1: Expanding received sample sign bit at MSB of TX FIFO register"]
339    E_XPANDING_SIGN = 1,
340}
341impl From<RX_FIFO_MODE_A> for bool {
342    #[inline(always)]
343    fn from(variant: RX_FIFO_MODE_A) -> Self {
344        variant as u8 != 0
345    }
346}
347impl RX_FIFO_MODE_R {
348    #[doc = "Get enumerated values variant"]
349    #[inline(always)]
350    pub const fn variant(&self) -> RX_FIFO_MODE_A {
351        match self.bits {
352            false => RX_FIFO_MODE_A::E_XPANDING_ZERO,
353            true => RX_FIFO_MODE_A::E_XPANDING_SIGN,
354        }
355    }
356    #[doc = "Expanding '0' at LSB of TX FIFO register"]
357    #[inline(always)]
358    pub fn is_e_xpanding_zero(&self) -> bool {
359        *self == RX_FIFO_MODE_A::E_XPANDING_ZERO
360    }
361    #[doc = "Expanding received sample sign bit at MSB of TX FIFO register"]
362    #[inline(always)]
363    pub fn is_e_xpanding_sign(&self) -> bool {
364        *self == RX_FIFO_MODE_A::E_XPANDING_SIGN
365    }
366}
367#[doc = "Field `rx_fifo_mode` writer - RX FIFO Output Mode (Mode 0, 1) \n\nFor 20-bit received audio sample:\n\nMode 0: RXDATA\\[31:0\\] = {FIFO_O\\[19:0\\], 12'h0}\n\nMode 1: RXDATA\\[31:0\\] = {12{FIFO_O\\[19\\]}, FIFO_O\\[19:0\\]}\n\nFor 16-bit received audio sample:\n\nMode 0: RXDATA\\[31:0\\] = {FIFO_O\\[19:4\\], 16'h0}\n\nMode 1: RXDATA\\[31:0\\] = {16{FIFO_O\\[19\\]}, FIFO_O\\[19:4\\]}"]
368pub type RX_FIFO_MODE_W<'a, REG> = crate::BitWriter<'a, REG, RX_FIFO_MODE_A>;
369impl<'a, REG> RX_FIFO_MODE_W<'a, REG>
370where
371    REG: crate::Writable + crate::RegisterSpec,
372{
373    #[doc = "Expanding '0' at LSB of TX FIFO register"]
374    #[inline(always)]
375    pub fn e_xpanding_zero(self) -> &'a mut crate::W<REG> {
376        self.variant(RX_FIFO_MODE_A::E_XPANDING_ZERO)
377    }
378    #[doc = "Expanding received sample sign bit at MSB of TX FIFO register"]
379    #[inline(always)]
380    pub fn e_xpanding_sign(self) -> &'a mut crate::W<REG> {
381        self.variant(RX_FIFO_MODE_A::E_XPANDING_SIGN)
382    }
383}
384#[doc = "Field `adcdfen` reader - ADC FIFO delay function for writing data after EN_AD"]
385pub type ADCDFEN_R = crate::BitReader<ADCDFEN_A>;
386#[doc = "ADC FIFO delay function for writing data after EN_AD\n\nValue on reset: 0"]
387#[derive(Clone, Copy, Debug, PartialEq, Eq)]
388pub enum ADCDFEN_A {
389    #[doc = "0: Disabled"]
390    DISABLED = 0,
391    #[doc = "1: Enabled"]
392    ENABLED = 1,
393}
394impl From<ADCDFEN_A> for bool {
395    #[inline(always)]
396    fn from(variant: ADCDFEN_A) -> Self {
397        variant as u8 != 0
398    }
399}
400impl ADCDFEN_R {
401    #[doc = "Get enumerated values variant"]
402    #[inline(always)]
403    pub const fn variant(&self) -> ADCDFEN_A {
404        match self.bits {
405            false => ADCDFEN_A::DISABLED,
406            true => ADCDFEN_A::ENABLED,
407        }
408    }
409    #[doc = "Disabled"]
410    #[inline(always)]
411    pub fn is_disabled(&self) -> bool {
412        *self == ADCDFEN_A::DISABLED
413    }
414    #[doc = "Enabled"]
415    #[inline(always)]
416    pub fn is_enabled(&self) -> bool {
417        *self == ADCDFEN_A::ENABLED
418    }
419}
420#[doc = "Field `adcdfen` writer - ADC FIFO delay function for writing data after EN_AD"]
421pub type ADCDFEN_W<'a, REG> = crate::BitWriter<'a, REG, ADCDFEN_A>;
422impl<'a, REG> ADCDFEN_W<'a, REG>
423where
424    REG: crate::Writable + crate::RegisterSpec,
425{
426    #[doc = "Disabled"]
427    #[inline(always)]
428    pub fn disabled(self) -> &'a mut crate::W<REG> {
429        self.variant(ADCDFEN_A::DISABLED)
430    }
431    #[doc = "Enabled"]
432    #[inline(always)]
433    pub fn enabled(self) -> &'a mut crate::W<REG> {
434        self.variant(ADCDFEN_A::ENABLED)
435    }
436}
437#[doc = "Field `adcfdt` reader - ADC FIFO delay time for writing data after EN_AD"]
438pub type ADCFDT_R = crate::FieldReader<ADCFDT_A>;
439#[doc = "ADC FIFO delay time for writing data after EN_AD\n\nValue on reset: 0"]
440#[derive(Clone, Copy, Debug, PartialEq, Eq)]
441#[repr(u8)]
442pub enum ADCFDT_A {
443    #[doc = "0: 5 ms"]
444    _5_MS = 0,
445    #[doc = "1: 10 ms"]
446    _10_MS = 1,
447    #[doc = "2: 20 ms"]
448    _20_MS = 2,
449    #[doc = "3: 30 ms"]
450    _30_MS = 3,
451}
452impl From<ADCFDT_A> for u8 {
453    #[inline(always)]
454    fn from(variant: ADCFDT_A) -> Self {
455        variant as _
456    }
457}
458impl crate::FieldSpec for ADCFDT_A {
459    type Ux = u8;
460}
461impl ADCFDT_R {
462    #[doc = "Get enumerated values variant"]
463    #[inline(always)]
464    pub const fn variant(&self) -> ADCFDT_A {
465        match self.bits {
466            0 => ADCFDT_A::_5_MS,
467            1 => ADCFDT_A::_10_MS,
468            2 => ADCFDT_A::_20_MS,
469            3 => ADCFDT_A::_30_MS,
470            _ => unreachable!(),
471        }
472    }
473    #[doc = "5 ms"]
474    #[inline(always)]
475    pub fn is_5_ms(&self) -> bool {
476        *self == ADCFDT_A::_5_MS
477    }
478    #[doc = "10 ms"]
479    #[inline(always)]
480    pub fn is_10_ms(&self) -> bool {
481        *self == ADCFDT_A::_10_MS
482    }
483    #[doc = "20 ms"]
484    #[inline(always)]
485    pub fn is_20_ms(&self) -> bool {
486        *self == ADCFDT_A::_20_MS
487    }
488    #[doc = "30 ms"]
489    #[inline(always)]
490    pub fn is_30_ms(&self) -> bool {
491        *self == ADCFDT_A::_30_MS
492    }
493}
494#[doc = "Field `adcfdt` writer - ADC FIFO delay time for writing data after EN_AD"]
495pub type ADCFDT_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, ADCFDT_A>;
496impl<'a, REG> ADCFDT_W<'a, REG>
497where
498    REG: crate::Writable + crate::RegisterSpec,
499    REG::Ux: From<u8>,
500{
501    #[doc = "5 ms"]
502    #[inline(always)]
503    pub fn _5_ms(self) -> &'a mut crate::W<REG> {
504        self.variant(ADCFDT_A::_5_MS)
505    }
506    #[doc = "10 ms"]
507    #[inline(always)]
508    pub fn _10_ms(self) -> &'a mut crate::W<REG> {
509        self.variant(ADCFDT_A::_10_MS)
510    }
511    #[doc = "20 ms"]
512    #[inline(always)]
513    pub fn _20_ms(self) -> &'a mut crate::W<REG> {
514        self.variant(ADCFDT_A::_20_MS)
515    }
516    #[doc = "30 ms"]
517    #[inline(always)]
518    pub fn _30_ms(self) -> &'a mut crate::W<REG> {
519        self.variant(ADCFDT_A::_30_MS)
520    }
521}
522#[doc = "Field `en_ad` reader - ADC Digital Part Enable"]
523pub type EN_AD_R = crate::BitReader<EN_AD_A>;
524#[doc = "ADC Digital Part Enable\n\nValue on reset: 0"]
525#[derive(Clone, Copy, Debug, PartialEq, Eq)]
526pub enum EN_AD_A {
527    #[doc = "0: Disabled"]
528    DISABLED = 0,
529    #[doc = "1: Enabled"]
530    ENABLED = 1,
531}
532impl From<EN_AD_A> for bool {
533    #[inline(always)]
534    fn from(variant: EN_AD_A) -> Self {
535        variant as u8 != 0
536    }
537}
538impl EN_AD_R {
539    #[doc = "Get enumerated values variant"]
540    #[inline(always)]
541    pub const fn variant(&self) -> EN_AD_A {
542        match self.bits {
543            false => EN_AD_A::DISABLED,
544            true => EN_AD_A::ENABLED,
545        }
546    }
547    #[doc = "Disabled"]
548    #[inline(always)]
549    pub fn is_disabled(&self) -> bool {
550        *self == EN_AD_A::DISABLED
551    }
552    #[doc = "Enabled"]
553    #[inline(always)]
554    pub fn is_enabled(&self) -> bool {
555        *self == EN_AD_A::ENABLED
556    }
557}
558#[doc = "Field `en_ad` writer - ADC Digital Part Enable"]
559pub type EN_AD_W<'a, REG> = crate::BitWriter<'a, REG, EN_AD_A>;
560impl<'a, REG> EN_AD_W<'a, REG>
561where
562    REG: crate::Writable + crate::RegisterSpec,
563{
564    #[doc = "Disabled"]
565    #[inline(always)]
566    pub fn disabled(self) -> &'a mut crate::W<REG> {
567        self.variant(EN_AD_A::DISABLED)
568    }
569    #[doc = "Enabled"]
570    #[inline(always)]
571    pub fn enabled(self) -> &'a mut crate::W<REG> {
572        self.variant(EN_AD_A::ENABLED)
573    }
574}
575#[doc = "Field `adfs` reader - Sample Rate of ADC \n\n44.1 kHz/22.05 kHz/11.025 kHz can be supported by Audio PLL Configure Bit."]
576pub type ADFS_R = crate::FieldReader<ADFS_A>;
577#[doc = "Sample Rate of ADC \n\n44.1 kHz/22.05 kHz/11.025 kHz can be supported by Audio PLL Configure Bit.\n\nValue on reset: 0"]
578#[derive(Clone, Copy, Debug, PartialEq, Eq)]
579#[repr(u8)]
580pub enum ADFS_A {
581    #[doc = "0: 48 kHz"]
582    _48KHZ = 0,
583    #[doc = "2: 24 kHz"]
584    _24KHZ = 2,
585    #[doc = "4: 12 kHz"]
586    _12KHZ = 4,
587    #[doc = "1: 32 kHz"]
588    _32KHZ = 1,
589    #[doc = "3: 16 kHz"]
590    _16KHZ = 3,
591    #[doc = "5: 8 kHz"]
592    _8KHZ = 5,
593    #[doc = "7: Reserved"]
594    R_ESERVED = 7,
595}
596impl From<ADFS_A> for u8 {
597    #[inline(always)]
598    fn from(variant: ADFS_A) -> Self {
599        variant as _
600    }
601}
602impl crate::FieldSpec for ADFS_A {
603    type Ux = u8;
604}
605impl ADFS_R {
606    #[doc = "Get enumerated values variant"]
607    #[inline(always)]
608    pub const fn variant(&self) -> Option<ADFS_A> {
609        match self.bits {
610            0 => Some(ADFS_A::_48KHZ),
611            2 => Some(ADFS_A::_24KHZ),
612            4 => Some(ADFS_A::_12KHZ),
613            1 => Some(ADFS_A::_32KHZ),
614            3 => Some(ADFS_A::_16KHZ),
615            5 => Some(ADFS_A::_8KHZ),
616            7 => Some(ADFS_A::R_ESERVED),
617            _ => None,
618        }
619    }
620    #[doc = "48 kHz"]
621    #[inline(always)]
622    pub fn is_48khz(&self) -> bool {
623        *self == ADFS_A::_48KHZ
624    }
625    #[doc = "24 kHz"]
626    #[inline(always)]
627    pub fn is_24khz(&self) -> bool {
628        *self == ADFS_A::_24KHZ
629    }
630    #[doc = "12 kHz"]
631    #[inline(always)]
632    pub fn is_12khz(&self) -> bool {
633        *self == ADFS_A::_12KHZ
634    }
635    #[doc = "32 kHz"]
636    #[inline(always)]
637    pub fn is_32khz(&self) -> bool {
638        *self == ADFS_A::_32KHZ
639    }
640    #[doc = "16 kHz"]
641    #[inline(always)]
642    pub fn is_16khz(&self) -> bool {
643        *self == ADFS_A::_16KHZ
644    }
645    #[doc = "8 kHz"]
646    #[inline(always)]
647    pub fn is_8khz(&self) -> bool {
648        *self == ADFS_A::_8KHZ
649    }
650    #[doc = "Reserved"]
651    #[inline(always)]
652    pub fn is_r_eserved(&self) -> bool {
653        *self == ADFS_A::R_ESERVED
654    }
655}
656#[doc = "Field `adfs` writer - Sample Rate of ADC \n\n44.1 kHz/22.05 kHz/11.025 kHz can be supported by Audio PLL Configure Bit."]
657pub type ADFS_W<'a, REG> = crate::FieldWriter<'a, REG, 3, ADFS_A>;
658impl<'a, REG> ADFS_W<'a, REG>
659where
660    REG: crate::Writable + crate::RegisterSpec,
661    REG::Ux: From<u8>,
662{
663    #[doc = "48 kHz"]
664    #[inline(always)]
665    pub fn _48khz(self) -> &'a mut crate::W<REG> {
666        self.variant(ADFS_A::_48KHZ)
667    }
668    #[doc = "24 kHz"]
669    #[inline(always)]
670    pub fn _24khz(self) -> &'a mut crate::W<REG> {
671        self.variant(ADFS_A::_24KHZ)
672    }
673    #[doc = "12 kHz"]
674    #[inline(always)]
675    pub fn _12khz(self) -> &'a mut crate::W<REG> {
676        self.variant(ADFS_A::_12KHZ)
677    }
678    #[doc = "32 kHz"]
679    #[inline(always)]
680    pub fn _32khz(self) -> &'a mut crate::W<REG> {
681        self.variant(ADFS_A::_32KHZ)
682    }
683    #[doc = "16 kHz"]
684    #[inline(always)]
685    pub fn _16khz(self) -> &'a mut crate::W<REG> {
686        self.variant(ADFS_A::_16KHZ)
687    }
688    #[doc = "8 kHz"]
689    #[inline(always)]
690    pub fn _8khz(self) -> &'a mut crate::W<REG> {
691        self.variant(ADFS_A::_8KHZ)
692    }
693    #[doc = "Reserved"]
694    #[inline(always)]
695    pub fn r_eserved(self) -> &'a mut crate::W<REG> {
696        self.variant(ADFS_A::R_ESERVED)
697    }
698}
699impl R {
700    #[doc = "Bit 0 - ADC FIFO Flush\n\nWrite '1' to flush TX FIFO, self clear to '0'."]
701    #[inline(always)]
702    pub fn adc_fifo_flush(&self) -> ADC_FIFO_FLUSH_R {
703        ADC_FIFO_FLUSH_R::new((self.bits & 1) != 0)
704    }
705    #[doc = "Bit 1 - ADC FIFO Overrun IRQ Enable"]
706    #[inline(always)]
707    pub fn adc_overrun_irq_en(&self) -> ADC_OVERRUN_IRQ_EN_R {
708        ADC_OVERRUN_IRQ_EN_R::new(((self.bits >> 1) & 1) != 0)
709    }
710    #[doc = "Bit 2 - ADC FIFO Data Available IRQ Enable"]
711    #[inline(always)]
712    pub fn adc_irq_en(&self) -> ADC_IRQ_EN_R {
713        ADC_IRQ_EN_R::new(((self.bits >> 2) & 1) != 0)
714    }
715    #[doc = "Bit 3 - ADC FIFO Data Available DRQ Enable"]
716    #[inline(always)]
717    pub fn adc_drq_en(&self) -> ADC_DRQ_EN_R {
718        ADC_DRQ_EN_R::new(((self.bits >> 3) & 1) != 0)
719    }
720    #[doc = "Bits 4:11 - RX FIFO Trigger Level (RXTL\\[5:0\\])\n\nInterrupt and DMA request trigger level for RX FIFO normal condition IRQ/DRQ generated when WLEVEL > RXTL\\[5:0\\]"]
721    #[inline(always)]
722    pub fn rx_fifo_trg_level(&self) -> RX_FIFO_TRG_LEVEL_R {
723        RX_FIFO_TRG_LEVEL_R::new(((self.bits >> 4) & 0xff) as u8)
724    }
725    #[doc = "Bit 16 - Receiving Audio Sample Resolution"]
726    #[inline(always)]
727    pub fn rx_sample_bits(&self) -> RX_SAMPLE_BITS_R {
728        RX_SAMPLE_BITS_R::new(((self.bits >> 16) & 1) != 0)
729    }
730    #[doc = "Bit 20 - Audiocodec RX Synchronize Enable"]
731    #[inline(always)]
732    pub fn rx_sync_en(&self) -> RX_SYNC_EN_R {
733        RX_SYNC_EN_R::new(((self.bits >> 20) & 1) != 0)
734    }
735    #[doc = "Bit 21 - The bit takes effect only when RX_SYNC_EN is set to 1. System Domain: Audio codec/I2S0/I2S1/I2S2/DMIC/OWA RX Synchronize Enable Start."]
736    #[inline(always)]
737    pub fn rx_sync_en_start(&self) -> RX_SYNC_EN_START_R {
738        RX_SYNC_EN_START_R::new(((self.bits >> 21) & 1) != 0)
739    }
740    #[doc = "Bit 24 - RX FIFO Output Mode (Mode 0, 1) \n\nFor 20-bit received audio sample:\n\nMode 0: RXDATA\\[31:0\\] = {FIFO_O\\[19:0\\], 12'h0}\n\nMode 1: RXDATA\\[31:0\\] = {12{FIFO_O\\[19\\]}, FIFO_O\\[19:0\\]}\n\nFor 16-bit received audio sample:\n\nMode 0: RXDATA\\[31:0\\] = {FIFO_O\\[19:4\\], 16'h0}\n\nMode 1: RXDATA\\[31:0\\] = {16{FIFO_O\\[19\\]}, FIFO_O\\[19:4\\]}"]
741    #[inline(always)]
742    pub fn rx_fifo_mode(&self) -> RX_FIFO_MODE_R {
743        RX_FIFO_MODE_R::new(((self.bits >> 24) & 1) != 0)
744    }
745    #[doc = "Bit 25 - ADC FIFO delay function for writing data after EN_AD"]
746    #[inline(always)]
747    pub fn adcdfen(&self) -> ADCDFEN_R {
748        ADCDFEN_R::new(((self.bits >> 25) & 1) != 0)
749    }
750    #[doc = "Bits 26:27 - ADC FIFO delay time for writing data after EN_AD"]
751    #[inline(always)]
752    pub fn adcfdt(&self) -> ADCFDT_R {
753        ADCFDT_R::new(((self.bits >> 26) & 3) as u8)
754    }
755    #[doc = "Bit 28 - ADC Digital Part Enable"]
756    #[inline(always)]
757    pub fn en_ad(&self) -> EN_AD_R {
758        EN_AD_R::new(((self.bits >> 28) & 1) != 0)
759    }
760    #[doc = "Bits 29:31 - Sample Rate of ADC \n\n44.1 kHz/22.05 kHz/11.025 kHz can be supported by Audio PLL Configure Bit."]
761    #[inline(always)]
762    pub fn adfs(&self) -> ADFS_R {
763        ADFS_R::new(((self.bits >> 29) & 7) as u8)
764    }
765}
766impl W {
767    #[doc = "Bit 0 - ADC FIFO Flush\n\nWrite '1' to flush TX FIFO, self clear to '0'."]
768    #[inline(always)]
769    #[must_use]
770    pub fn adc_fifo_flush(&mut self) -> ADC_FIFO_FLUSH_W<AC_ADC_FIFOC_SPEC> {
771        ADC_FIFO_FLUSH_W::new(self, 0)
772    }
773    #[doc = "Bit 1 - ADC FIFO Overrun IRQ Enable"]
774    #[inline(always)]
775    #[must_use]
776    pub fn adc_overrun_irq_en(&mut self) -> ADC_OVERRUN_IRQ_EN_W<AC_ADC_FIFOC_SPEC> {
777        ADC_OVERRUN_IRQ_EN_W::new(self, 1)
778    }
779    #[doc = "Bit 2 - ADC FIFO Data Available IRQ Enable"]
780    #[inline(always)]
781    #[must_use]
782    pub fn adc_irq_en(&mut self) -> ADC_IRQ_EN_W<AC_ADC_FIFOC_SPEC> {
783        ADC_IRQ_EN_W::new(self, 2)
784    }
785    #[doc = "Bit 3 - ADC FIFO Data Available DRQ Enable"]
786    #[inline(always)]
787    #[must_use]
788    pub fn adc_drq_en(&mut self) -> ADC_DRQ_EN_W<AC_ADC_FIFOC_SPEC> {
789        ADC_DRQ_EN_W::new(self, 3)
790    }
791    #[doc = "Bits 4:11 - RX FIFO Trigger Level (RXTL\\[5:0\\])\n\nInterrupt and DMA request trigger level for RX FIFO normal condition IRQ/DRQ generated when WLEVEL > RXTL\\[5:0\\]"]
792    #[inline(always)]
793    #[must_use]
794    pub fn rx_fifo_trg_level(&mut self) -> RX_FIFO_TRG_LEVEL_W<AC_ADC_FIFOC_SPEC> {
795        RX_FIFO_TRG_LEVEL_W::new(self, 4)
796    }
797    #[doc = "Bit 16 - Receiving Audio Sample Resolution"]
798    #[inline(always)]
799    #[must_use]
800    pub fn rx_sample_bits(&mut self) -> RX_SAMPLE_BITS_W<AC_ADC_FIFOC_SPEC> {
801        RX_SAMPLE_BITS_W::new(self, 16)
802    }
803    #[doc = "Bit 20 - Audiocodec RX Synchronize Enable"]
804    #[inline(always)]
805    #[must_use]
806    pub fn rx_sync_en(&mut self) -> RX_SYNC_EN_W<AC_ADC_FIFOC_SPEC> {
807        RX_SYNC_EN_W::new(self, 20)
808    }
809    #[doc = "Bit 21 - The bit takes effect only when RX_SYNC_EN is set to 1. System Domain: Audio codec/I2S0/I2S1/I2S2/DMIC/OWA RX Synchronize Enable Start."]
810    #[inline(always)]
811    #[must_use]
812    pub fn rx_sync_en_start(&mut self) -> RX_SYNC_EN_START_W<AC_ADC_FIFOC_SPEC> {
813        RX_SYNC_EN_START_W::new(self, 21)
814    }
815    #[doc = "Bit 24 - RX FIFO Output Mode (Mode 0, 1) \n\nFor 20-bit received audio sample:\n\nMode 0: RXDATA\\[31:0\\] = {FIFO_O\\[19:0\\], 12'h0}\n\nMode 1: RXDATA\\[31:0\\] = {12{FIFO_O\\[19\\]}, FIFO_O\\[19:0\\]}\n\nFor 16-bit received audio sample:\n\nMode 0: RXDATA\\[31:0\\] = {FIFO_O\\[19:4\\], 16'h0}\n\nMode 1: RXDATA\\[31:0\\] = {16{FIFO_O\\[19\\]}, FIFO_O\\[19:4\\]}"]
816    #[inline(always)]
817    #[must_use]
818    pub fn rx_fifo_mode(&mut self) -> RX_FIFO_MODE_W<AC_ADC_FIFOC_SPEC> {
819        RX_FIFO_MODE_W::new(self, 24)
820    }
821    #[doc = "Bit 25 - ADC FIFO delay function for writing data after EN_AD"]
822    #[inline(always)]
823    #[must_use]
824    pub fn adcdfen(&mut self) -> ADCDFEN_W<AC_ADC_FIFOC_SPEC> {
825        ADCDFEN_W::new(self, 25)
826    }
827    #[doc = "Bits 26:27 - ADC FIFO delay time for writing data after EN_AD"]
828    #[inline(always)]
829    #[must_use]
830    pub fn adcfdt(&mut self) -> ADCFDT_W<AC_ADC_FIFOC_SPEC> {
831        ADCFDT_W::new(self, 26)
832    }
833    #[doc = "Bit 28 - ADC Digital Part Enable"]
834    #[inline(always)]
835    #[must_use]
836    pub fn en_ad(&mut self) -> EN_AD_W<AC_ADC_FIFOC_SPEC> {
837        EN_AD_W::new(self, 28)
838    }
839    #[doc = "Bits 29:31 - Sample Rate of ADC \n\n44.1 kHz/22.05 kHz/11.025 kHz can be supported by Audio PLL Configure Bit."]
840    #[inline(always)]
841    #[must_use]
842    pub fn adfs(&mut self) -> ADFS_W<AC_ADC_FIFOC_SPEC> {
843        ADFS_W::new(self, 29)
844    }
845    #[doc = r" Writes raw bits to the register."]
846    #[doc = r""]
847    #[doc = r" # Safety"]
848    #[doc = r""]
849    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
850    #[inline(always)]
851    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
852        self.bits = bits;
853        self
854    }
855}
856#[doc = "ADC FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ac_adc_fifoc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ac_adc_fifoc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
857pub struct AC_ADC_FIFOC_SPEC;
858impl crate::RegisterSpec for AC_ADC_FIFOC_SPEC {
859    type Ux = u32;
860}
861#[doc = "`read()` method returns [`ac_adc_fifoc::R`](R) reader structure"]
862impl crate::Readable for AC_ADC_FIFOC_SPEC {}
863#[doc = "`write(|w| ..)` method takes [`ac_adc_fifoc::W`](W) writer structure"]
864impl crate::Writable for AC_ADC_FIFOC_SPEC {
865    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
866    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
867}
868#[doc = "`reset()` method sets ac_adc_fifoc to value 0x0400"]
869impl crate::Resettable for AC_ADC_FIFOC_SPEC {
870    const RESET_VALUE: Self::Ux = 0x0400;
871}
d1_pac/audio_codec/ac_adc_fifoc.rs

d1_pac/audio_codec/
ac_adc_fifoc.rs
