d1_pac/audio_codec/
ac_adc_drc_hkl.rs

1#[doc = "Register `ac_adc_drc_hkl` reader"]
2pub type R = crate::R<AC_ADC_DRC_HKL_SPEC>;
3#[doc = "Register `ac_adc_drc_hkl` writer"]
4pub type W = crate::W<AC_ADC_DRC_HKL_SPEC>;
5#[doc = "Field `adc_drc_hkl` reader - The slope of the limiter, which is determined by the equation that Kl = 1/R. R is the ratio of the limiter, which is always an integer. The format is 8.24. (The default value is &lt;50:1>)"]
6pub type ADC_DRC_HKL_R = crate::FieldReader<u16>;
7#[doc = "Field `adc_drc_hkl` writer - The slope of the limiter, which is determined by the equation that Kl = 1/R. R is the ratio of the limiter, which is always an integer. The format is 8.24. (The default value is &lt;50:1>)"]
8pub type ADC_DRC_HKL_W<'a, REG> = crate::FieldWriter<'a, REG, 14, u16>;
9impl R {
10    #[doc = "Bits 0:13 - The slope of the limiter, which is determined by the equation that Kl = 1/R. R is the ratio of the limiter, which is always an integer. The format is 8.24. (The default value is &lt;50:1>)"]
11    #[inline(always)]
12    pub fn adc_drc_hkl(&self) -> ADC_DRC_HKL_R {
13        ADC_DRC_HKL_R::new((self.bits & 0x3fff) as u16)
14    }
15}
16impl W {
17    #[doc = "Bits 0:13 - The slope of the limiter, which is determined by the equation that Kl = 1/R. R is the ratio of the limiter, which is always an integer. The format is 8.24. (The default value is &lt;50:1>)"]
18    #[inline(always)]
19    #[must_use]
20    pub fn adc_drc_hkl(&mut self) -> ADC_DRC_HKL_W<AC_ADC_DRC_HKL_SPEC> {
21        ADC_DRC_HKL_W::new(self, 0)
22    }
23    #[doc = r" Writes raw bits to the register."]
24    #[doc = r""]
25    #[doc = r" # Safety"]
26    #[doc = r""]
27    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
28    #[inline(always)]
29    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
30        self.bits = bits;
31        self
32    }
33}
34#[doc = "ADC DRC Limiter Slope High Setting Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ac_adc_drc_hkl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ac_adc_drc_hkl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
35pub struct AC_ADC_DRC_HKL_SPEC;
36impl crate::RegisterSpec for AC_ADC_DRC_HKL_SPEC {
37    type Ux = u32;
38}
39#[doc = "`read()` method returns [`ac_adc_drc_hkl::R`](R) reader structure"]
40impl crate::Readable for AC_ADC_DRC_HKL_SPEC {}
41#[doc = "`write(|w| ..)` method takes [`ac_adc_drc_hkl::W`](W) writer structure"]
42impl crate::Writable for AC_ADC_DRC_HKL_SPEC {
43    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
44    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
45}
46#[doc = "`reset()` method sets ac_adc_drc_hkl to value 0x05"]
47impl crate::Resettable for AC_ADC_DRC_HKL_SPEC {
48    const RESET_VALUE: Self::Ux = 0x05;
49}
d1_pac/audio_codec/ac_adc_drc_hkl.rs

d1_pac/audio_codec/
ac_adc_drc_hkl.rs
