d1_pac/gpio/
pe_cfg0.rs

1#[doc = "Register `pe_cfg0` reader"]
2pub type R = crate::R<PE_CFG0_SPEC>;
3#[doc = "Register `pe_cfg0` writer"]
4pub type W = crate::W<PE_CFG0_SPEC>;
5#[doc = "Field `pe0_select` reader - PE0 Select"]
6pub type PE0_SELECT_R = crate::FieldReader<PE0_SELECT_A>;
7#[doc = "PE0 Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum PE0_SELECT_A {
11    #[doc = "0: `0`"]
12    INPUT = 0,
13    #[doc = "2: `10`"]
14    NCSI0_HSYNC = 2,
15    #[doc = "4: `100`"]
16    TWI1_SCK = 4,
17    #[doc = "8: `1000`"]
18    RGMII_RXCTRL_RMII_CRS_DV = 8,
19    #[doc = "14: `1110`"]
20    PE_EINT0 = 14,
21    #[doc = "1: `1`"]
22    OUTPUT = 1,
23    #[doc = "3: `11`"]
24    UART2_RTS = 3,
25    #[doc = "5: `101`"]
26    LCD0_HSYNC = 5,
27    #[doc = "15: `1111`"]
28    IO_DISABLE = 15,
29}
30impl From<PE0_SELECT_A> for u8 {
31    #[inline(always)]
32    fn from(variant: PE0_SELECT_A) -> Self {
33        variant as _
34    }
35}
36impl crate::FieldSpec for PE0_SELECT_A {
37    type Ux = u8;
38}
39impl PE0_SELECT_R {
40    #[doc = "Get enumerated values variant"]
41    #[inline(always)]
42    pub const fn variant(&self) -> Option<PE0_SELECT_A> {
43        match self.bits {
44            0 => Some(PE0_SELECT_A::INPUT),
45            2 => Some(PE0_SELECT_A::NCSI0_HSYNC),
46            4 => Some(PE0_SELECT_A::TWI1_SCK),
47            8 => Some(PE0_SELECT_A::RGMII_RXCTRL_RMII_CRS_DV),
48            14 => Some(PE0_SELECT_A::PE_EINT0),
49            1 => Some(PE0_SELECT_A::OUTPUT),
50            3 => Some(PE0_SELECT_A::UART2_RTS),
51            5 => Some(PE0_SELECT_A::LCD0_HSYNC),
52            15 => Some(PE0_SELECT_A::IO_DISABLE),
53            _ => None,
54        }
55    }
56    #[doc = "`0`"]
57    #[inline(always)]
58    pub fn is_input(&self) -> bool {
59        *self == PE0_SELECT_A::INPUT
60    }
61    #[doc = "`10`"]
62    #[inline(always)]
63    pub fn is_ncsi0_hsync(&self) -> bool {
64        *self == PE0_SELECT_A::NCSI0_HSYNC
65    }
66    #[doc = "`100`"]
67    #[inline(always)]
68    pub fn is_twi1_sck(&self) -> bool {
69        *self == PE0_SELECT_A::TWI1_SCK
70    }
71    #[doc = "`1000`"]
72    #[inline(always)]
73    pub fn is_rgmii_rxctrl_rmii_crs_dv(&self) -> bool {
74        *self == PE0_SELECT_A::RGMII_RXCTRL_RMII_CRS_DV
75    }
76    #[doc = "`1110`"]
77    #[inline(always)]
78    pub fn is_pe_eint0(&self) -> bool {
79        *self == PE0_SELECT_A::PE_EINT0
80    }
81    #[doc = "`1`"]
82    #[inline(always)]
83    pub fn is_output(&self) -> bool {
84        *self == PE0_SELECT_A::OUTPUT
85    }
86    #[doc = "`11`"]
87    #[inline(always)]
88    pub fn is_uart2_rts(&self) -> bool {
89        *self == PE0_SELECT_A::UART2_RTS
90    }
91    #[doc = "`101`"]
92    #[inline(always)]
93    pub fn is_lcd0_hsync(&self) -> bool {
94        *self == PE0_SELECT_A::LCD0_HSYNC
95    }
96    #[doc = "`1111`"]
97    #[inline(always)]
98    pub fn is_io_disable(&self) -> bool {
99        *self == PE0_SELECT_A::IO_DISABLE
100    }
101}
102#[doc = "Field `pe0_select` writer - PE0 Select"]
103pub type PE0_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PE0_SELECT_A>;
104impl<'a, REG> PE0_SELECT_W<'a, REG>
105where
106    REG: crate::Writable + crate::RegisterSpec,
107    REG::Ux: From<u8>,
108{
109    #[doc = "`0`"]
110    #[inline(always)]
111    pub fn input(self) -> &'a mut crate::W<REG> {
112        self.variant(PE0_SELECT_A::INPUT)
113    }
114    #[doc = "`10`"]
115    #[inline(always)]
116    pub fn ncsi0_hsync(self) -> &'a mut crate::W<REG> {
117        self.variant(PE0_SELECT_A::NCSI0_HSYNC)
118    }
119    #[doc = "`100`"]
120    #[inline(always)]
121    pub fn twi1_sck(self) -> &'a mut crate::W<REG> {
122        self.variant(PE0_SELECT_A::TWI1_SCK)
123    }
124    #[doc = "`1000`"]
125    #[inline(always)]
126    pub fn rgmii_rxctrl_rmii_crs_dv(self) -> &'a mut crate::W<REG> {
127        self.variant(PE0_SELECT_A::RGMII_RXCTRL_RMII_CRS_DV)
128    }
129    #[doc = "`1110`"]
130    #[inline(always)]
131    pub fn pe_eint0(self) -> &'a mut crate::W<REG> {
132        self.variant(PE0_SELECT_A::PE_EINT0)
133    }
134    #[doc = "`1`"]
135    #[inline(always)]
136    pub fn output(self) -> &'a mut crate::W<REG> {
137        self.variant(PE0_SELECT_A::OUTPUT)
138    }
139    #[doc = "`11`"]
140    #[inline(always)]
141    pub fn uart2_rts(self) -> &'a mut crate::W<REG> {
142        self.variant(PE0_SELECT_A::UART2_RTS)
143    }
144    #[doc = "`101`"]
145    #[inline(always)]
146    pub fn lcd0_hsync(self) -> &'a mut crate::W<REG> {
147        self.variant(PE0_SELECT_A::LCD0_HSYNC)
148    }
149    #[doc = "`1111`"]
150    #[inline(always)]
151    pub fn io_disable(self) -> &'a mut crate::W<REG> {
152        self.variant(PE0_SELECT_A::IO_DISABLE)
153    }
154}
155#[doc = "Field `pe1_select` reader - PE1 Select"]
156pub type PE1_SELECT_R = crate::FieldReader<PE1_SELECT_A>;
157#[doc = "PE1 Select\n\nValue on reset: 0"]
158#[derive(Clone, Copy, Debug, PartialEq, Eq)]
159#[repr(u8)]
160pub enum PE1_SELECT_A {
161    #[doc = "0: `0`"]
162    INPUT = 0,
163    #[doc = "2: `10`"]
164    NCSI0_VSYNC = 2,
165    #[doc = "4: `100`"]
166    TWI1_SDA = 4,
167    #[doc = "8: `1000`"]
168    RGMII_RXD0_RMII_RXD0 = 8,
169    #[doc = "14: `1110`"]
170    PE_EINT1 = 14,
171    #[doc = "1: `1`"]
172    OUTPUT = 1,
173    #[doc = "3: `11`"]
174    UART2_CTS = 3,
175    #[doc = "5: `101`"]
176    LCD0_VSYNC = 5,
177    #[doc = "15: `1111`"]
178    IO_DISABLE = 15,
179}
180impl From<PE1_SELECT_A> for u8 {
181    #[inline(always)]
182    fn from(variant: PE1_SELECT_A) -> Self {
183        variant as _
184    }
185}
186impl crate::FieldSpec for PE1_SELECT_A {
187    type Ux = u8;
188}
189impl PE1_SELECT_R {
190    #[doc = "Get enumerated values variant"]
191    #[inline(always)]
192    pub const fn variant(&self) -> Option<PE1_SELECT_A> {
193        match self.bits {
194            0 => Some(PE1_SELECT_A::INPUT),
195            2 => Some(PE1_SELECT_A::NCSI0_VSYNC),
196            4 => Some(PE1_SELECT_A::TWI1_SDA),
197            8 => Some(PE1_SELECT_A::RGMII_RXD0_RMII_RXD0),
198            14 => Some(PE1_SELECT_A::PE_EINT1),
199            1 => Some(PE1_SELECT_A::OUTPUT),
200            3 => Some(PE1_SELECT_A::UART2_CTS),
201            5 => Some(PE1_SELECT_A::LCD0_VSYNC),
202            15 => Some(PE1_SELECT_A::IO_DISABLE),
203            _ => None,
204        }
205    }
206    #[doc = "`0`"]
207    #[inline(always)]
208    pub fn is_input(&self) -> bool {
209        *self == PE1_SELECT_A::INPUT
210    }
211    #[doc = "`10`"]
212    #[inline(always)]
213    pub fn is_ncsi0_vsync(&self) -> bool {
214        *self == PE1_SELECT_A::NCSI0_VSYNC
215    }
216    #[doc = "`100`"]
217    #[inline(always)]
218    pub fn is_twi1_sda(&self) -> bool {
219        *self == PE1_SELECT_A::TWI1_SDA
220    }
221    #[doc = "`1000`"]
222    #[inline(always)]
223    pub fn is_rgmii_rxd0_rmii_rxd0(&self) -> bool {
224        *self == PE1_SELECT_A::RGMII_RXD0_RMII_RXD0
225    }
226    #[doc = "`1110`"]
227    #[inline(always)]
228    pub fn is_pe_eint1(&self) -> bool {
229        *self == PE1_SELECT_A::PE_EINT1
230    }
231    #[doc = "`1`"]
232    #[inline(always)]
233    pub fn is_output(&self) -> bool {
234        *self == PE1_SELECT_A::OUTPUT
235    }
236    #[doc = "`11`"]
237    #[inline(always)]
238    pub fn is_uart2_cts(&self) -> bool {
239        *self == PE1_SELECT_A::UART2_CTS
240    }
241    #[doc = "`101`"]
242    #[inline(always)]
243    pub fn is_lcd0_vsync(&self) -> bool {
244        *self == PE1_SELECT_A::LCD0_VSYNC
245    }
246    #[doc = "`1111`"]
247    #[inline(always)]
248    pub fn is_io_disable(&self) -> bool {
249        *self == PE1_SELECT_A::IO_DISABLE
250    }
251}
252#[doc = "Field `pe1_select` writer - PE1 Select"]
253pub type PE1_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PE1_SELECT_A>;
254impl<'a, REG> PE1_SELECT_W<'a, REG>
255where
256    REG: crate::Writable + crate::RegisterSpec,
257    REG::Ux: From<u8>,
258{
259    #[doc = "`0`"]
260    #[inline(always)]
261    pub fn input(self) -> &'a mut crate::W<REG> {
262        self.variant(PE1_SELECT_A::INPUT)
263    }
264    #[doc = "`10`"]
265    #[inline(always)]
266    pub fn ncsi0_vsync(self) -> &'a mut crate::W<REG> {
267        self.variant(PE1_SELECT_A::NCSI0_VSYNC)
268    }
269    #[doc = "`100`"]
270    #[inline(always)]
271    pub fn twi1_sda(self) -> &'a mut crate::W<REG> {
272        self.variant(PE1_SELECT_A::TWI1_SDA)
273    }
274    #[doc = "`1000`"]
275    #[inline(always)]
276    pub fn rgmii_rxd0_rmii_rxd0(self) -> &'a mut crate::W<REG> {
277        self.variant(PE1_SELECT_A::RGMII_RXD0_RMII_RXD0)
278    }
279    #[doc = "`1110`"]
280    #[inline(always)]
281    pub fn pe_eint1(self) -> &'a mut crate::W<REG> {
282        self.variant(PE1_SELECT_A::PE_EINT1)
283    }
284    #[doc = "`1`"]
285    #[inline(always)]
286    pub fn output(self) -> &'a mut crate::W<REG> {
287        self.variant(PE1_SELECT_A::OUTPUT)
288    }
289    #[doc = "`11`"]
290    #[inline(always)]
291    pub fn uart2_cts(self) -> &'a mut crate::W<REG> {
292        self.variant(PE1_SELECT_A::UART2_CTS)
293    }
294    #[doc = "`101`"]
295    #[inline(always)]
296    pub fn lcd0_vsync(self) -> &'a mut crate::W<REG> {
297        self.variant(PE1_SELECT_A::LCD0_VSYNC)
298    }
299    #[doc = "`1111`"]
300    #[inline(always)]
301    pub fn io_disable(self) -> &'a mut crate::W<REG> {
302        self.variant(PE1_SELECT_A::IO_DISABLE)
303    }
304}
305#[doc = "Field `pe2_select` reader - PE2 Select"]
306pub type PE2_SELECT_R = crate::FieldReader<PE2_SELECT_A>;
307#[doc = "PE2 Select\n\nValue on reset: 0"]
308#[derive(Clone, Copy, Debug, PartialEq, Eq)]
309#[repr(u8)]
310pub enum PE2_SELECT_A {
311    #[doc = "0: `0`"]
312    INPUT = 0,
313    #[doc = "2: `10`"]
314    NCSI0_PCLK = 2,
315    #[doc = "4: `100`"]
316    TWI0_SCK = 4,
317    #[doc = "6: `110`"]
318    UART0_TX = 6,
319    #[doc = "8: `1000`"]
320    RGMII_RXD1_RMII_RXD1 = 8,
321    #[doc = "14: `1110`"]
322    PE_EINT2 = 14,
323    #[doc = "15: `1111`"]
324    IO_DISABLE = 15,
325    #[doc = "1: `1`"]
326    OUTPUT = 1,
327    #[doc = "3: `11`"]
328    UART2_TX = 3,
329    #[doc = "5: `101`"]
330    CLK_FANOUT0 = 5,
331}
332impl From<PE2_SELECT_A> for u8 {
333    #[inline(always)]
334    fn from(variant: PE2_SELECT_A) -> Self {
335        variant as _
336    }
337}
338impl crate::FieldSpec for PE2_SELECT_A {
339    type Ux = u8;
340}
341impl PE2_SELECT_R {
342    #[doc = "Get enumerated values variant"]
343    #[inline(always)]
344    pub const fn variant(&self) -> Option<PE2_SELECT_A> {
345        match self.bits {
346            0 => Some(PE2_SELECT_A::INPUT),
347            2 => Some(PE2_SELECT_A::NCSI0_PCLK),
348            4 => Some(PE2_SELECT_A::TWI0_SCK),
349            6 => Some(PE2_SELECT_A::UART0_TX),
350            8 => Some(PE2_SELECT_A::RGMII_RXD1_RMII_RXD1),
351            14 => Some(PE2_SELECT_A::PE_EINT2),
352            15 => Some(PE2_SELECT_A::IO_DISABLE),
353            1 => Some(PE2_SELECT_A::OUTPUT),
354            3 => Some(PE2_SELECT_A::UART2_TX),
355            5 => Some(PE2_SELECT_A::CLK_FANOUT0),
356            _ => None,
357        }
358    }
359    #[doc = "`0`"]
360    #[inline(always)]
361    pub fn is_input(&self) -> bool {
362        *self == PE2_SELECT_A::INPUT
363    }
364    #[doc = "`10`"]
365    #[inline(always)]
366    pub fn is_ncsi0_pclk(&self) -> bool {
367        *self == PE2_SELECT_A::NCSI0_PCLK
368    }
369    #[doc = "`100`"]
370    #[inline(always)]
371    pub fn is_twi0_sck(&self) -> bool {
372        *self == PE2_SELECT_A::TWI0_SCK
373    }
374    #[doc = "`110`"]
375    #[inline(always)]
376    pub fn is_uart0_tx(&self) -> bool {
377        *self == PE2_SELECT_A::UART0_TX
378    }
379    #[doc = "`1000`"]
380    #[inline(always)]
381    pub fn is_rgmii_rxd1_rmii_rxd1(&self) -> bool {
382        *self == PE2_SELECT_A::RGMII_RXD1_RMII_RXD1
383    }
384    #[doc = "`1110`"]
385    #[inline(always)]
386    pub fn is_pe_eint2(&self) -> bool {
387        *self == PE2_SELECT_A::PE_EINT2
388    }
389    #[doc = "`1111`"]
390    #[inline(always)]
391    pub fn is_io_disable(&self) -> bool {
392        *self == PE2_SELECT_A::IO_DISABLE
393    }
394    #[doc = "`1`"]
395    #[inline(always)]
396    pub fn is_output(&self) -> bool {
397        *self == PE2_SELECT_A::OUTPUT
398    }
399    #[doc = "`11`"]
400    #[inline(always)]
401    pub fn is_uart2_tx(&self) -> bool {
402        *self == PE2_SELECT_A::UART2_TX
403    }
404    #[doc = "`101`"]
405    #[inline(always)]
406    pub fn is_clk_fanout0(&self) -> bool {
407        *self == PE2_SELECT_A::CLK_FANOUT0
408    }
409}
410#[doc = "Field `pe2_select` writer - PE2 Select"]
411pub type PE2_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PE2_SELECT_A>;
412impl<'a, REG> PE2_SELECT_W<'a, REG>
413where
414    REG: crate::Writable + crate::RegisterSpec,
415    REG::Ux: From<u8>,
416{
417    #[doc = "`0`"]
418    #[inline(always)]
419    pub fn input(self) -> &'a mut crate::W<REG> {
420        self.variant(PE2_SELECT_A::INPUT)
421    }
422    #[doc = "`10`"]
423    #[inline(always)]
424    pub fn ncsi0_pclk(self) -> &'a mut crate::W<REG> {
425        self.variant(PE2_SELECT_A::NCSI0_PCLK)
426    }
427    #[doc = "`100`"]
428    #[inline(always)]
429    pub fn twi0_sck(self) -> &'a mut crate::W<REG> {
430        self.variant(PE2_SELECT_A::TWI0_SCK)
431    }
432    #[doc = "`110`"]
433    #[inline(always)]
434    pub fn uart0_tx(self) -> &'a mut crate::W<REG> {
435        self.variant(PE2_SELECT_A::UART0_TX)
436    }
437    #[doc = "`1000`"]
438    #[inline(always)]
439    pub fn rgmii_rxd1_rmii_rxd1(self) -> &'a mut crate::W<REG> {
440        self.variant(PE2_SELECT_A::RGMII_RXD1_RMII_RXD1)
441    }
442    #[doc = "`1110`"]
443    #[inline(always)]
444    pub fn pe_eint2(self) -> &'a mut crate::W<REG> {
445        self.variant(PE2_SELECT_A::PE_EINT2)
446    }
447    #[doc = "`1111`"]
448    #[inline(always)]
449    pub fn io_disable(self) -> &'a mut crate::W<REG> {
450        self.variant(PE2_SELECT_A::IO_DISABLE)
451    }
452    #[doc = "`1`"]
453    #[inline(always)]
454    pub fn output(self) -> &'a mut crate::W<REG> {
455        self.variant(PE2_SELECT_A::OUTPUT)
456    }
457    #[doc = "`11`"]
458    #[inline(always)]
459    pub fn uart2_tx(self) -> &'a mut crate::W<REG> {
460        self.variant(PE2_SELECT_A::UART2_TX)
461    }
462    #[doc = "`101`"]
463    #[inline(always)]
464    pub fn clk_fanout0(self) -> &'a mut crate::W<REG> {
465        self.variant(PE2_SELECT_A::CLK_FANOUT0)
466    }
467}
468#[doc = "Field `pe3_select` reader - PE3 Select"]
469pub type PE3_SELECT_R = crate::FieldReader<PE3_SELECT_A>;
470#[doc = "PE3 Select\n\nValue on reset: 0"]
471#[derive(Clone, Copy, Debug, PartialEq, Eq)]
472#[repr(u8)]
473pub enum PE3_SELECT_A {
474    #[doc = "0: `0`"]
475    INPUT = 0,
476    #[doc = "2: `10`"]
477    NCSI0_MCLK = 2,
478    #[doc = "4: `100`"]
479    TWI0_SDA = 4,
480    #[doc = "6: `110`"]
481    UART0_RX = 6,
482    #[doc = "8: `1000`"]
483    RGMII_TXCK_RMII_TXCK = 8,
484    #[doc = "14: `1110`"]
485    PE_EINT3 = 14,
486    #[doc = "15: `1111`"]
487    IO_DISABLE = 15,
488    #[doc = "1: `1`"]
489    OUTPUT = 1,
490    #[doc = "3: `11`"]
491    UART2_RX = 3,
492    #[doc = "5: `101`"]
493    CLK_FANOUT1 = 5,
494}
495impl From<PE3_SELECT_A> for u8 {
496    #[inline(always)]
497    fn from(variant: PE3_SELECT_A) -> Self {
498        variant as _
499    }
500}
501impl crate::FieldSpec for PE3_SELECT_A {
502    type Ux = u8;
503}
504impl PE3_SELECT_R {
505    #[doc = "Get enumerated values variant"]
506    #[inline(always)]
507    pub const fn variant(&self) -> Option<PE3_SELECT_A> {
508        match self.bits {
509            0 => Some(PE3_SELECT_A::INPUT),
510            2 => Some(PE3_SELECT_A::NCSI0_MCLK),
511            4 => Some(PE3_SELECT_A::TWI0_SDA),
512            6 => Some(PE3_SELECT_A::UART0_RX),
513            8 => Some(PE3_SELECT_A::RGMII_TXCK_RMII_TXCK),
514            14 => Some(PE3_SELECT_A::PE_EINT3),
515            15 => Some(PE3_SELECT_A::IO_DISABLE),
516            1 => Some(PE3_SELECT_A::OUTPUT),
517            3 => Some(PE3_SELECT_A::UART2_RX),
518            5 => Some(PE3_SELECT_A::CLK_FANOUT1),
519            _ => None,
520        }
521    }
522    #[doc = "`0`"]
523    #[inline(always)]
524    pub fn is_input(&self) -> bool {
525        *self == PE3_SELECT_A::INPUT
526    }
527    #[doc = "`10`"]
528    #[inline(always)]
529    pub fn is_ncsi0_mclk(&self) -> bool {
530        *self == PE3_SELECT_A::NCSI0_MCLK
531    }
532    #[doc = "`100`"]
533    #[inline(always)]
534    pub fn is_twi0_sda(&self) -> bool {
535        *self == PE3_SELECT_A::TWI0_SDA
536    }
537    #[doc = "`110`"]
538    #[inline(always)]
539    pub fn is_uart0_rx(&self) -> bool {
540        *self == PE3_SELECT_A::UART0_RX
541    }
542    #[doc = "`1000`"]
543    #[inline(always)]
544    pub fn is_rgmii_txck_rmii_txck(&self) -> bool {
545        *self == PE3_SELECT_A::RGMII_TXCK_RMII_TXCK
546    }
547    #[doc = "`1110`"]
548    #[inline(always)]
549    pub fn is_pe_eint3(&self) -> bool {
550        *self == PE3_SELECT_A::PE_EINT3
551    }
552    #[doc = "`1111`"]
553    #[inline(always)]
554    pub fn is_io_disable(&self) -> bool {
555        *self == PE3_SELECT_A::IO_DISABLE
556    }
557    #[doc = "`1`"]
558    #[inline(always)]
559    pub fn is_output(&self) -> bool {
560        *self == PE3_SELECT_A::OUTPUT
561    }
562    #[doc = "`11`"]
563    #[inline(always)]
564    pub fn is_uart2_rx(&self) -> bool {
565        *self == PE3_SELECT_A::UART2_RX
566    }
567    #[doc = "`101`"]
568    #[inline(always)]
569    pub fn is_clk_fanout1(&self) -> bool {
570        *self == PE3_SELECT_A::CLK_FANOUT1
571    }
572}
573#[doc = "Field `pe3_select` writer - PE3 Select"]
574pub type PE3_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PE3_SELECT_A>;
575impl<'a, REG> PE3_SELECT_W<'a, REG>
576where
577    REG: crate::Writable + crate::RegisterSpec,
578    REG::Ux: From<u8>,
579{
580    #[doc = "`0`"]
581    #[inline(always)]
582    pub fn input(self) -> &'a mut crate::W<REG> {
583        self.variant(PE3_SELECT_A::INPUT)
584    }
585    #[doc = "`10`"]
586    #[inline(always)]
587    pub fn ncsi0_mclk(self) -> &'a mut crate::W<REG> {
588        self.variant(PE3_SELECT_A::NCSI0_MCLK)
589    }
590    #[doc = "`100`"]
591    #[inline(always)]
592    pub fn twi0_sda(self) -> &'a mut crate::W<REG> {
593        self.variant(PE3_SELECT_A::TWI0_SDA)
594    }
595    #[doc = "`110`"]
596    #[inline(always)]
597    pub fn uart0_rx(self) -> &'a mut crate::W<REG> {
598        self.variant(PE3_SELECT_A::UART0_RX)
599    }
600    #[doc = "`1000`"]
601    #[inline(always)]
602    pub fn rgmii_txck_rmii_txck(self) -> &'a mut crate::W<REG> {
603        self.variant(PE3_SELECT_A::RGMII_TXCK_RMII_TXCK)
604    }
605    #[doc = "`1110`"]
606    #[inline(always)]
607    pub fn pe_eint3(self) -> &'a mut crate::W<REG> {
608        self.variant(PE3_SELECT_A::PE_EINT3)
609    }
610    #[doc = "`1111`"]
611    #[inline(always)]
612    pub fn io_disable(self) -> &'a mut crate::W<REG> {
613        self.variant(PE3_SELECT_A::IO_DISABLE)
614    }
615    #[doc = "`1`"]
616    #[inline(always)]
617    pub fn output(self) -> &'a mut crate::W<REG> {
618        self.variant(PE3_SELECT_A::OUTPUT)
619    }
620    #[doc = "`11`"]
621    #[inline(always)]
622    pub fn uart2_rx(self) -> &'a mut crate::W<REG> {
623        self.variant(PE3_SELECT_A::UART2_RX)
624    }
625    #[doc = "`101`"]
626    #[inline(always)]
627    pub fn clk_fanout1(self) -> &'a mut crate::W<REG> {
628        self.variant(PE3_SELECT_A::CLK_FANOUT1)
629    }
630}
631#[doc = "Field `pe4_select` reader - PE4 Select"]
632pub type PE4_SELECT_R = crate::FieldReader<PE4_SELECT_A>;
633#[doc = "PE4 Select\n\nValue on reset: 0"]
634#[derive(Clone, Copy, Debug, PartialEq, Eq)]
635#[repr(u8)]
636pub enum PE4_SELECT_A {
637    #[doc = "0: `0`"]
638    INPUT = 0,
639    #[doc = "2: `10`"]
640    NCSI0_D0 = 2,
641    #[doc = "4: `100`"]
642    TWI2_SCK = 4,
643    #[doc = "6: `110`"]
644    D_JTAG_MS = 6,
645    #[doc = "8: `1000`"]
646    RGMII_TXD0_RMII_TXD0 = 8,
647    #[doc = "14: `1110`"]
648    PE_EINT4 = 14,
649    #[doc = "15: `1111`"]
650    IO_DISABLE = 15,
651    #[doc = "1: `1`"]
652    OUTPUT = 1,
653    #[doc = "3: `11`"]
654    UART4_TX = 3,
655    #[doc = "5: `101`"]
656    CLK_FANOUT2 = 5,
657    #[doc = "7: `111`"]
658    R_JTAG_MS = 7,
659}
660impl From<PE4_SELECT_A> for u8 {
661    #[inline(always)]
662    fn from(variant: PE4_SELECT_A) -> Self {
663        variant as _
664    }
665}
666impl crate::FieldSpec for PE4_SELECT_A {
667    type Ux = u8;
668}
669impl PE4_SELECT_R {
670    #[doc = "Get enumerated values variant"]
671    #[inline(always)]
672    pub const fn variant(&self) -> Option<PE4_SELECT_A> {
673        match self.bits {
674            0 => Some(PE4_SELECT_A::INPUT),
675            2 => Some(PE4_SELECT_A::NCSI0_D0),
676            4 => Some(PE4_SELECT_A::TWI2_SCK),
677            6 => Some(PE4_SELECT_A::D_JTAG_MS),
678            8 => Some(PE4_SELECT_A::RGMII_TXD0_RMII_TXD0),
679            14 => Some(PE4_SELECT_A::PE_EINT4),
680            15 => Some(PE4_SELECT_A::IO_DISABLE),
681            1 => Some(PE4_SELECT_A::OUTPUT),
682            3 => Some(PE4_SELECT_A::UART4_TX),
683            5 => Some(PE4_SELECT_A::CLK_FANOUT2),
684            7 => Some(PE4_SELECT_A::R_JTAG_MS),
685            _ => None,
686        }
687    }
688    #[doc = "`0`"]
689    #[inline(always)]
690    pub fn is_input(&self) -> bool {
691        *self == PE4_SELECT_A::INPUT
692    }
693    #[doc = "`10`"]
694    #[inline(always)]
695    pub fn is_ncsi0_d0(&self) -> bool {
696        *self == PE4_SELECT_A::NCSI0_D0
697    }
698    #[doc = "`100`"]
699    #[inline(always)]
700    pub fn is_twi2_sck(&self) -> bool {
701        *self == PE4_SELECT_A::TWI2_SCK
702    }
703    #[doc = "`110`"]
704    #[inline(always)]
705    pub fn is_d_jtag_ms(&self) -> bool {
706        *self == PE4_SELECT_A::D_JTAG_MS
707    }
708    #[doc = "`1000`"]
709    #[inline(always)]
710    pub fn is_rgmii_txd0_rmii_txd0(&self) -> bool {
711        *self == PE4_SELECT_A::RGMII_TXD0_RMII_TXD0
712    }
713    #[doc = "`1110`"]
714    #[inline(always)]
715    pub fn is_pe_eint4(&self) -> bool {
716        *self == PE4_SELECT_A::PE_EINT4
717    }
718    #[doc = "`1111`"]
719    #[inline(always)]
720    pub fn is_io_disable(&self) -> bool {
721        *self == PE4_SELECT_A::IO_DISABLE
722    }
723    #[doc = "`1`"]
724    #[inline(always)]
725    pub fn is_output(&self) -> bool {
726        *self == PE4_SELECT_A::OUTPUT
727    }
728    #[doc = "`11`"]
729    #[inline(always)]
730    pub fn is_uart4_tx(&self) -> bool {
731        *self == PE4_SELECT_A::UART4_TX
732    }
733    #[doc = "`101`"]
734    #[inline(always)]
735    pub fn is_clk_fanout2(&self) -> bool {
736        *self == PE4_SELECT_A::CLK_FANOUT2
737    }
738    #[doc = "`111`"]
739    #[inline(always)]
740    pub fn is_r_jtag_ms(&self) -> bool {
741        *self == PE4_SELECT_A::R_JTAG_MS
742    }
743}
744#[doc = "Field `pe4_select` writer - PE4 Select"]
745pub type PE4_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PE4_SELECT_A>;
746impl<'a, REG> PE4_SELECT_W<'a, REG>
747where
748    REG: crate::Writable + crate::RegisterSpec,
749    REG::Ux: From<u8>,
750{
751    #[doc = "`0`"]
752    #[inline(always)]
753    pub fn input(self) -> &'a mut crate::W<REG> {
754        self.variant(PE4_SELECT_A::INPUT)
755    }
756    #[doc = "`10`"]
757    #[inline(always)]
758    pub fn ncsi0_d0(self) -> &'a mut crate::W<REG> {
759        self.variant(PE4_SELECT_A::NCSI0_D0)
760    }
761    #[doc = "`100`"]
762    #[inline(always)]
763    pub fn twi2_sck(self) -> &'a mut crate::W<REG> {
764        self.variant(PE4_SELECT_A::TWI2_SCK)
765    }
766    #[doc = "`110`"]
767    #[inline(always)]
768    pub fn d_jtag_ms(self) -> &'a mut crate::W<REG> {
769        self.variant(PE4_SELECT_A::D_JTAG_MS)
770    }
771    #[doc = "`1000`"]
772    #[inline(always)]
773    pub fn rgmii_txd0_rmii_txd0(self) -> &'a mut crate::W<REG> {
774        self.variant(PE4_SELECT_A::RGMII_TXD0_RMII_TXD0)
775    }
776    #[doc = "`1110`"]
777    #[inline(always)]
778    pub fn pe_eint4(self) -> &'a mut crate::W<REG> {
779        self.variant(PE4_SELECT_A::PE_EINT4)
780    }
781    #[doc = "`1111`"]
782    #[inline(always)]
783    pub fn io_disable(self) -> &'a mut crate::W<REG> {
784        self.variant(PE4_SELECT_A::IO_DISABLE)
785    }
786    #[doc = "`1`"]
787    #[inline(always)]
788    pub fn output(self) -> &'a mut crate::W<REG> {
789        self.variant(PE4_SELECT_A::OUTPUT)
790    }
791    #[doc = "`11`"]
792    #[inline(always)]
793    pub fn uart4_tx(self) -> &'a mut crate::W<REG> {
794        self.variant(PE4_SELECT_A::UART4_TX)
795    }
796    #[doc = "`101`"]
797    #[inline(always)]
798    pub fn clk_fanout2(self) -> &'a mut crate::W<REG> {
799        self.variant(PE4_SELECT_A::CLK_FANOUT2)
800    }
801    #[doc = "`111`"]
802    #[inline(always)]
803    pub fn r_jtag_ms(self) -> &'a mut crate::W<REG> {
804        self.variant(PE4_SELECT_A::R_JTAG_MS)
805    }
806}
807#[doc = "Field `pe5_select` reader - PE5 Select"]
808pub type PE5_SELECT_R = crate::FieldReader<PE5_SELECT_A>;
809#[doc = "PE5 Select\n\nValue on reset: 0"]
810#[derive(Clone, Copy, Debug, PartialEq, Eq)]
811#[repr(u8)]
812pub enum PE5_SELECT_A {
813    #[doc = "0: `0`"]
814    INPUT = 0,
815    #[doc = "2: `10`"]
816    NCSI0_D1 = 2,
817    #[doc = "4: `100`"]
818    TWI2_SDA = 4,
819    #[doc = "6: `110`"]
820    D_JTAG_DI = 6,
821    #[doc = "8: `1000`"]
822    RGMII_TXD1_RMII_TXD1 = 8,
823    #[doc = "14: `1110`"]
824    PE_EINT5 = 14,
825    #[doc = "15: `1111`"]
826    IO_DISABLE = 15,
827    #[doc = "1: `1`"]
828    OUTPUT = 1,
829    #[doc = "3: `11`"]
830    UART4_RX = 3,
831    #[doc = "5: `101`"]
832    LEDC_DO = 5,
833    #[doc = "7: `111`"]
834    R_JTAG_DI = 7,
835}
836impl From<PE5_SELECT_A> for u8 {
837    #[inline(always)]
838    fn from(variant: PE5_SELECT_A) -> Self {
839        variant as _
840    }
841}
842impl crate::FieldSpec for PE5_SELECT_A {
843    type Ux = u8;
844}
845impl PE5_SELECT_R {
846    #[doc = "Get enumerated values variant"]
847    #[inline(always)]
848    pub const fn variant(&self) -> Option<PE5_SELECT_A> {
849        match self.bits {
850            0 => Some(PE5_SELECT_A::INPUT),
851            2 => Some(PE5_SELECT_A::NCSI0_D1),
852            4 => Some(PE5_SELECT_A::TWI2_SDA),
853            6 => Some(PE5_SELECT_A::D_JTAG_DI),
854            8 => Some(PE5_SELECT_A::RGMII_TXD1_RMII_TXD1),
855            14 => Some(PE5_SELECT_A::PE_EINT5),
856            15 => Some(PE5_SELECT_A::IO_DISABLE),
857            1 => Some(PE5_SELECT_A::OUTPUT),
858            3 => Some(PE5_SELECT_A::UART4_RX),
859            5 => Some(PE5_SELECT_A::LEDC_DO),
860            7 => Some(PE5_SELECT_A::R_JTAG_DI),
861            _ => None,
862        }
863    }
864    #[doc = "`0`"]
865    #[inline(always)]
866    pub fn is_input(&self) -> bool {
867        *self == PE5_SELECT_A::INPUT
868    }
869    #[doc = "`10`"]
870    #[inline(always)]
871    pub fn is_ncsi0_d1(&self) -> bool {
872        *self == PE5_SELECT_A::NCSI0_D1
873    }
874    #[doc = "`100`"]
875    #[inline(always)]
876    pub fn is_twi2_sda(&self) -> bool {
877        *self == PE5_SELECT_A::TWI2_SDA
878    }
879    #[doc = "`110`"]
880    #[inline(always)]
881    pub fn is_d_jtag_di(&self) -> bool {
882        *self == PE5_SELECT_A::D_JTAG_DI
883    }
884    #[doc = "`1000`"]
885    #[inline(always)]
886    pub fn is_rgmii_txd1_rmii_txd1(&self) -> bool {
887        *self == PE5_SELECT_A::RGMII_TXD1_RMII_TXD1
888    }
889    #[doc = "`1110`"]
890    #[inline(always)]
891    pub fn is_pe_eint5(&self) -> bool {
892        *self == PE5_SELECT_A::PE_EINT5
893    }
894    #[doc = "`1111`"]
895    #[inline(always)]
896    pub fn is_io_disable(&self) -> bool {
897        *self == PE5_SELECT_A::IO_DISABLE
898    }
899    #[doc = "`1`"]
900    #[inline(always)]
901    pub fn is_output(&self) -> bool {
902        *self == PE5_SELECT_A::OUTPUT
903    }
904    #[doc = "`11`"]
905    #[inline(always)]
906    pub fn is_uart4_rx(&self) -> bool {
907        *self == PE5_SELECT_A::UART4_RX
908    }
909    #[doc = "`101`"]
910    #[inline(always)]
911    pub fn is_ledc_do(&self) -> bool {
912        *self == PE5_SELECT_A::LEDC_DO
913    }
914    #[doc = "`111`"]
915    #[inline(always)]
916    pub fn is_r_jtag_di(&self) -> bool {
917        *self == PE5_SELECT_A::R_JTAG_DI
918    }
919}
920#[doc = "Field `pe5_select` writer - PE5 Select"]
921pub type PE5_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PE5_SELECT_A>;
922impl<'a, REG> PE5_SELECT_W<'a, REG>
923where
924    REG: crate::Writable + crate::RegisterSpec,
925    REG::Ux: From<u8>,
926{
927    #[doc = "`0`"]
928    #[inline(always)]
929    pub fn input(self) -> &'a mut crate::W<REG> {
930        self.variant(PE5_SELECT_A::INPUT)
931    }
932    #[doc = "`10`"]
933    #[inline(always)]
934    pub fn ncsi0_d1(self) -> &'a mut crate::W<REG> {
935        self.variant(PE5_SELECT_A::NCSI0_D1)
936    }
937    #[doc = "`100`"]
938    #[inline(always)]
939    pub fn twi2_sda(self) -> &'a mut crate::W<REG> {
940        self.variant(PE5_SELECT_A::TWI2_SDA)
941    }
942    #[doc = "`110`"]
943    #[inline(always)]
944    pub fn d_jtag_di(self) -> &'a mut crate::W<REG> {
945        self.variant(PE5_SELECT_A::D_JTAG_DI)
946    }
947    #[doc = "`1000`"]
948    #[inline(always)]
949    pub fn rgmii_txd1_rmii_txd1(self) -> &'a mut crate::W<REG> {
950        self.variant(PE5_SELECT_A::RGMII_TXD1_RMII_TXD1)
951    }
952    #[doc = "`1110`"]
953    #[inline(always)]
954    pub fn pe_eint5(self) -> &'a mut crate::W<REG> {
955        self.variant(PE5_SELECT_A::PE_EINT5)
956    }
957    #[doc = "`1111`"]
958    #[inline(always)]
959    pub fn io_disable(self) -> &'a mut crate::W<REG> {
960        self.variant(PE5_SELECT_A::IO_DISABLE)
961    }
962    #[doc = "`1`"]
963    #[inline(always)]
964    pub fn output(self) -> &'a mut crate::W<REG> {
965        self.variant(PE5_SELECT_A::OUTPUT)
966    }
967    #[doc = "`11`"]
968    #[inline(always)]
969    pub fn uart4_rx(self) -> &'a mut crate::W<REG> {
970        self.variant(PE5_SELECT_A::UART4_RX)
971    }
972    #[doc = "`101`"]
973    #[inline(always)]
974    pub fn ledc_do(self) -> &'a mut crate::W<REG> {
975        self.variant(PE5_SELECT_A::LEDC_DO)
976    }
977    #[doc = "`111`"]
978    #[inline(always)]
979    pub fn r_jtag_di(self) -> &'a mut crate::W<REG> {
980        self.variant(PE5_SELECT_A::R_JTAG_DI)
981    }
982}
983#[doc = "Field `pe6_select` reader - PE6 Select"]
984pub type PE6_SELECT_R = crate::FieldReader<PE6_SELECT_A>;
985#[doc = "PE6 Select\n\nValue on reset: 0"]
986#[derive(Clone, Copy, Debug, PartialEq, Eq)]
987#[repr(u8)]
988pub enum PE6_SELECT_A {
989    #[doc = "0: `0`"]
990    INPUT = 0,
991    #[doc = "2: `10`"]
992    NCSI0_D2 = 2,
993    #[doc = "4: `100`"]
994    TWI3_SCK = 4,
995    #[doc = "6: `110`"]
996    D_JTAG_DO = 6,
997    #[doc = "8: `1000`"]
998    RMII_TXCTRL_RMII_TXEN = 8,
999    #[doc = "14: `1110`"]
1000    PE_EINT6 = 14,
1001    #[doc = "15: `1111`"]
1002    IO_DISABLE = 15,
1003    #[doc = "1: `1`"]
1004    OUTPUT = 1,
1005    #[doc = "3: `11`"]
1006    UART5_TX = 3,
1007    #[doc = "5: `101`"]
1008    OWA_IN = 5,
1009    #[doc = "7: `111`"]
1010    R_JTAG_DO = 7,
1011}
1012impl From<PE6_SELECT_A> for u8 {
1013    #[inline(always)]
1014    fn from(variant: PE6_SELECT_A) -> Self {
1015        variant as _
1016    }
1017}
1018impl crate::FieldSpec for PE6_SELECT_A {
1019    type Ux = u8;
1020}
1021impl PE6_SELECT_R {
1022    #[doc = "Get enumerated values variant"]
1023    #[inline(always)]
1024    pub const fn variant(&self) -> Option<PE6_SELECT_A> {
1025        match self.bits {
1026            0 => Some(PE6_SELECT_A::INPUT),
1027            2 => Some(PE6_SELECT_A::NCSI0_D2),
1028            4 => Some(PE6_SELECT_A::TWI3_SCK),
1029            6 => Some(PE6_SELECT_A::D_JTAG_DO),
1030            8 => Some(PE6_SELECT_A::RMII_TXCTRL_RMII_TXEN),
1031            14 => Some(PE6_SELECT_A::PE_EINT6),
1032            15 => Some(PE6_SELECT_A::IO_DISABLE),
1033            1 => Some(PE6_SELECT_A::OUTPUT),
1034            3 => Some(PE6_SELECT_A::UART5_TX),
1035            5 => Some(PE6_SELECT_A::OWA_IN),
1036            7 => Some(PE6_SELECT_A::R_JTAG_DO),
1037            _ => None,
1038        }
1039    }
1040    #[doc = "`0`"]
1041    #[inline(always)]
1042    pub fn is_input(&self) -> bool {
1043        *self == PE6_SELECT_A::INPUT
1044    }
1045    #[doc = "`10`"]
1046    #[inline(always)]
1047    pub fn is_ncsi0_d2(&self) -> bool {
1048        *self == PE6_SELECT_A::NCSI0_D2
1049    }
1050    #[doc = "`100`"]
1051    #[inline(always)]
1052    pub fn is_twi3_sck(&self) -> bool {
1053        *self == PE6_SELECT_A::TWI3_SCK
1054    }
1055    #[doc = "`110`"]
1056    #[inline(always)]
1057    pub fn is_d_jtag_do(&self) -> bool {
1058        *self == PE6_SELECT_A::D_JTAG_DO
1059    }
1060    #[doc = "`1000`"]
1061    #[inline(always)]
1062    pub fn is_rmii_txctrl_rmii_txen(&self) -> bool {
1063        *self == PE6_SELECT_A::RMII_TXCTRL_RMII_TXEN
1064    }
1065    #[doc = "`1110`"]
1066    #[inline(always)]
1067    pub fn is_pe_eint6(&self) -> bool {
1068        *self == PE6_SELECT_A::PE_EINT6
1069    }
1070    #[doc = "`1111`"]
1071    #[inline(always)]
1072    pub fn is_io_disable(&self) -> bool {
1073        *self == PE6_SELECT_A::IO_DISABLE
1074    }
1075    #[doc = "`1`"]
1076    #[inline(always)]
1077    pub fn is_output(&self) -> bool {
1078        *self == PE6_SELECT_A::OUTPUT
1079    }
1080    #[doc = "`11`"]
1081    #[inline(always)]
1082    pub fn is_uart5_tx(&self) -> bool {
1083        *self == PE6_SELECT_A::UART5_TX
1084    }
1085    #[doc = "`101`"]
1086    #[inline(always)]
1087    pub fn is_owa_in(&self) -> bool {
1088        *self == PE6_SELECT_A::OWA_IN
1089    }
1090    #[doc = "`111`"]
1091    #[inline(always)]
1092    pub fn is_r_jtag_do(&self) -> bool {
1093        *self == PE6_SELECT_A::R_JTAG_DO
1094    }
1095}
1096#[doc = "Field `pe6_select` writer - PE6 Select"]
1097pub type PE6_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PE6_SELECT_A>;
1098impl<'a, REG> PE6_SELECT_W<'a, REG>
1099where
1100    REG: crate::Writable + crate::RegisterSpec,
1101    REG::Ux: From<u8>,
1102{
1103    #[doc = "`0`"]
1104    #[inline(always)]
1105    pub fn input(self) -> &'a mut crate::W<REG> {
1106        self.variant(PE6_SELECT_A::INPUT)
1107    }
1108    #[doc = "`10`"]
1109    #[inline(always)]
1110    pub fn ncsi0_d2(self) -> &'a mut crate::W<REG> {
1111        self.variant(PE6_SELECT_A::NCSI0_D2)
1112    }
1113    #[doc = "`100`"]
1114    #[inline(always)]
1115    pub fn twi3_sck(self) -> &'a mut crate::W<REG> {
1116        self.variant(PE6_SELECT_A::TWI3_SCK)
1117    }
1118    #[doc = "`110`"]
1119    #[inline(always)]
1120    pub fn d_jtag_do(self) -> &'a mut crate::W<REG> {
1121        self.variant(PE6_SELECT_A::D_JTAG_DO)
1122    }
1123    #[doc = "`1000`"]
1124    #[inline(always)]
1125    pub fn rmii_txctrl_rmii_txen(self) -> &'a mut crate::W<REG> {
1126        self.variant(PE6_SELECT_A::RMII_TXCTRL_RMII_TXEN)
1127    }
1128    #[doc = "`1110`"]
1129    #[inline(always)]
1130    pub fn pe_eint6(self) -> &'a mut crate::W<REG> {
1131        self.variant(PE6_SELECT_A::PE_EINT6)
1132    }
1133    #[doc = "`1111`"]
1134    #[inline(always)]
1135    pub fn io_disable(self) -> &'a mut crate::W<REG> {
1136        self.variant(PE6_SELECT_A::IO_DISABLE)
1137    }
1138    #[doc = "`1`"]
1139    #[inline(always)]
1140    pub fn output(self) -> &'a mut crate::W<REG> {
1141        self.variant(PE6_SELECT_A::OUTPUT)
1142    }
1143    #[doc = "`11`"]
1144    #[inline(always)]
1145    pub fn uart5_tx(self) -> &'a mut crate::W<REG> {
1146        self.variant(PE6_SELECT_A::UART5_TX)
1147    }
1148    #[doc = "`101`"]
1149    #[inline(always)]
1150    pub fn owa_in(self) -> &'a mut crate::W<REG> {
1151        self.variant(PE6_SELECT_A::OWA_IN)
1152    }
1153    #[doc = "`111`"]
1154    #[inline(always)]
1155    pub fn r_jtag_do(self) -> &'a mut crate::W<REG> {
1156        self.variant(PE6_SELECT_A::R_JTAG_DO)
1157    }
1158}
1159#[doc = "Field `pe7_select` reader - PE7 Select"]
1160pub type PE7_SELECT_R = crate::FieldReader<PE7_SELECT_A>;
1161#[doc = "PE7 Select\n\nValue on reset: 0"]
1162#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1163#[repr(u8)]
1164pub enum PE7_SELECT_A {
1165    #[doc = "0: `0`"]
1166    INPUT = 0,
1167    #[doc = "2: `10`"]
1168    NCSI0_D3 = 2,
1169    #[doc = "4: `100`"]
1170    TWI3_SDA = 4,
1171    #[doc = "6: `110`"]
1172    D_JTAG_CK = 6,
1173    #[doc = "8: `1000`"]
1174    RGMII_CLKIN_RMII_RXER = 8,
1175    #[doc = "14: `1110`"]
1176    PE_EINT7 = 14,
1177    #[doc = "15: `1111`"]
1178    IO_DISABLE = 15,
1179    #[doc = "1: `1`"]
1180    OUTPUT = 1,
1181    #[doc = "3: `11`"]
1182    UART5_RX = 3,
1183    #[doc = "5: `101`"]
1184    OWA_OUT = 5,
1185    #[doc = "7: `111`"]
1186    R_JTAG_CK = 7,
1187}
1188impl From<PE7_SELECT_A> for u8 {
1189    #[inline(always)]
1190    fn from(variant: PE7_SELECT_A) -> Self {
1191        variant as _
1192    }
1193}
1194impl crate::FieldSpec for PE7_SELECT_A {
1195    type Ux = u8;
1196}
1197impl PE7_SELECT_R {
1198    #[doc = "Get enumerated values variant"]
1199    #[inline(always)]
1200    pub const fn variant(&self) -> Option<PE7_SELECT_A> {
1201        match self.bits {
1202            0 => Some(PE7_SELECT_A::INPUT),
1203            2 => Some(PE7_SELECT_A::NCSI0_D3),
1204            4 => Some(PE7_SELECT_A::TWI3_SDA),
1205            6 => Some(PE7_SELECT_A::D_JTAG_CK),
1206            8 => Some(PE7_SELECT_A::RGMII_CLKIN_RMII_RXER),
1207            14 => Some(PE7_SELECT_A::PE_EINT7),
1208            15 => Some(PE7_SELECT_A::IO_DISABLE),
1209            1 => Some(PE7_SELECT_A::OUTPUT),
1210            3 => Some(PE7_SELECT_A::UART5_RX),
1211            5 => Some(PE7_SELECT_A::OWA_OUT),
1212            7 => Some(PE7_SELECT_A::R_JTAG_CK),
1213            _ => None,
1214        }
1215    }
1216    #[doc = "`0`"]
1217    #[inline(always)]
1218    pub fn is_input(&self) -> bool {
1219        *self == PE7_SELECT_A::INPUT
1220    }
1221    #[doc = "`10`"]
1222    #[inline(always)]
1223    pub fn is_ncsi0_d3(&self) -> bool {
1224        *self == PE7_SELECT_A::NCSI0_D3
1225    }
1226    #[doc = "`100`"]
1227    #[inline(always)]
1228    pub fn is_twi3_sda(&self) -> bool {
1229        *self == PE7_SELECT_A::TWI3_SDA
1230    }
1231    #[doc = "`110`"]
1232    #[inline(always)]
1233    pub fn is_d_jtag_ck(&self) -> bool {
1234        *self == PE7_SELECT_A::D_JTAG_CK
1235    }
1236    #[doc = "`1000`"]
1237    #[inline(always)]
1238    pub fn is_rgmii_clkin_rmii_rxer(&self) -> bool {
1239        *self == PE7_SELECT_A::RGMII_CLKIN_RMII_RXER
1240    }
1241    #[doc = "`1110`"]
1242    #[inline(always)]
1243    pub fn is_pe_eint7(&self) -> bool {
1244        *self == PE7_SELECT_A::PE_EINT7
1245    }
1246    #[doc = "`1111`"]
1247    #[inline(always)]
1248    pub fn is_io_disable(&self) -> bool {
1249        *self == PE7_SELECT_A::IO_DISABLE
1250    }
1251    #[doc = "`1`"]
1252    #[inline(always)]
1253    pub fn is_output(&self) -> bool {
1254        *self == PE7_SELECT_A::OUTPUT
1255    }
1256    #[doc = "`11`"]
1257    #[inline(always)]
1258    pub fn is_uart5_rx(&self) -> bool {
1259        *self == PE7_SELECT_A::UART5_RX
1260    }
1261    #[doc = "`101`"]
1262    #[inline(always)]
1263    pub fn is_owa_out(&self) -> bool {
1264        *self == PE7_SELECT_A::OWA_OUT
1265    }
1266    #[doc = "`111`"]
1267    #[inline(always)]
1268    pub fn is_r_jtag_ck(&self) -> bool {
1269        *self == PE7_SELECT_A::R_JTAG_CK
1270    }
1271}
1272#[doc = "Field `pe7_select` writer - PE7 Select"]
1273pub type PE7_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PE7_SELECT_A>;
1274impl<'a, REG> PE7_SELECT_W<'a, REG>
1275where
1276    REG: crate::Writable + crate::RegisterSpec,
1277    REG::Ux: From<u8>,
1278{
1279    #[doc = "`0`"]
1280    #[inline(always)]
1281    pub fn input(self) -> &'a mut crate::W<REG> {
1282        self.variant(PE7_SELECT_A::INPUT)
1283    }
1284    #[doc = "`10`"]
1285    #[inline(always)]
1286    pub fn ncsi0_d3(self) -> &'a mut crate::W<REG> {
1287        self.variant(PE7_SELECT_A::NCSI0_D3)
1288    }
1289    #[doc = "`100`"]
1290    #[inline(always)]
1291    pub fn twi3_sda(self) -> &'a mut crate::W<REG> {
1292        self.variant(PE7_SELECT_A::TWI3_SDA)
1293    }
1294    #[doc = "`110`"]
1295    #[inline(always)]
1296    pub fn d_jtag_ck(self) -> &'a mut crate::W<REG> {
1297        self.variant(PE7_SELECT_A::D_JTAG_CK)
1298    }
1299    #[doc = "`1000`"]
1300    #[inline(always)]
1301    pub fn rgmii_clkin_rmii_rxer(self) -> &'a mut crate::W<REG> {
1302        self.variant(PE7_SELECT_A::RGMII_CLKIN_RMII_RXER)
1303    }
1304    #[doc = "`1110`"]
1305    #[inline(always)]
1306    pub fn pe_eint7(self) -> &'a mut crate::W<REG> {
1307        self.variant(PE7_SELECT_A::PE_EINT7)
1308    }
1309    #[doc = "`1111`"]
1310    #[inline(always)]
1311    pub fn io_disable(self) -> &'a mut crate::W<REG> {
1312        self.variant(PE7_SELECT_A::IO_DISABLE)
1313    }
1314    #[doc = "`1`"]
1315    #[inline(always)]
1316    pub fn output(self) -> &'a mut crate::W<REG> {
1317        self.variant(PE7_SELECT_A::OUTPUT)
1318    }
1319    #[doc = "`11`"]
1320    #[inline(always)]
1321    pub fn uart5_rx(self) -> &'a mut crate::W<REG> {
1322        self.variant(PE7_SELECT_A::UART5_RX)
1323    }
1324    #[doc = "`101`"]
1325    #[inline(always)]
1326    pub fn owa_out(self) -> &'a mut crate::W<REG> {
1327        self.variant(PE7_SELECT_A::OWA_OUT)
1328    }
1329    #[doc = "`111`"]
1330    #[inline(always)]
1331    pub fn r_jtag_ck(self) -> &'a mut crate::W<REG> {
1332        self.variant(PE7_SELECT_A::R_JTAG_CK)
1333    }
1334}
1335impl R {
1336    #[doc = "Bits 0:3 - PE0 Select"]
1337    #[inline(always)]
1338    pub fn pe0_select(&self) -> PE0_SELECT_R {
1339        PE0_SELECT_R::new((self.bits & 0x0f) as u8)
1340    }
1341    #[doc = "Bits 4:7 - PE1 Select"]
1342    #[inline(always)]
1343    pub fn pe1_select(&self) -> PE1_SELECT_R {
1344        PE1_SELECT_R::new(((self.bits >> 4) & 0x0f) as u8)
1345    }
1346    #[doc = "Bits 8:11 - PE2 Select"]
1347    #[inline(always)]
1348    pub fn pe2_select(&self) -> PE2_SELECT_R {
1349        PE2_SELECT_R::new(((self.bits >> 8) & 0x0f) as u8)
1350    }
1351    #[doc = "Bits 12:15 - PE3 Select"]
1352    #[inline(always)]
1353    pub fn pe3_select(&self) -> PE3_SELECT_R {
1354        PE3_SELECT_R::new(((self.bits >> 12) & 0x0f) as u8)
1355    }
1356    #[doc = "Bits 16:19 - PE4 Select"]
1357    #[inline(always)]
1358    pub fn pe4_select(&self) -> PE4_SELECT_R {
1359        PE4_SELECT_R::new(((self.bits >> 16) & 0x0f) as u8)
1360    }
1361    #[doc = "Bits 20:23 - PE5 Select"]
1362    #[inline(always)]
1363    pub fn pe5_select(&self) -> PE5_SELECT_R {
1364        PE5_SELECT_R::new(((self.bits >> 20) & 0x0f) as u8)
1365    }
1366    #[doc = "Bits 24:27 - PE6 Select"]
1367    #[inline(always)]
1368    pub fn pe6_select(&self) -> PE6_SELECT_R {
1369        PE6_SELECT_R::new(((self.bits >> 24) & 0x0f) as u8)
1370    }
1371    #[doc = "Bits 28:31 - PE7 Select"]
1372    #[inline(always)]
1373    pub fn pe7_select(&self) -> PE7_SELECT_R {
1374        PE7_SELECT_R::new(((self.bits >> 28) & 0x0f) as u8)
1375    }
1376}
1377impl W {
1378    #[doc = "Bits 0:3 - PE0 Select"]
1379    #[inline(always)]
1380    #[must_use]
1381    pub fn pe0_select(&mut self) -> PE0_SELECT_W<PE_CFG0_SPEC> {
1382        PE0_SELECT_W::new(self, 0)
1383    }
1384    #[doc = "Bits 4:7 - PE1 Select"]
1385    #[inline(always)]
1386    #[must_use]
1387    pub fn pe1_select(&mut self) -> PE1_SELECT_W<PE_CFG0_SPEC> {
1388        PE1_SELECT_W::new(self, 4)
1389    }
1390    #[doc = "Bits 8:11 - PE2 Select"]
1391    #[inline(always)]
1392    #[must_use]
1393    pub fn pe2_select(&mut self) -> PE2_SELECT_W<PE_CFG0_SPEC> {
1394        PE2_SELECT_W::new(self, 8)
1395    }
1396    #[doc = "Bits 12:15 - PE3 Select"]
1397    #[inline(always)]
1398    #[must_use]
1399    pub fn pe3_select(&mut self) -> PE3_SELECT_W<PE_CFG0_SPEC> {
1400        PE3_SELECT_W::new(self, 12)
1401    }
1402    #[doc = "Bits 16:19 - PE4 Select"]
1403    #[inline(always)]
1404    #[must_use]
1405    pub fn pe4_select(&mut self) -> PE4_SELECT_W<PE_CFG0_SPEC> {
1406        PE4_SELECT_W::new(self, 16)
1407    }
1408    #[doc = "Bits 20:23 - PE5 Select"]
1409    #[inline(always)]
1410    #[must_use]
1411    pub fn pe5_select(&mut self) -> PE5_SELECT_W<PE_CFG0_SPEC> {
1412        PE5_SELECT_W::new(self, 20)
1413    }
1414    #[doc = "Bits 24:27 - PE6 Select"]
1415    #[inline(always)]
1416    #[must_use]
1417    pub fn pe6_select(&mut self) -> PE6_SELECT_W<PE_CFG0_SPEC> {
1418        PE6_SELECT_W::new(self, 24)
1419    }
1420    #[doc = "Bits 28:31 - PE7 Select"]
1421    #[inline(always)]
1422    #[must_use]
1423    pub fn pe7_select(&mut self) -> PE7_SELECT_W<PE_CFG0_SPEC> {
1424        PE7_SELECT_W::new(self, 28)
1425    }
1426    #[doc = r" Writes raw bits to the register."]
1427    #[doc = r""]
1428    #[doc = r" # Safety"]
1429    #[doc = r""]
1430    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
1431    #[inline(always)]
1432    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1433        self.bits = bits;
1434        self
1435    }
1436}
1437#[doc = "PE Configure Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pe_cfg0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pe_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1438pub struct PE_CFG0_SPEC;
1439impl crate::RegisterSpec for PE_CFG0_SPEC {
1440    type Ux = u32;
1441}
1442#[doc = "`read()` method returns [`pe_cfg0::R`](R) reader structure"]
1443impl crate::Readable for PE_CFG0_SPEC {}
1444#[doc = "`write(|w| ..)` method takes [`pe_cfg0::W`](W) writer structure"]
1445impl crate::Writable for PE_CFG0_SPEC {
1446    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
1447    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
1448}
1449#[doc = "`reset()` method sets pe_cfg0 to value 0"]
1450impl crate::Resettable for PE_CFG0_SPEC {
1451    const RESET_VALUE: Self::Ux = 0;
1452}
d1_pac/gpio/pe_cfg0.rs

d1_pac/gpio/
pe_cfg0.rs
