1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 pll_cpu_ctrl: PLL_CPU_CTRL,
5 _reserved1: [u8; 0x0c],
6 pll_ddr_ctrl: PLL_DDR_CTRL,
7 _reserved2: [u8; 0x0c],
8 pll_peri_ctrl: PLL_PERI_CTRL,
9 _reserved3: [u8; 0x1c],
10 pll_video0_ctrl: PLL_VIDEO0_CTRL,
11 _reserved4: [u8; 0x04],
12 pll_video1_ctrl: PLL_VIDEO1_CTRL,
13 _reserved5: [u8; 0x0c],
14 pll_ve_ctrl: PLL_VE_CTRL,
15 _reserved6: [u8; 0x1c],
16 pll_audio0_ctrl: PLL_AUDIO0_CTRL,
17 _reserved7: [u8; 0x04],
18 pll_audio1_ctrl: PLL_AUDIO1_CTRL,
19 _reserved8: [u8; 0x8c],
20 pll_ddr_pat0_ctrl: PLL_DDR_PAT0_CTRL,
21 pll_ddr_pat1_ctrl: PLL_DDR_PAT1_CTRL,
22 _reserved10: [u8; 0x08],
23 pll_peri_pat0_ctrl: PLL_PERI_PAT0_CTRL,
24 pll_peri_pat1_ctrl: PLL_PERI_PAT1_CTRL,
25 _reserved12: [u8; 0x18],
26 pll_video0_pat0_ctrl: PLL_VIDEO0_PAT0_CTRL,
27 pll_video0_pat1_ctrl: PLL_VIDEO0_PAT1_CTRL,
28 pll_video1_pat0_ctrl: PLL_VIDEO1_PAT0_CTRL,
29 pll_video1_pat1_ctrl: PLL_VIDEO1_PAT1_CTRL,
30 _reserved16: [u8; 0x08],
31 pll_ve_pat0_ctrl: PLL_VE_PAT0_CTRL,
32 pll_ve_pat1_ctrl: PLL_VE_PAT1_CTRL,
33 _reserved18: [u8; 0x18],
34 pll_audio0_pat0_ctrl: PLL_AUDIO0_PAT0_CTRL,
35 pll_audio0_pat1_ctrl: PLL_AUDIO0_PAT1_CTRL,
36 pll_audio1_pat0_ctrl: PLL_AUDIO1_PAT0_CTRL,
37 pll_audio1_pat1_ctrl: PLL_AUDIO1_PAT1_CTRL,
38 _reserved22: [u8; 0x0178],
39 pll_cpu_bias: PLL_CPU_BIAS,
40 _reserved23: [u8; 0x0c],
41 pll_ddr_bias: PLL_DDR_BIAS,
42 _reserved24: [u8; 0x0c],
43 pll_peri_bias: PLL_PERI_BIAS,
44 _reserved25: [u8; 0x1c],
45 pll_video0_bias: PLL_VIDEO0_BIAS,
46 _reserved26: [u8; 0x04],
47 pll_video1_bias: PLL_VIDEO1_BIAS,
48 _reserved27: [u8; 0x0c],
49 pll_ve_bias: PLL_VE_BIAS,
50 _reserved28: [u8; 0x1c],
51 pll_audio0_bias: PLL_AUDIO0_BIAS,
52 _reserved29: [u8; 0x04],
53 pll_audio1_bias: PLL_AUDIO1_BIAS,
54 _reserved30: [u8; 0x7c],
55 pll_cpu_tun: PLL_CPU_TUN,
56 _reserved31: [u8; 0xfc],
57 cpu_axi_cfg: CPU_AXI_CFG,
58 cpu_gating: CPU_GATING,
59 _reserved33: [u8; 0x08],
60 psi_clk: PSI_CLK,
61 _reserved34: [u8; 0x0c],
62 apb_clk: [APB_CLK; 2],
63 _reserved35: [u8; 0x18],
64 mbus_clk: MBUS_CLK,
65 _reserved36: [u8; 0xbc],
66 de_clk: DE_CLK,
67 _reserved37: [u8; 0x08],
68 de_bgr: DE_BGR,
69 _reserved38: [u8; 0x10],
70 di_clk: DI_CLK,
71 _reserved39: [u8; 0x08],
72 di_bgr: DI_BGR,
73 g2d_clk: G2D_CLK,
74 _reserved41: [u8; 0x08],
75 g2d_bgr: G2D_BGR,
76 _reserved42: [u8; 0x40],
77 ce_clk: CE_CLK,
78 _reserved43: [u8; 0x08],
79 ce_bgr: CE_BGR,
80 ve_clk: VE_CLK,
81 _reserved45: [u8; 0x08],
82 ve_bgr: VE_BGR,
83 _reserved46: [u8; 0x6c],
84 dma_bgr: DMA_BGR,
85 _reserved47: [u8; 0x0c],
86 msgbox_bgr: MSGBOX_BGR,
87 _reserved48: [u8; 0x0c],
88 spinlock_bgr: SPINLOCK_BGR,
89 _reserved49: [u8; 0x0c],
90 hstimer_bgr: HSTIMER_BGR,
91 avs_clk: AVS_CLK,
92 _reserved51: [u8; 0x48],
93 dbgsys_bgr: DBGSYS_BGR,
94 _reserved52: [u8; 0x1c],
95 pwm_bgr: PWM_BGR,
96 _reserved53: [u8; 0x0c],
97 iommu_bgr: IOMMU_BGR,
98 _reserved54: [u8; 0x40],
99 dram_clk: DRAM_CLK,
100 mbus_mat_clk_gating: MBUS_MAT_CLK_GATING,
101 _reserved56: [u8; 0x04],
102 dram_bgr: DRAM_BGR,
103 _reserved57: [u8; 0x20],
104 smhc0_clk: SMHC0_CLK,
105 smhc1_clk: SMHC1_CLK,
106 smhc2_clk: SMHC2_CLK,
107 _reserved60: [u8; 0x10],
108 smhc_bgr: SMHC_BGR,
109 _reserved61: [u8; 0xbc],
110 uart_bgr: UART_BGR,
111 _reserved62: [u8; 0x0c],
112 twi_bgr: TWI_BGR,
113 _reserved63: [u8; 0x20],
114 spi0_clk: SPI0_CLK,
115 spi1_clk: SPI1_CLK,
116 _reserved65: [u8; 0x24],
117 spi_bgr: SPI_BGR,
118 emac_25m_clk: EMAC_25M_CLK,
119 _reserved67: [u8; 0x08],
120 emac_bgr: EMAC_BGR,
121 _reserved68: [u8; 0x40],
122 irtx_clk: IRTX_CLK,
123 _reserved69: [u8; 0x08],
124 irtx_bgr: IRTX_BGR,
125 _reserved70: [u8; 0x1c],
126 gpadc_bgr: GPADC_BGR,
127 _reserved71: [u8; 0x0c],
128 ths_bgr: THS_BGR,
129 _reserved72: [u8; 0x10],
130 i2s_clk: [I2S_CLK; 3],
131 i2s2_asrc_clk: I2S2_ASRC_CLK,
132 i2s_bgr: I2S_BGR,
133 owa_tx_clk: OWA_TX_CLK,
134 owa_rx_clk: OWA_RX_CLK,
135 owa_bgr: OWA_BGR,
136 _reserved78: [u8; 0x10],
137 dmic_clk: DMIC_CLK,
138 _reserved79: [u8; 0x08],
139 dmic_bgr: DMIC_BGR,
140 audio_codec_dac_clk: AUDIO_CODEC_DAC_CLK,
141 audio_codec_adc_clk: AUDIO_CODEC_ADC_CLK,
142 _reserved82: [u8; 0x04],
143 audio_codec_bgr: AUDIO_CODEC_BGR,
144 _reserved83: [u8; 0x10],
145 usb0_clk: USB0_CLK,
146 usb1_clk: USB1_CLK,
147 _reserved85: [u8; 0x14],
148 usb_bgr: USB_BGR,
149 _reserved86: [u8; 0x0c],
150 lradc_bgr: LRADC_BGR,
151 _reserved87: [u8; 0x1c],
152 dpss_top_bgr: DPSS_TOP_BGR,
153 _reserved88: [u8; 0x64],
154 dsi_clk: DSI_CLK,
155 _reserved89: [u8; 0x24],
156 dsi_bgr: DSI_BGR,
157 _reserved90: [u8; 0x10],
158 tconlcd_clk: TCONLCD_CLK,
159 _reserved91: [u8; 0x18],
160 tconlcd_bgr: TCONLCD_BGR,
161 tcontv_clk: TCONTV_CLK,
162 _reserved93: [u8; 0x18],
163 tcontv_bgr: TCONTV_BGR,
164 _reserved94: [u8; 0x0c],
165 lvds_bgr: LVDS_BGR,
166 tve_clk: TVE_CLK,
167 _reserved96: [u8; 0x08],
168 tve_bgr: TVE_BGR,
169 tvd_clk: TVD_CLK,
170 _reserved98: [u8; 0x18],
171 tvd_bgr: TVD_BGR,
172 _reserved99: [u8; 0x10],
173 ledc_clk: LEDC_CLK,
174 _reserved100: [u8; 0x08],
175 ledc_bgr: LEDC_BGR,
176 _reserved101: [u8; 0x04],
177 csi_clk: CSI_CLK,
178 csi_master_clk: CSI_MASTER_CLK,
179 _reserved103: [u8; 0x10],
180 csi_bgr: CSI_BGR,
181 _reserved104: [u8; 0x30],
182 tpadc_clk: TPADC_CLK,
183 _reserved105: [u8; 0x08],
184 tpadc_bgr: TPADC_BGR,
185 _reserved106: [u8; 0x10],
186 dsp_clk: DSP_CLK,
187 _reserved107: [u8; 0x08],
188 dsp_bgr: DSP_BGR,
189 _reserved108: [u8; 0x80],
190 riscv_clk: RISCV_CLK,
191 riscv_gating: RISCV_GATING,
192 _reserved110: [u8; 0x04],
193 riscv_cfg_bgr: RISCV_CFG_BGR,
194 _reserved111: [u8; 0x01f4],
195 pll_lock_dbg_ctrl: PLL_LOCK_DBG_CTRL,
196 fre_det_ctrl: FRE_DET_CTRL,
197 fre_up_lim: FRE_UP_LIM,
198 fre_down_lim: FRE_DOWN_LIM,
199 _reserved115: [u8; 0x1c],
200 ccu_fan_gate: CCU_FAN_GATE,
201 clk27m_fan: CLK27M_FAN,
202 pclk_fan: PCLK_FAN,
203 ccu_fan: CCU_FAN,
204}
205impl RegisterBlock {
206 #[doc = "0x00 - PLL_CPU Control Register"]
207 #[inline(always)]
208 pub const fn pll_cpu_ctrl(&self) -> &PLL_CPU_CTRL {
209 &self.pll_cpu_ctrl
210 }
211 #[doc = "0x10 - PLL_DDR Control Register"]
212 #[inline(always)]
213 pub const fn pll_ddr_ctrl(&self) -> &PLL_DDR_CTRL {
214 &self.pll_ddr_ctrl
215 }
216 #[doc = "0x20 - PLL_PERI Control Register"]
217 #[inline(always)]
218 pub const fn pll_peri_ctrl(&self) -> &PLL_PERI_CTRL {
219 &self.pll_peri_ctrl
220 }
221 #[doc = "0x40 - PLL_VIDEO0 Control Register"]
222 #[inline(always)]
223 pub const fn pll_video0_ctrl(&self) -> &PLL_VIDEO0_CTRL {
224 &self.pll_video0_ctrl
225 }
226 #[doc = "0x48 - PLL_VIDEO1 Control Register"]
227 #[inline(always)]
228 pub const fn pll_video1_ctrl(&self) -> &PLL_VIDEO1_CTRL {
229 &self.pll_video1_ctrl
230 }
231 #[doc = "0x58 - PLL_VE Control Register"]
232 #[inline(always)]
233 pub const fn pll_ve_ctrl(&self) -> &PLL_VE_CTRL {
234 &self.pll_ve_ctrl
235 }
236 #[doc = "0x78 - PLL_AUDIO0 Control Register"]
237 #[inline(always)]
238 pub const fn pll_audio0_ctrl(&self) -> &PLL_AUDIO0_CTRL {
239 &self.pll_audio0_ctrl
240 }
241 #[doc = "0x80 - PLL_AUDIO1 Control Register"]
242 #[inline(always)]
243 pub const fn pll_audio1_ctrl(&self) -> &PLL_AUDIO1_CTRL {
244 &self.pll_audio1_ctrl
245 }
246 #[doc = "0x110 - PLL_DDR Pattern0 Control Register"]
247 #[inline(always)]
248 pub const fn pll_ddr_pat0_ctrl(&self) -> &PLL_DDR_PAT0_CTRL {
249 &self.pll_ddr_pat0_ctrl
250 }
251 #[doc = "0x114 - PLL_DDR Pattern1 Control Register"]
252 #[inline(always)]
253 pub const fn pll_ddr_pat1_ctrl(&self) -> &PLL_DDR_PAT1_CTRL {
254 &self.pll_ddr_pat1_ctrl
255 }
256 #[doc = "0x120 - PLL_PERI Pattern0 Control Register"]
257 #[inline(always)]
258 pub const fn pll_peri_pat0_ctrl(&self) -> &PLL_PERI_PAT0_CTRL {
259 &self.pll_peri_pat0_ctrl
260 }
261 #[doc = "0x124 - PLL_PERI Pattern1 Control Register"]
262 #[inline(always)]
263 pub const fn pll_peri_pat1_ctrl(&self) -> &PLL_PERI_PAT1_CTRL {
264 &self.pll_peri_pat1_ctrl
265 }
266 #[doc = "0x140 - PLL_VIDEO0 Pattern0 Control Register"]
267 #[inline(always)]
268 pub const fn pll_video0_pat0_ctrl(&self) -> &PLL_VIDEO0_PAT0_CTRL {
269 &self.pll_video0_pat0_ctrl
270 }
271 #[doc = "0x144 - PLL_VIDEO0 Pattern1 Control Register"]
272 #[inline(always)]
273 pub const fn pll_video0_pat1_ctrl(&self) -> &PLL_VIDEO0_PAT1_CTRL {
274 &self.pll_video0_pat1_ctrl
275 }
276 #[doc = "0x148 - PLL_VIDEO1 Pattern0 Control Register"]
277 #[inline(always)]
278 pub const fn pll_video1_pat0_ctrl(&self) -> &PLL_VIDEO1_PAT0_CTRL {
279 &self.pll_video1_pat0_ctrl
280 }
281 #[doc = "0x14c - PLL_VIDEO1 Pattern1 Control Register"]
282 #[inline(always)]
283 pub const fn pll_video1_pat1_ctrl(&self) -> &PLL_VIDEO1_PAT1_CTRL {
284 &self.pll_video1_pat1_ctrl
285 }
286 #[doc = "0x158 - PLL_VE Pattern0 Control Register"]
287 #[inline(always)]
288 pub const fn pll_ve_pat0_ctrl(&self) -> &PLL_VE_PAT0_CTRL {
289 &self.pll_ve_pat0_ctrl
290 }
291 #[doc = "0x15c - PLL_VE Pattern1 Control Register"]
292 #[inline(always)]
293 pub const fn pll_ve_pat1_ctrl(&self) -> &PLL_VE_PAT1_CTRL {
294 &self.pll_ve_pat1_ctrl
295 }
296 #[doc = "0x178 - PLL_AUDIO0 Pattern0 Control Register"]
297 #[inline(always)]
298 pub const fn pll_audio0_pat0_ctrl(&self) -> &PLL_AUDIO0_PAT0_CTRL {
299 &self.pll_audio0_pat0_ctrl
300 }
301 #[doc = "0x17c - PLL_AUDIO0 Pattern1 Control Register"]
302 #[inline(always)]
303 pub const fn pll_audio0_pat1_ctrl(&self) -> &PLL_AUDIO0_PAT1_CTRL {
304 &self.pll_audio0_pat1_ctrl
305 }
306 #[doc = "0x180 - PLL_AUDIO1 Pattern0 Control Register"]
307 #[inline(always)]
308 pub const fn pll_audio1_pat0_ctrl(&self) -> &PLL_AUDIO1_PAT0_CTRL {
309 &self.pll_audio1_pat0_ctrl
310 }
311 #[doc = "0x184 - PLL_AUDIO1 Pattern1 Control Register"]
312 #[inline(always)]
313 pub const fn pll_audio1_pat1_ctrl(&self) -> &PLL_AUDIO1_PAT1_CTRL {
314 &self.pll_audio1_pat1_ctrl
315 }
316 #[doc = "0x300 - PLL_CPU Bias Register"]
317 #[inline(always)]
318 pub const fn pll_cpu_bias(&self) -> &PLL_CPU_BIAS {
319 &self.pll_cpu_bias
320 }
321 #[doc = "0x310 - PLL_DDR Bias Register"]
322 #[inline(always)]
323 pub const fn pll_ddr_bias(&self) -> &PLL_DDR_BIAS {
324 &self.pll_ddr_bias
325 }
326 #[doc = "0x320 - PLL_PERI Bias Register"]
327 #[inline(always)]
328 pub const fn pll_peri_bias(&self) -> &PLL_PERI_BIAS {
329 &self.pll_peri_bias
330 }
331 #[doc = "0x340 - PLL_VIDEO0 Bias Register"]
332 #[inline(always)]
333 pub const fn pll_video0_bias(&self) -> &PLL_VIDEO0_BIAS {
334 &self.pll_video0_bias
335 }
336 #[doc = "0x348 - PLL_VIDEO1 Bias Register"]
337 #[inline(always)]
338 pub const fn pll_video1_bias(&self) -> &PLL_VIDEO1_BIAS {
339 &self.pll_video1_bias
340 }
341 #[doc = "0x358 - PLL_VE Bias Register"]
342 #[inline(always)]
343 pub const fn pll_ve_bias(&self) -> &PLL_VE_BIAS {
344 &self.pll_ve_bias
345 }
346 #[doc = "0x378 - PLL_AUDIO0 Bias Register"]
347 #[inline(always)]
348 pub const fn pll_audio0_bias(&self) -> &PLL_AUDIO0_BIAS {
349 &self.pll_audio0_bias
350 }
351 #[doc = "0x380 - PLL_AUDIO1 Bias Register"]
352 #[inline(always)]
353 pub const fn pll_audio1_bias(&self) -> &PLL_AUDIO1_BIAS {
354 &self.pll_audio1_bias
355 }
356 #[doc = "0x400 - PLL_CPU Tuning Register"]
357 #[inline(always)]
358 pub const fn pll_cpu_tun(&self) -> &PLL_CPU_TUN {
359 &self.pll_cpu_tun
360 }
361 #[doc = "0x500 - CPU_AXI Configuration Register"]
362 #[inline(always)]
363 pub const fn cpu_axi_cfg(&self) -> &CPU_AXI_CFG {
364 &self.cpu_axi_cfg
365 }
366 #[doc = "0x504 - CPU_GATING Configuration Register"]
367 #[inline(always)]
368 pub const fn cpu_gating(&self) -> &CPU_GATING {
369 &self.cpu_gating
370 }
371 #[doc = "0x510 - PSI Clock Register"]
372 #[inline(always)]
373 pub const fn psi_clk(&self) -> &PSI_CLK {
374 &self.psi_clk
375 }
376 #[doc = "0x520..0x528 - APB Clock Register"]
377 #[inline(always)]
378 pub const fn apb_clk(&self, n: usize) -> &APB_CLK {
379 &self.apb_clk[n]
380 }
381 #[doc = "0x520 - APB Clock Register"]
382 #[inline(always)]
383 pub const fn apb0_clk(&self) -> &APB_CLK {
384 self.apb_clk(0)
385 }
386 #[doc = "0x524 - APB Clock Register"]
387 #[inline(always)]
388 pub const fn apb1_clk(&self) -> &APB_CLK {
389 self.apb_clk(1)
390 }
391 #[doc = "0x540 - MBUS Clock Register"]
392 #[inline(always)]
393 pub const fn mbus_clk(&self) -> &MBUS_CLK {
394 &self.mbus_clk
395 }
396 #[doc = "0x600 - DE Clock Register"]
397 #[inline(always)]
398 pub const fn de_clk(&self) -> &DE_CLK {
399 &self.de_clk
400 }
401 #[doc = "0x60c - DE Bus Gating Reset Register"]
402 #[inline(always)]
403 pub const fn de_bgr(&self) -> &DE_BGR {
404 &self.de_bgr
405 }
406 #[doc = "0x620 - DI Clock Register"]
407 #[inline(always)]
408 pub const fn di_clk(&self) -> &DI_CLK {
409 &self.di_clk
410 }
411 #[doc = "0x62c - DI Bus Gating Reset Register"]
412 #[inline(always)]
413 pub const fn di_bgr(&self) -> &DI_BGR {
414 &self.di_bgr
415 }
416 #[doc = "0x630 - G2D Clock Register"]
417 #[inline(always)]
418 pub const fn g2d_clk(&self) -> &G2D_CLK {
419 &self.g2d_clk
420 }
421 #[doc = "0x63c - G2D Bus Gating Reset Register"]
422 #[inline(always)]
423 pub const fn g2d_bgr(&self) -> &G2D_BGR {
424 &self.g2d_bgr
425 }
426 #[doc = "0x680 - CE Clock Register"]
427 #[inline(always)]
428 pub const fn ce_clk(&self) -> &CE_CLK {
429 &self.ce_clk
430 }
431 #[doc = "0x68c - CE Bus Gating Reset Register"]
432 #[inline(always)]
433 pub const fn ce_bgr(&self) -> &CE_BGR {
434 &self.ce_bgr
435 }
436 #[doc = "0x690 - VE Clock Register"]
437 #[inline(always)]
438 pub const fn ve_clk(&self) -> &VE_CLK {
439 &self.ve_clk
440 }
441 #[doc = "0x69c - VE Bus Gating Reset Register"]
442 #[inline(always)]
443 pub const fn ve_bgr(&self) -> &VE_BGR {
444 &self.ve_bgr
445 }
446 #[doc = "0x70c - DMA Bus Gating Reset Register"]
447 #[inline(always)]
448 pub const fn dma_bgr(&self) -> &DMA_BGR {
449 &self.dma_bgr
450 }
451 #[doc = "0x71c - MSGBOX Bus Gating Reset Register"]
452 #[inline(always)]
453 pub const fn msgbox_bgr(&self) -> &MSGBOX_BGR {
454 &self.msgbox_bgr
455 }
456 #[doc = "0x72c - SPINLOCK Bus Gating Reset Register"]
457 #[inline(always)]
458 pub const fn spinlock_bgr(&self) -> &SPINLOCK_BGR {
459 &self.spinlock_bgr
460 }
461 #[doc = "0x73c - HSTIMER Bus Gating Reset Register"]
462 #[inline(always)]
463 pub const fn hstimer_bgr(&self) -> &HSTIMER_BGR {
464 &self.hstimer_bgr
465 }
466 #[doc = "0x740 - AVS Clock Register"]
467 #[inline(always)]
468 pub const fn avs_clk(&self) -> &AVS_CLK {
469 &self.avs_clk
470 }
471 #[doc = "0x78c - DBGSYS Bus Gating Reset Register"]
472 #[inline(always)]
473 pub const fn dbgsys_bgr(&self) -> &DBGSYS_BGR {
474 &self.dbgsys_bgr
475 }
476 #[doc = "0x7ac - PWM Bus Gating Reset Register"]
477 #[inline(always)]
478 pub const fn pwm_bgr(&self) -> &PWM_BGR {
479 &self.pwm_bgr
480 }
481 #[doc = "0x7bc - IOMMU Bus Gating Reset Register"]
482 #[inline(always)]
483 pub const fn iommu_bgr(&self) -> &IOMMU_BGR {
484 &self.iommu_bgr
485 }
486 #[doc = "0x800 - DRAM Clock Register"]
487 #[inline(always)]
488 pub const fn dram_clk(&self) -> &DRAM_CLK {
489 &self.dram_clk
490 }
491 #[doc = "0x804 - MBUS Master Clock Gating Register"]
492 #[inline(always)]
493 pub const fn mbus_mat_clk_gating(&self) -> &MBUS_MAT_CLK_GATING {
494 &self.mbus_mat_clk_gating
495 }
496 #[doc = "0x80c - DRAM Bus Gating Reset Register"]
497 #[inline(always)]
498 pub const fn dram_bgr(&self) -> &DRAM_BGR {
499 &self.dram_bgr
500 }
501 #[doc = "0x830 - SMHC0 Clock Register"]
502 #[inline(always)]
503 pub const fn smhc0_clk(&self) -> &SMHC0_CLK {
504 &self.smhc0_clk
505 }
506 #[doc = "0x834 - SMHC1 Clock Register"]
507 #[inline(always)]
508 pub const fn smhc1_clk(&self) -> &SMHC1_CLK {
509 &self.smhc1_clk
510 }
511 #[doc = "0x838 - SMHC2 Clock Register"]
512 #[inline(always)]
513 pub const fn smhc2_clk(&self) -> &SMHC2_CLK {
514 &self.smhc2_clk
515 }
516 #[doc = "0x84c - SMHC Bus Gating Reset Register"]
517 #[inline(always)]
518 pub const fn smhc_bgr(&self) -> &SMHC_BGR {
519 &self.smhc_bgr
520 }
521 #[doc = "0x90c - UART Bus Gating Reset Register"]
522 #[inline(always)]
523 pub const fn uart_bgr(&self) -> &UART_BGR {
524 &self.uart_bgr
525 }
526 #[doc = "0x91c - TWI Bus Gating Reset Register"]
527 #[inline(always)]
528 pub const fn twi_bgr(&self) -> &TWI_BGR {
529 &self.twi_bgr
530 }
531 #[doc = "0x940 - SPI0 Clock Register"]
532 #[inline(always)]
533 pub const fn spi0_clk(&self) -> &SPI0_CLK {
534 &self.spi0_clk
535 }
536 #[doc = "0x944 - SPI1 Clock Register"]
537 #[inline(always)]
538 pub const fn spi1_clk(&self) -> &SPI1_CLK {
539 &self.spi1_clk
540 }
541 #[doc = "0x96c - SPI Bus Gating Reset Register"]
542 #[inline(always)]
543 pub const fn spi_bgr(&self) -> &SPI_BGR {
544 &self.spi_bgr
545 }
546 #[doc = "0x970 - EMAC_25M Clock Register"]
547 #[inline(always)]
548 pub const fn emac_25m_clk(&self) -> &EMAC_25M_CLK {
549 &self.emac_25m_clk
550 }
551 #[doc = "0x97c - EMAC Bus Gating Reset Register"]
552 #[inline(always)]
553 pub const fn emac_bgr(&self) -> &EMAC_BGR {
554 &self.emac_bgr
555 }
556 #[doc = "0x9c0 - IRTX Clock Register"]
557 #[inline(always)]
558 pub const fn irtx_clk(&self) -> &IRTX_CLK {
559 &self.irtx_clk
560 }
561 #[doc = "0x9cc - IRTX Bus Gating Reset Register"]
562 #[inline(always)]
563 pub const fn irtx_bgr(&self) -> &IRTX_BGR {
564 &self.irtx_bgr
565 }
566 #[doc = "0x9ec - GPADC Bus Gating Reset Register"]
567 #[inline(always)]
568 pub const fn gpadc_bgr(&self) -> &GPADC_BGR {
569 &self.gpadc_bgr
570 }
571 #[doc = "0x9fc - THS Bus Gating Reset Register"]
572 #[inline(always)]
573 pub const fn ths_bgr(&self) -> &THS_BGR {
574 &self.ths_bgr
575 }
576 #[doc = "0xa10..0xa1c - I2S Clock Register"]
577 #[inline(always)]
578 pub const fn i2s_clk(&self, n: usize) -> &I2S_CLK {
579 &self.i2s_clk[n]
580 }
581 #[doc = "0xa10 - I2S Clock Register"]
582 #[inline(always)]
583 pub const fn i2s0_clk(&self) -> &I2S_CLK {
584 self.i2s_clk(0)
585 }
586 #[doc = "0xa14 - I2S Clock Register"]
587 #[inline(always)]
588 pub const fn i2s1_clk(&self) -> &I2S_CLK {
589 self.i2s_clk(1)
590 }
591 #[doc = "0xa18 - I2S Clock Register"]
592 #[inline(always)]
593 pub const fn i2s2_clk(&self) -> &I2S_CLK {
594 self.i2s_clk(2)
595 }
596 #[doc = "0xa1c - I2S2_ASRC Clock Register"]
597 #[inline(always)]
598 pub const fn i2s2_asrc_clk(&self) -> &I2S2_ASRC_CLK {
599 &self.i2s2_asrc_clk
600 }
601 #[doc = "0xa20 - I2S Bus Gating Reset Register"]
602 #[inline(always)]
603 pub const fn i2s_bgr(&self) -> &I2S_BGR {
604 &self.i2s_bgr
605 }
606 #[doc = "0xa24 - OWA_TX Clock Register"]
607 #[inline(always)]
608 pub const fn owa_tx_clk(&self) -> &OWA_TX_CLK {
609 &self.owa_tx_clk
610 }
611 #[doc = "0xa28 - OWA_RX Clock Register"]
612 #[inline(always)]
613 pub const fn owa_rx_clk(&self) -> &OWA_RX_CLK {
614 &self.owa_rx_clk
615 }
616 #[doc = "0xa2c - OWA Bus Gating Reset Register"]
617 #[inline(always)]
618 pub const fn owa_bgr(&self) -> &OWA_BGR {
619 &self.owa_bgr
620 }
621 #[doc = "0xa40 - DMIC Clock Register"]
622 #[inline(always)]
623 pub const fn dmic_clk(&self) -> &DMIC_CLK {
624 &self.dmic_clk
625 }
626 #[doc = "0xa4c - DMIC Bus Gating Reset Register"]
627 #[inline(always)]
628 pub const fn dmic_bgr(&self) -> &DMIC_BGR {
629 &self.dmic_bgr
630 }
631 #[doc = "0xa50 - AUDIO_CODEC_DAC Clock Register"]
632 #[inline(always)]
633 pub const fn audio_codec_dac_clk(&self) -> &AUDIO_CODEC_DAC_CLK {
634 &self.audio_codec_dac_clk
635 }
636 #[doc = "0xa54 - AUDIO_CODEC_ADC Clock Register"]
637 #[inline(always)]
638 pub const fn audio_codec_adc_clk(&self) -> &AUDIO_CODEC_ADC_CLK {
639 &self.audio_codec_adc_clk
640 }
641 #[doc = "0xa5c - AUDIO_CODEC Bus Gating Reset Register"]
642 #[inline(always)]
643 pub const fn audio_codec_bgr(&self) -> &AUDIO_CODEC_BGR {
644 &self.audio_codec_bgr
645 }
646 #[doc = "0xa70 - USB0 Clock Register"]
647 #[inline(always)]
648 pub const fn usb0_clk(&self) -> &USB0_CLK {
649 &self.usb0_clk
650 }
651 #[doc = "0xa74 - USB1 Clock Register"]
652 #[inline(always)]
653 pub const fn usb1_clk(&self) -> &USB1_CLK {
654 &self.usb1_clk
655 }
656 #[doc = "0xa8c - USB Bus Gating Reset Register"]
657 #[inline(always)]
658 pub const fn usb_bgr(&self) -> &USB_BGR {
659 &self.usb_bgr
660 }
661 #[doc = "0xa9c - LRADC Bus Gating Reset Register"]
662 #[inline(always)]
663 pub const fn lradc_bgr(&self) -> &LRADC_BGR {
664 &self.lradc_bgr
665 }
666 #[doc = "0xabc - DPSS_TOP Bus Gating Reset Register"]
667 #[inline(always)]
668 pub const fn dpss_top_bgr(&self) -> &DPSS_TOP_BGR {
669 &self.dpss_top_bgr
670 }
671 #[doc = "0xb24 - DSI Clock Register"]
672 #[inline(always)]
673 pub const fn dsi_clk(&self) -> &DSI_CLK {
674 &self.dsi_clk
675 }
676 #[doc = "0xb4c - DSI Bus Gating Reset Register"]
677 #[inline(always)]
678 pub const fn dsi_bgr(&self) -> &DSI_BGR {
679 &self.dsi_bgr
680 }
681 #[doc = "0xb60 - TCONLCD Clock Register"]
682 #[inline(always)]
683 pub const fn tconlcd_clk(&self) -> &TCONLCD_CLK {
684 &self.tconlcd_clk
685 }
686 #[doc = "0xb7c - TCONLCD Bus Gating Reset Register"]
687 #[inline(always)]
688 pub const fn tconlcd_bgr(&self) -> &TCONLCD_BGR {
689 &self.tconlcd_bgr
690 }
691 #[doc = "0xb80 - TCONTV Clock Register"]
692 #[inline(always)]
693 pub const fn tcontv_clk(&self) -> &TCONTV_CLK {
694 &self.tcontv_clk
695 }
696 #[doc = "0xb9c - TCONTV Bus Gating Reset Register"]
697 #[inline(always)]
698 pub const fn tcontv_bgr(&self) -> &TCONTV_BGR {
699 &self.tcontv_bgr
700 }
701 #[doc = "0xbac - LVDS Bus Gating Reset Register"]
702 #[inline(always)]
703 pub const fn lvds_bgr(&self) -> &LVDS_BGR {
704 &self.lvds_bgr
705 }
706 #[doc = "0xbb0 - TVE Clock Register"]
707 #[inline(always)]
708 pub const fn tve_clk(&self) -> &TVE_CLK {
709 &self.tve_clk
710 }
711 #[doc = "0xbbc - TVE Bus Gating Reset Register"]
712 #[inline(always)]
713 pub const fn tve_bgr(&self) -> &TVE_BGR {
714 &self.tve_bgr
715 }
716 #[doc = "0xbc0 - TVD Clock Register"]
717 #[inline(always)]
718 pub const fn tvd_clk(&self) -> &TVD_CLK {
719 &self.tvd_clk
720 }
721 #[doc = "0xbdc - TVD Bus Gating Reset Register"]
722 #[inline(always)]
723 pub const fn tvd_bgr(&self) -> &TVD_BGR {
724 &self.tvd_bgr
725 }
726 #[doc = "0xbf0 - LEDC Clock Register"]
727 #[inline(always)]
728 pub const fn ledc_clk(&self) -> &LEDC_CLK {
729 &self.ledc_clk
730 }
731 #[doc = "0xbfc - LEDC Bus Gating Reset Register"]
732 #[inline(always)]
733 pub const fn ledc_bgr(&self) -> &LEDC_BGR {
734 &self.ledc_bgr
735 }
736 #[doc = "0xc04 - CSI Clock Register"]
737 #[inline(always)]
738 pub const fn csi_clk(&self) -> &CSI_CLK {
739 &self.csi_clk
740 }
741 #[doc = "0xc08 - CSI Master Clock Register"]
742 #[inline(always)]
743 pub const fn csi_master_clk(&self) -> &CSI_MASTER_CLK {
744 &self.csi_master_clk
745 }
746 #[doc = "0xc1c - CSI Bus Gating Reset Register"]
747 #[inline(always)]
748 pub const fn csi_bgr(&self) -> &CSI_BGR {
749 &self.csi_bgr
750 }
751 #[doc = "0xc50 - TPADC Clock Register"]
752 #[inline(always)]
753 pub const fn tpadc_clk(&self) -> &TPADC_CLK {
754 &self.tpadc_clk
755 }
756 #[doc = "0xc5c - TPADC Bus Gating Reset Register"]
757 #[inline(always)]
758 pub const fn tpadc_bgr(&self) -> &TPADC_BGR {
759 &self.tpadc_bgr
760 }
761 #[doc = "0xc70 - DSP Clock Register"]
762 #[inline(always)]
763 pub const fn dsp_clk(&self) -> &DSP_CLK {
764 &self.dsp_clk
765 }
766 #[doc = "0xc7c - DSP Bus Gating Reset Register"]
767 #[inline(always)]
768 pub const fn dsp_bgr(&self) -> &DSP_BGR {
769 &self.dsp_bgr
770 }
771 #[doc = "0xd00 - RISC-V Clock Register"]
772 #[inline(always)]
773 pub const fn riscv_clk(&self) -> &RISCV_CLK {
774 &self.riscv_clk
775 }
776 #[doc = "0xd04 - RISC-V GATING Configuration Register"]
777 #[inline(always)]
778 pub const fn riscv_gating(&self) -> &RISCV_GATING {
779 &self.riscv_gating
780 }
781 #[doc = "0xd0c - RISC-V_CFG Bus Gating Reset Register"]
782 #[inline(always)]
783 pub const fn riscv_cfg_bgr(&self) -> &RISCV_CFG_BGR {
784 &self.riscv_cfg_bgr
785 }
786 #[doc = "0xf04 - PLL Lock Debug Control Register"]
787 #[inline(always)]
788 pub const fn pll_lock_dbg_ctrl(&self) -> &PLL_LOCK_DBG_CTRL {
789 &self.pll_lock_dbg_ctrl
790 }
791 #[doc = "0xf08 - Frequency Detect Control Register"]
792 #[inline(always)]
793 pub const fn fre_det_ctrl(&self) -> &FRE_DET_CTRL {
794 &self.fre_det_ctrl
795 }
796 #[doc = "0xf0c - Frequency Up Limit Register"]
797 #[inline(always)]
798 pub const fn fre_up_lim(&self) -> &FRE_UP_LIM {
799 &self.fre_up_lim
800 }
801 #[doc = "0xf10 - Frequency Down Limit Register"]
802 #[inline(always)]
803 pub const fn fre_down_lim(&self) -> &FRE_DOWN_LIM {
804 &self.fre_down_lim
805 }
806 #[doc = "0xf30 - CCU FANOUT CLOCK GATE Register"]
807 #[inline(always)]
808 pub const fn ccu_fan_gate(&self) -> &CCU_FAN_GATE {
809 &self.ccu_fan_gate
810 }
811 #[doc = "0xf34 - CLK27M FANOUT Register"]
812 #[inline(always)]
813 pub const fn clk27m_fan(&self) -> &CLK27M_FAN {
814 &self.clk27m_fan
815 }
816 #[doc = "0xf38 - PCLK FANOUT Register"]
817 #[inline(always)]
818 pub const fn pclk_fan(&self) -> &PCLK_FAN {
819 &self.pclk_fan
820 }
821 #[doc = "0xf3c - CCU FANOUT Register"]
822 #[inline(always)]
823 pub const fn ccu_fan(&self) -> &CCU_FAN {
824 &self.ccu_fan
825 }
826}
827#[doc = "pll_cpu_ctrl (rw) register accessor: PLL_CPU Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_cpu_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_cpu_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_cpu_ctrl`] module"]
828pub type PLL_CPU_CTRL = crate::Reg<pll_cpu_ctrl::PLL_CPU_CTRL_SPEC>;
829#[doc = "PLL_CPU Control Register"]
830pub mod pll_cpu_ctrl;
831#[doc = "pll_ddr_ctrl (rw) register accessor: PLL_DDR Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_ddr_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_ddr_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_ddr_ctrl`] module"]
832pub type PLL_DDR_CTRL = crate::Reg<pll_ddr_ctrl::PLL_DDR_CTRL_SPEC>;
833#[doc = "PLL_DDR Control Register"]
834pub mod pll_ddr_ctrl;
835#[doc = "pll_peri_ctrl (rw) register accessor: PLL_PERI Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_peri_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_peri_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_peri_ctrl`] module"]
836pub type PLL_PERI_CTRL = crate::Reg<pll_peri_ctrl::PLL_PERI_CTRL_SPEC>;
837#[doc = "PLL_PERI Control Register"]
838pub mod pll_peri_ctrl;
839#[doc = "pll_video0_ctrl (rw) register accessor: PLL_VIDEO0 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_video0_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_video0_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_video0_ctrl`] module"]
840pub type PLL_VIDEO0_CTRL = crate::Reg<pll_video0_ctrl::PLL_VIDEO0_CTRL_SPEC>;
841#[doc = "PLL_VIDEO0 Control Register"]
842pub mod pll_video0_ctrl;
843#[doc = "pll_video1_ctrl (rw) register accessor: PLL_VIDEO1 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_video1_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_video1_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_video1_ctrl`] module"]
844pub type PLL_VIDEO1_CTRL = crate::Reg<pll_video1_ctrl::PLL_VIDEO1_CTRL_SPEC>;
845#[doc = "PLL_VIDEO1 Control Register"]
846pub mod pll_video1_ctrl;
847#[doc = "pll_ve_ctrl (rw) register accessor: PLL_VE Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_ve_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_ve_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_ve_ctrl`] module"]
848pub type PLL_VE_CTRL = crate::Reg<pll_ve_ctrl::PLL_VE_CTRL_SPEC>;
849#[doc = "PLL_VE Control Register"]
850pub mod pll_ve_ctrl;
851#[doc = "pll_audio0_ctrl (rw) register accessor: PLL_AUDIO0 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_audio0_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_audio0_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_audio0_ctrl`] module"]
852pub type PLL_AUDIO0_CTRL = crate::Reg<pll_audio0_ctrl::PLL_AUDIO0_CTRL_SPEC>;
853#[doc = "PLL_AUDIO0 Control Register"]
854pub mod pll_audio0_ctrl;
855#[doc = "pll_audio1_ctrl (rw) register accessor: PLL_AUDIO1 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_audio1_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_audio1_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_audio1_ctrl`] module"]
856pub type PLL_AUDIO1_CTRL = crate::Reg<pll_audio1_ctrl::PLL_AUDIO1_CTRL_SPEC>;
857#[doc = "PLL_AUDIO1 Control Register"]
858pub mod pll_audio1_ctrl;
859#[doc = "pll_ddr_pat0_ctrl (rw) register accessor: PLL_DDR Pattern0 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_ddr_pat0_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_ddr_pat0_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_ddr_pat0_ctrl`] module"]
860pub type PLL_DDR_PAT0_CTRL = crate::Reg<pll_ddr_pat0_ctrl::PLL_DDR_PAT0_CTRL_SPEC>;
861#[doc = "PLL_DDR Pattern0 Control Register"]
862pub mod pll_ddr_pat0_ctrl;
863#[doc = "pll_ddr_pat1_ctrl (rw) register accessor: PLL_DDR Pattern1 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_ddr_pat1_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_ddr_pat1_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_ddr_pat1_ctrl`] module"]
864pub type PLL_DDR_PAT1_CTRL = crate::Reg<pll_ddr_pat1_ctrl::PLL_DDR_PAT1_CTRL_SPEC>;
865#[doc = "PLL_DDR Pattern1 Control Register"]
866pub mod pll_ddr_pat1_ctrl;
867#[doc = "pll_peri_pat0_ctrl (rw) register accessor: PLL_PERI Pattern0 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_peri_pat0_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_peri_pat0_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_peri_pat0_ctrl`] module"]
868pub type PLL_PERI_PAT0_CTRL = crate::Reg<pll_peri_pat0_ctrl::PLL_PERI_PAT0_CTRL_SPEC>;
869#[doc = "PLL_PERI Pattern0 Control Register"]
870pub mod pll_peri_pat0_ctrl;
871#[doc = "pll_peri_pat1_ctrl (rw) register accessor: PLL_PERI Pattern1 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_peri_pat1_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_peri_pat1_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_peri_pat1_ctrl`] module"]
872pub type PLL_PERI_PAT1_CTRL = crate::Reg<pll_peri_pat1_ctrl::PLL_PERI_PAT1_CTRL_SPEC>;
873#[doc = "PLL_PERI Pattern1 Control Register"]
874pub mod pll_peri_pat1_ctrl;
875#[doc = "pll_video0_pat0_ctrl (rw) register accessor: PLL_VIDEO0 Pattern0 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_video0_pat0_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_video0_pat0_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_video0_pat0_ctrl`] module"]
876pub type PLL_VIDEO0_PAT0_CTRL = crate::Reg<pll_video0_pat0_ctrl::PLL_VIDEO0_PAT0_CTRL_SPEC>;
877#[doc = "PLL_VIDEO0 Pattern0 Control Register"]
878pub mod pll_video0_pat0_ctrl;
879#[doc = "pll_video0_pat1_ctrl (rw) register accessor: PLL_VIDEO0 Pattern1 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_video0_pat1_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_video0_pat1_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_video0_pat1_ctrl`] module"]
880pub type PLL_VIDEO0_PAT1_CTRL = crate::Reg<pll_video0_pat1_ctrl::PLL_VIDEO0_PAT1_CTRL_SPEC>;
881#[doc = "PLL_VIDEO0 Pattern1 Control Register"]
882pub mod pll_video0_pat1_ctrl;
883#[doc = "pll_video1_pat0_ctrl (rw) register accessor: PLL_VIDEO1 Pattern0 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_video1_pat0_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_video1_pat0_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_video1_pat0_ctrl`] module"]
884pub type PLL_VIDEO1_PAT0_CTRL = crate::Reg<pll_video1_pat0_ctrl::PLL_VIDEO1_PAT0_CTRL_SPEC>;
885#[doc = "PLL_VIDEO1 Pattern0 Control Register"]
886pub mod pll_video1_pat0_ctrl;
887#[doc = "pll_video1_pat1_ctrl (rw) register accessor: PLL_VIDEO1 Pattern1 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_video1_pat1_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_video1_pat1_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_video1_pat1_ctrl`] module"]
888pub type PLL_VIDEO1_PAT1_CTRL = crate::Reg<pll_video1_pat1_ctrl::PLL_VIDEO1_PAT1_CTRL_SPEC>;
889#[doc = "PLL_VIDEO1 Pattern1 Control Register"]
890pub mod pll_video1_pat1_ctrl;
891#[doc = "pll_ve_pat0_ctrl (rw) register accessor: PLL_VE Pattern0 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_ve_pat0_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_ve_pat0_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_ve_pat0_ctrl`] module"]
892pub type PLL_VE_PAT0_CTRL = crate::Reg<pll_ve_pat0_ctrl::PLL_VE_PAT0_CTRL_SPEC>;
893#[doc = "PLL_VE Pattern0 Control Register"]
894pub mod pll_ve_pat0_ctrl;
895#[doc = "pll_ve_pat1_ctrl (rw) register accessor: PLL_VE Pattern1 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_ve_pat1_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_ve_pat1_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_ve_pat1_ctrl`] module"]
896pub type PLL_VE_PAT1_CTRL = crate::Reg<pll_ve_pat1_ctrl::PLL_VE_PAT1_CTRL_SPEC>;
897#[doc = "PLL_VE Pattern1 Control Register"]
898pub mod pll_ve_pat1_ctrl;
899#[doc = "pll_audio0_pat0_ctrl (rw) register accessor: PLL_AUDIO0 Pattern0 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_audio0_pat0_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_audio0_pat0_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_audio0_pat0_ctrl`] module"]
900pub type PLL_AUDIO0_PAT0_CTRL = crate::Reg<pll_audio0_pat0_ctrl::PLL_AUDIO0_PAT0_CTRL_SPEC>;
901#[doc = "PLL_AUDIO0 Pattern0 Control Register"]
902pub mod pll_audio0_pat0_ctrl;
903#[doc = "pll_audio0_pat1_ctrl (rw) register accessor: PLL_AUDIO0 Pattern1 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_audio0_pat1_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_audio0_pat1_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_audio0_pat1_ctrl`] module"]
904pub type PLL_AUDIO0_PAT1_CTRL = crate::Reg<pll_audio0_pat1_ctrl::PLL_AUDIO0_PAT1_CTRL_SPEC>;
905#[doc = "PLL_AUDIO0 Pattern1 Control Register"]
906pub mod pll_audio0_pat1_ctrl;
907#[doc = "pll_audio1_pat0_ctrl (rw) register accessor: PLL_AUDIO1 Pattern0 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_audio1_pat0_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_audio1_pat0_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_audio1_pat0_ctrl`] module"]
908pub type PLL_AUDIO1_PAT0_CTRL = crate::Reg<pll_audio1_pat0_ctrl::PLL_AUDIO1_PAT0_CTRL_SPEC>;
909#[doc = "PLL_AUDIO1 Pattern0 Control Register"]
910pub mod pll_audio1_pat0_ctrl;
911#[doc = "pll_audio1_pat1_ctrl (rw) register accessor: PLL_AUDIO1 Pattern1 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_audio1_pat1_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_audio1_pat1_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_audio1_pat1_ctrl`] module"]
912pub type PLL_AUDIO1_PAT1_CTRL = crate::Reg<pll_audio1_pat1_ctrl::PLL_AUDIO1_PAT1_CTRL_SPEC>;
913#[doc = "PLL_AUDIO1 Pattern1 Control Register"]
914pub mod pll_audio1_pat1_ctrl;
915#[doc = "pll_cpu_bias (rw) register accessor: PLL_CPU Bias Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_cpu_bias::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_cpu_bias::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_cpu_bias`] module"]
916pub type PLL_CPU_BIAS = crate::Reg<pll_cpu_bias::PLL_CPU_BIAS_SPEC>;
917#[doc = "PLL_CPU Bias Register"]
918pub mod pll_cpu_bias;
919#[doc = "pll_ddr_bias (rw) register accessor: PLL_DDR Bias Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_ddr_bias::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_ddr_bias::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_ddr_bias`] module"]
920pub type PLL_DDR_BIAS = crate::Reg<pll_ddr_bias::PLL_DDR_BIAS_SPEC>;
921#[doc = "PLL_DDR Bias Register"]
922pub mod pll_ddr_bias;
923#[doc = "pll_peri_bias (rw) register accessor: PLL_PERI Bias Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_peri_bias::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_peri_bias::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_peri_bias`] module"]
924pub type PLL_PERI_BIAS = crate::Reg<pll_peri_bias::PLL_PERI_BIAS_SPEC>;
925#[doc = "PLL_PERI Bias Register"]
926pub mod pll_peri_bias;
927#[doc = "pll_video0_bias (rw) register accessor: PLL_VIDEO0 Bias Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_video0_bias::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_video0_bias::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_video0_bias`] module"]
928pub type PLL_VIDEO0_BIAS = crate::Reg<pll_video0_bias::PLL_VIDEO0_BIAS_SPEC>;
929#[doc = "PLL_VIDEO0 Bias Register"]
930pub mod pll_video0_bias;
931#[doc = "pll_video1_bias (rw) register accessor: PLL_VIDEO1 Bias Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_video1_bias::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_video1_bias::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_video1_bias`] module"]
932pub type PLL_VIDEO1_BIAS = crate::Reg<pll_video1_bias::PLL_VIDEO1_BIAS_SPEC>;
933#[doc = "PLL_VIDEO1 Bias Register"]
934pub mod pll_video1_bias;
935#[doc = "pll_ve_bias (rw) register accessor: PLL_VE Bias Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_ve_bias::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_ve_bias::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_ve_bias`] module"]
936pub type PLL_VE_BIAS = crate::Reg<pll_ve_bias::PLL_VE_BIAS_SPEC>;
937#[doc = "PLL_VE Bias Register"]
938pub mod pll_ve_bias;
939#[doc = "pll_audio0_bias (rw) register accessor: PLL_AUDIO0 Bias Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_audio0_bias::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_audio0_bias::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_audio0_bias`] module"]
940pub type PLL_AUDIO0_BIAS = crate::Reg<pll_audio0_bias::PLL_AUDIO0_BIAS_SPEC>;
941#[doc = "PLL_AUDIO0 Bias Register"]
942pub mod pll_audio0_bias;
943#[doc = "pll_audio1_bias (rw) register accessor: PLL_AUDIO1 Bias Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_audio1_bias::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_audio1_bias::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_audio1_bias`] module"]
944pub type PLL_AUDIO1_BIAS = crate::Reg<pll_audio1_bias::PLL_AUDIO1_BIAS_SPEC>;
945#[doc = "PLL_AUDIO1 Bias Register"]
946pub mod pll_audio1_bias;
947#[doc = "pll_cpu_tun (rw) register accessor: PLL_CPU Tuning Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_cpu_tun::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_cpu_tun::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_cpu_tun`] module"]
948pub type PLL_CPU_TUN = crate::Reg<pll_cpu_tun::PLL_CPU_TUN_SPEC>;
949#[doc = "PLL_CPU Tuning Register"]
950pub mod pll_cpu_tun;
951#[doc = "cpu_axi_cfg (rw) register accessor: CPU_AXI Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_axi_cfg::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_axi_cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_axi_cfg`] module"]
952pub type CPU_AXI_CFG = crate::Reg<cpu_axi_cfg::CPU_AXI_CFG_SPEC>;
953#[doc = "CPU_AXI Configuration Register"]
954pub mod cpu_axi_cfg;
955#[doc = "cpu_gating (rw) register accessor: CPU_GATING Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_gating::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_gating::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpu_gating`] module"]
956pub type CPU_GATING = crate::Reg<cpu_gating::CPU_GATING_SPEC>;
957#[doc = "CPU_GATING Configuration Register"]
958pub mod cpu_gating;
959#[doc = "psi_clk (rw) register accessor: PSI Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`psi_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`psi_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@psi_clk`] module"]
960pub type PSI_CLK = crate::Reg<psi_clk::PSI_CLK_SPEC>;
961#[doc = "PSI Clock Register"]
962pub mod psi_clk;
963#[doc = "apb_clk (rw) register accessor: APB Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`apb_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`apb_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@apb_clk`] module"]
964pub type APB_CLK = crate::Reg<apb_clk::APB_CLK_SPEC>;
965#[doc = "APB Clock Register"]
966pub mod apb_clk;
967#[doc = "mbus_clk (rw) register accessor: MBUS Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mbus_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mbus_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbus_clk`] module"]
968pub type MBUS_CLK = crate::Reg<mbus_clk::MBUS_CLK_SPEC>;
969#[doc = "MBUS Clock Register"]
970pub mod mbus_clk;
971#[doc = "de_clk (rw) register accessor: DE Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`de_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`de_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@de_clk`] module"]
972pub type DE_CLK = crate::Reg<de_clk::DE_CLK_SPEC>;
973#[doc = "DE Clock Register"]
974pub mod de_clk;
975#[doc = "de_bgr (rw) register accessor: DE Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`de_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`de_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@de_bgr`] module"]
976pub type DE_BGR = crate::Reg<de_bgr::DE_BGR_SPEC>;
977#[doc = "DE Bus Gating Reset Register"]
978pub mod de_bgr;
979#[doc = "di_clk (rw) register accessor: DI Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`di_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`di_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@di_clk`] module"]
980pub type DI_CLK = crate::Reg<di_clk::DI_CLK_SPEC>;
981#[doc = "DI Clock Register"]
982pub mod di_clk;
983#[doc = "di_bgr (rw) register accessor: DI Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`di_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`di_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@di_bgr`] module"]
984pub type DI_BGR = crate::Reg<di_bgr::DI_BGR_SPEC>;
985#[doc = "DI Bus Gating Reset Register"]
986pub mod di_bgr;
987#[doc = "g2d_clk (rw) register accessor: G2D Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`g2d_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`g2d_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@g2d_clk`] module"]
988pub type G2D_CLK = crate::Reg<g2d_clk::G2D_CLK_SPEC>;
989#[doc = "G2D Clock Register"]
990pub mod g2d_clk;
991#[doc = "g2d_bgr (rw) register accessor: G2D Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`g2d_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`g2d_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@g2d_bgr`] module"]
992pub type G2D_BGR = crate::Reg<g2d_bgr::G2D_BGR_SPEC>;
993#[doc = "G2D Bus Gating Reset Register"]
994pub mod g2d_bgr;
995#[doc = "ce_clk (rw) register accessor: CE Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ce_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ce_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ce_clk`] module"]
996pub type CE_CLK = crate::Reg<ce_clk::CE_CLK_SPEC>;
997#[doc = "CE Clock Register"]
998pub mod ce_clk;
999#[doc = "ce_bgr (rw) register accessor: CE Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ce_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ce_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ce_bgr`] module"]
1000pub type CE_BGR = crate::Reg<ce_bgr::CE_BGR_SPEC>;
1001#[doc = "CE Bus Gating Reset Register"]
1002pub mod ce_bgr;
1003#[doc = "ve_clk (rw) register accessor: VE Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ve_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ve_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ve_clk`] module"]
1004pub type VE_CLK = crate::Reg<ve_clk::VE_CLK_SPEC>;
1005#[doc = "VE Clock Register"]
1006pub mod ve_clk;
1007#[doc = "ve_bgr (rw) register accessor: VE Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ve_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ve_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ve_bgr`] module"]
1008pub type VE_BGR = crate::Reg<ve_bgr::VE_BGR_SPEC>;
1009#[doc = "VE Bus Gating Reset Register"]
1010pub mod ve_bgr;
1011#[doc = "dma_bgr (rw) register accessor: DMA Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dma_bgr`] module"]
1012pub type DMA_BGR = crate::Reg<dma_bgr::DMA_BGR_SPEC>;
1013#[doc = "DMA Bus Gating Reset Register"]
1014pub mod dma_bgr;
1015#[doc = "msgbox_bgr (rw) register accessor: MSGBOX Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msgbox_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msgbox_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msgbox_bgr`] module"]
1016pub type MSGBOX_BGR = crate::Reg<msgbox_bgr::MSGBOX_BGR_SPEC>;
1017#[doc = "MSGBOX Bus Gating Reset Register"]
1018pub mod msgbox_bgr;
1019#[doc = "spinlock_bgr (rw) register accessor: SPINLOCK Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spinlock_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spinlock_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spinlock_bgr`] module"]
1020pub type SPINLOCK_BGR = crate::Reg<spinlock_bgr::SPINLOCK_BGR_SPEC>;
1021#[doc = "SPINLOCK Bus Gating Reset Register"]
1022pub mod spinlock_bgr;
1023#[doc = "hstimer_bgr (rw) register accessor: HSTIMER Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hstimer_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hstimer_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hstimer_bgr`] module"]
1024pub type HSTIMER_BGR = crate::Reg<hstimer_bgr::HSTIMER_BGR_SPEC>;
1025#[doc = "HSTIMER Bus Gating Reset Register"]
1026pub mod hstimer_bgr;
1027#[doc = "avs_clk (rw) register accessor: AVS Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`avs_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`avs_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@avs_clk`] module"]
1028pub type AVS_CLK = crate::Reg<avs_clk::AVS_CLK_SPEC>;
1029#[doc = "AVS Clock Register"]
1030pub mod avs_clk;
1031#[doc = "dbgsys_bgr (rw) register accessor: DBGSYS Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbgsys_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbgsys_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dbgsys_bgr`] module"]
1032pub type DBGSYS_BGR = crate::Reg<dbgsys_bgr::DBGSYS_BGR_SPEC>;
1033#[doc = "DBGSYS Bus Gating Reset Register"]
1034pub mod dbgsys_bgr;
1035#[doc = "pwm_bgr (rw) register accessor: PWM Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwm_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwm_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm_bgr`] module"]
1036pub type PWM_BGR = crate::Reg<pwm_bgr::PWM_BGR_SPEC>;
1037#[doc = "PWM Bus Gating Reset Register"]
1038pub mod pwm_bgr;
1039#[doc = "iommu_bgr (rw) register accessor: IOMMU Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iommu_bgr`] module"]
1040pub type IOMMU_BGR = crate::Reg<iommu_bgr::IOMMU_BGR_SPEC>;
1041#[doc = "IOMMU Bus Gating Reset Register"]
1042pub mod iommu_bgr;
1043#[doc = "dram_clk (rw) register accessor: DRAM Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dram_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dram_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dram_clk`] module"]
1044pub type DRAM_CLK = crate::Reg<dram_clk::DRAM_CLK_SPEC>;
1045#[doc = "DRAM Clock Register"]
1046pub mod dram_clk;
1047#[doc = "mbus_mat_clk_gating (rw) register accessor: MBUS Master Clock Gating Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mbus_mat_clk_gating::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mbus_mat_clk_gating::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbus_mat_clk_gating`] module"]
1048pub type MBUS_MAT_CLK_GATING = crate::Reg<mbus_mat_clk_gating::MBUS_MAT_CLK_GATING_SPEC>;
1049#[doc = "MBUS Master Clock Gating Register"]
1050pub mod mbus_mat_clk_gating;
1051#[doc = "dram_bgr (rw) register accessor: DRAM Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dram_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dram_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dram_bgr`] module"]
1052pub type DRAM_BGR = crate::Reg<dram_bgr::DRAM_BGR_SPEC>;
1053#[doc = "DRAM Bus Gating Reset Register"]
1054pub mod dram_bgr;
1055#[doc = "smhc0_clk (rw) register accessor: SMHC0 Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc0_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc0_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc0_clk`] module"]
1056pub type SMHC0_CLK = crate::Reg<smhc0_clk::SMHC0_CLK_SPEC>;
1057#[doc = "SMHC0 Clock Register"]
1058pub mod smhc0_clk;
1059#[doc = "smhc1_clk (rw) register accessor: SMHC1 Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc1_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc1_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc1_clk`] module"]
1060pub type SMHC1_CLK = crate::Reg<smhc1_clk::SMHC1_CLK_SPEC>;
1061#[doc = "SMHC1 Clock Register"]
1062pub mod smhc1_clk;
1063#[doc = "smhc2_clk (rw) register accessor: SMHC2 Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc2_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc2_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc2_clk`] module"]
1064pub type SMHC2_CLK = crate::Reg<smhc2_clk::SMHC2_CLK_SPEC>;
1065#[doc = "SMHC2 Clock Register"]
1066pub mod smhc2_clk;
1067#[doc = "smhc_bgr (rw) register accessor: SMHC Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_bgr`] module"]
1068pub type SMHC_BGR = crate::Reg<smhc_bgr::SMHC_BGR_SPEC>;
1069#[doc = "SMHC Bus Gating Reset Register"]
1070pub mod smhc_bgr;
1071#[doc = "uart_bgr (rw) register accessor: UART Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`uart_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`uart_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uart_bgr`] module"]
1072pub type UART_BGR = crate::Reg<uart_bgr::UART_BGR_SPEC>;
1073#[doc = "UART Bus Gating Reset Register"]
1074pub mod uart_bgr;
1075#[doc = "twi_bgr (rw) register accessor: TWI Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`twi_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`twi_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@twi_bgr`] module"]
1076pub type TWI_BGR = crate::Reg<twi_bgr::TWI_BGR_SPEC>;
1077#[doc = "TWI Bus Gating Reset Register"]
1078pub mod twi_bgr;
1079#[doc = "spi0_clk (rw) register accessor: SPI0 Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi0_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi0_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi0_clk`] module"]
1080pub type SPI0_CLK = crate::Reg<spi0_clk::SPI0_CLK_SPEC>;
1081#[doc = "SPI0 Clock Register"]
1082pub mod spi0_clk;
1083#[doc = "spi1_clk (rw) register accessor: SPI1 Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi1_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi1_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi1_clk`] module"]
1084pub type SPI1_CLK = crate::Reg<spi1_clk::SPI1_CLK_SPEC>;
1085#[doc = "SPI1 Clock Register"]
1086pub mod spi1_clk;
1087#[doc = "spi_bgr (rw) register accessor: SPI Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@spi_bgr`] module"]
1088pub type SPI_BGR = crate::Reg<spi_bgr::SPI_BGR_SPEC>;
1089#[doc = "SPI Bus Gating Reset Register"]
1090pub mod spi_bgr;
1091#[doc = "emac_25m_clk (rw) register accessor: EMAC_25M Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emac_25m_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emac_25m_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emac_25m_clk`] module"]
1092pub type EMAC_25M_CLK = crate::Reg<emac_25m_clk::EMAC_25M_CLK_SPEC>;
1093#[doc = "EMAC_25M Clock Register"]
1094pub mod emac_25m_clk;
1095#[doc = "emac_bgr (rw) register accessor: EMAC Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emac_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emac_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emac_bgr`] module"]
1096pub type EMAC_BGR = crate::Reg<emac_bgr::EMAC_BGR_SPEC>;
1097#[doc = "EMAC Bus Gating Reset Register"]
1098pub mod emac_bgr;
1099#[doc = "irtx_clk (rw) register accessor: IRTX Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irtx_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irtx_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irtx_clk`] module"]
1100pub type IRTX_CLK = crate::Reg<irtx_clk::IRTX_CLK_SPEC>;
1101#[doc = "IRTX Clock Register"]
1102pub mod irtx_clk;
1103#[doc = "irtx_bgr (rw) register accessor: IRTX Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irtx_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irtx_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irtx_bgr`] module"]
1104pub type IRTX_BGR = crate::Reg<irtx_bgr::IRTX_BGR_SPEC>;
1105#[doc = "IRTX Bus Gating Reset Register"]
1106pub mod irtx_bgr;
1107#[doc = "gpadc_bgr (rw) register accessor: GPADC Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gpadc_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gpadc_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gpadc_bgr`] module"]
1108pub type GPADC_BGR = crate::Reg<gpadc_bgr::GPADC_BGR_SPEC>;
1109#[doc = "GPADC Bus Gating Reset Register"]
1110pub mod gpadc_bgr;
1111#[doc = "ths_bgr (rw) register accessor: THS Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ths_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ths_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ths_bgr`] module"]
1112pub type THS_BGR = crate::Reg<ths_bgr::THS_BGR_SPEC>;
1113#[doc = "THS Bus Gating Reset Register"]
1114pub mod ths_bgr;
1115#[doc = "i2s_clk (rw) register accessor: I2S Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2s_clk`] module"]
1116pub type I2S_CLK = crate::Reg<i2s_clk::I2S_CLK_SPEC>;
1117#[doc = "I2S Clock Register"]
1118pub mod i2s_clk;
1119#[doc = "i2s2_asrc_clk (rw) register accessor: I2S2_ASRC Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s2_asrc_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s2_asrc_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2s2_asrc_clk`] module"]
1120pub type I2S2_ASRC_CLK = crate::Reg<i2s2_asrc_clk::I2S2_ASRC_CLK_SPEC>;
1121#[doc = "I2S2_ASRC Clock Register"]
1122pub mod i2s2_asrc_clk;
1123#[doc = "i2s_bgr (rw) register accessor: I2S Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@i2s_bgr`] module"]
1124pub type I2S_BGR = crate::Reg<i2s_bgr::I2S_BGR_SPEC>;
1125#[doc = "I2S Bus Gating Reset Register"]
1126pub mod i2s_bgr;
1127#[doc = "owa_tx_clk (rw) register accessor: OWA_TX Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`owa_tx_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`owa_tx_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@owa_tx_clk`] module"]
1128pub type OWA_TX_CLK = crate::Reg<owa_tx_clk::OWA_TX_CLK_SPEC>;
1129#[doc = "OWA_TX Clock Register"]
1130pub mod owa_tx_clk;
1131#[doc = "owa_rx_clk (rw) register accessor: OWA_RX Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`owa_rx_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`owa_rx_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@owa_rx_clk`] module"]
1132pub type OWA_RX_CLK = crate::Reg<owa_rx_clk::OWA_RX_CLK_SPEC>;
1133#[doc = "OWA_RX Clock Register"]
1134pub mod owa_rx_clk;
1135#[doc = "owa_bgr (rw) register accessor: OWA Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`owa_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`owa_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@owa_bgr`] module"]
1136pub type OWA_BGR = crate::Reg<owa_bgr::OWA_BGR_SPEC>;
1137#[doc = "OWA Bus Gating Reset Register"]
1138pub mod owa_bgr;
1139#[doc = "dmic_clk (rw) register accessor: DMIC Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmic_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmic_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmic_clk`] module"]
1140pub type DMIC_CLK = crate::Reg<dmic_clk::DMIC_CLK_SPEC>;
1141#[doc = "DMIC Clock Register"]
1142pub mod dmic_clk;
1143#[doc = "dmic_bgr (rw) register accessor: DMIC Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmic_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmic_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmic_bgr`] module"]
1144pub type DMIC_BGR = crate::Reg<dmic_bgr::DMIC_BGR_SPEC>;
1145#[doc = "DMIC Bus Gating Reset Register"]
1146pub mod dmic_bgr;
1147#[doc = "audio_codec_dac_clk (rw) register accessor: AUDIO_CODEC_DAC Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_codec_dac_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_codec_dac_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@audio_codec_dac_clk`] module"]
1148pub type AUDIO_CODEC_DAC_CLK = crate::Reg<audio_codec_dac_clk::AUDIO_CODEC_DAC_CLK_SPEC>;
1149#[doc = "AUDIO_CODEC_DAC Clock Register"]
1150pub mod audio_codec_dac_clk;
1151#[doc = "audio_codec_adc_clk (rw) register accessor: AUDIO_CODEC_ADC Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_codec_adc_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_codec_adc_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@audio_codec_adc_clk`] module"]
1152pub type AUDIO_CODEC_ADC_CLK = crate::Reg<audio_codec_adc_clk::AUDIO_CODEC_ADC_CLK_SPEC>;
1153#[doc = "AUDIO_CODEC_ADC Clock Register"]
1154pub mod audio_codec_adc_clk;
1155#[doc = "audio_codec_bgr (rw) register accessor: AUDIO_CODEC Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_codec_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_codec_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@audio_codec_bgr`] module"]
1156pub type AUDIO_CODEC_BGR = crate::Reg<audio_codec_bgr::AUDIO_CODEC_BGR_SPEC>;
1157#[doc = "AUDIO_CODEC Bus Gating Reset Register"]
1158pub mod audio_codec_bgr;
1159#[doc = "usb0_clk (rw) register accessor: USB0 Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb0_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb0_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usb0_clk`] module"]
1160pub type USB0_CLK = crate::Reg<usb0_clk::USB0_CLK_SPEC>;
1161#[doc = "USB0 Clock Register"]
1162pub mod usb0_clk;
1163#[doc = "usb1_clk (rw) register accessor: USB1 Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb1_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb1_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usb1_clk`] module"]
1164pub type USB1_CLK = crate::Reg<usb1_clk::USB1_CLK_SPEC>;
1165#[doc = "USB1 Clock Register"]
1166pub mod usb1_clk;
1167#[doc = "usb_bgr (rw) register accessor: USB Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`usb_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`usb_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usb_bgr`] module"]
1168pub type USB_BGR = crate::Reg<usb_bgr::USB_BGR_SPEC>;
1169#[doc = "USB Bus Gating Reset Register"]
1170pub mod usb_bgr;
1171#[doc = "lradc_bgr (rw) register accessor: LRADC Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lradc_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lradc_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lradc_bgr`] module"]
1172pub type LRADC_BGR = crate::Reg<lradc_bgr::LRADC_BGR_SPEC>;
1173#[doc = "LRADC Bus Gating Reset Register"]
1174pub mod lradc_bgr;
1175#[doc = "dpss_top_bgr (rw) register accessor: DPSS_TOP Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dpss_top_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dpss_top_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dpss_top_bgr`] module"]
1176pub type DPSS_TOP_BGR = crate::Reg<dpss_top_bgr::DPSS_TOP_BGR_SPEC>;
1177#[doc = "DPSS_TOP Bus Gating Reset Register"]
1178pub mod dpss_top_bgr;
1179#[doc = "dsi_clk (rw) register accessor: DSI Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsi_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dsi_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dsi_clk`] module"]
1180pub type DSI_CLK = crate::Reg<dsi_clk::DSI_CLK_SPEC>;
1181#[doc = "DSI Clock Register"]
1182pub mod dsi_clk;
1183#[doc = "dsi_bgr (rw) register accessor: DSI Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsi_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dsi_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dsi_bgr`] module"]
1184pub type DSI_BGR = crate::Reg<dsi_bgr::DSI_BGR_SPEC>;
1185#[doc = "DSI Bus Gating Reset Register"]
1186pub mod dsi_bgr;
1187#[doc = "tconlcd_clk (rw) register accessor: TCONLCD Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tconlcd_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tconlcd_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tconlcd_clk`] module"]
1188pub type TCONLCD_CLK = crate::Reg<tconlcd_clk::TCONLCD_CLK_SPEC>;
1189#[doc = "TCONLCD Clock Register"]
1190pub mod tconlcd_clk;
1191#[doc = "tconlcd_bgr (rw) register accessor: TCONLCD Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tconlcd_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tconlcd_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tconlcd_bgr`] module"]
1192pub type TCONLCD_BGR = crate::Reg<tconlcd_bgr::TCONLCD_BGR_SPEC>;
1193#[doc = "TCONLCD Bus Gating Reset Register"]
1194pub mod tconlcd_bgr;
1195#[doc = "tcontv_clk (rw) register accessor: TCONTV Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcontv_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcontv_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcontv_clk`] module"]
1196pub type TCONTV_CLK = crate::Reg<tcontv_clk::TCONTV_CLK_SPEC>;
1197#[doc = "TCONTV Clock Register"]
1198pub mod tcontv_clk;
1199#[doc = "tcontv_bgr (rw) register accessor: TCONTV Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tcontv_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tcontv_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcontv_bgr`] module"]
1200pub type TCONTV_BGR = crate::Reg<tcontv_bgr::TCONTV_BGR_SPEC>;
1201#[doc = "TCONTV Bus Gating Reset Register"]
1202pub mod tcontv_bgr;
1203#[doc = "lvds_bgr (rw) register accessor: LVDS Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lvds_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lvds_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lvds_bgr`] module"]
1204pub type LVDS_BGR = crate::Reg<lvds_bgr::LVDS_BGR_SPEC>;
1205#[doc = "LVDS Bus Gating Reset Register"]
1206pub mod lvds_bgr;
1207#[doc = "tve_clk (rw) register accessor: TVE Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tve_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tve_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tve_clk`] module"]
1208pub type TVE_CLK = crate::Reg<tve_clk::TVE_CLK_SPEC>;
1209#[doc = "TVE Clock Register"]
1210pub mod tve_clk;
1211#[doc = "tve_bgr (rw) register accessor: TVE Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tve_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tve_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tve_bgr`] module"]
1212pub type TVE_BGR = crate::Reg<tve_bgr::TVE_BGR_SPEC>;
1213#[doc = "TVE Bus Gating Reset Register"]
1214pub mod tve_bgr;
1215#[doc = "tvd_clk (rw) register accessor: TVD Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tvd_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tvd_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tvd_clk`] module"]
1216pub type TVD_CLK = crate::Reg<tvd_clk::TVD_CLK_SPEC>;
1217#[doc = "TVD Clock Register"]
1218pub mod tvd_clk;
1219#[doc = "tvd_bgr (rw) register accessor: TVD Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tvd_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tvd_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tvd_bgr`] module"]
1220pub type TVD_BGR = crate::Reg<tvd_bgr::TVD_BGR_SPEC>;
1221#[doc = "TVD Bus Gating Reset Register"]
1222pub mod tvd_bgr;
1223#[doc = "ledc_clk (rw) register accessor: LEDC Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ledc_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ledc_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ledc_clk`] module"]
1224pub type LEDC_CLK = crate::Reg<ledc_clk::LEDC_CLK_SPEC>;
1225#[doc = "LEDC Clock Register"]
1226pub mod ledc_clk;
1227#[doc = "ledc_bgr (rw) register accessor: LEDC Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ledc_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ledc_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ledc_bgr`] module"]
1228pub type LEDC_BGR = crate::Reg<ledc_bgr::LEDC_BGR_SPEC>;
1229#[doc = "LEDC Bus Gating Reset Register"]
1230pub mod ledc_bgr;
1231#[doc = "csi_clk (rw) register accessor: CSI Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csi_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csi_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csi_clk`] module"]
1232pub type CSI_CLK = crate::Reg<csi_clk::CSI_CLK_SPEC>;
1233#[doc = "CSI Clock Register"]
1234pub mod csi_clk;
1235#[doc = "csi_master_clk (rw) register accessor: CSI Master Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csi_master_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csi_master_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csi_master_clk`] module"]
1236pub type CSI_MASTER_CLK = crate::Reg<csi_master_clk::CSI_MASTER_CLK_SPEC>;
1237#[doc = "CSI Master Clock Register"]
1238pub mod csi_master_clk;
1239#[doc = "csi_bgr (rw) register accessor: CSI Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`csi_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`csi_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@csi_bgr`] module"]
1240pub type CSI_BGR = crate::Reg<csi_bgr::CSI_BGR_SPEC>;
1241#[doc = "CSI Bus Gating Reset Register"]
1242pub mod csi_bgr;
1243#[doc = "tpadc_clk (rw) register accessor: TPADC Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tpadc_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tpadc_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tpadc_clk`] module"]
1244pub type TPADC_CLK = crate::Reg<tpadc_clk::TPADC_CLK_SPEC>;
1245#[doc = "TPADC Clock Register"]
1246pub mod tpadc_clk;
1247#[doc = "tpadc_bgr (rw) register accessor: TPADC Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tpadc_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tpadc_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tpadc_bgr`] module"]
1248pub type TPADC_BGR = crate::Reg<tpadc_bgr::TPADC_BGR_SPEC>;
1249#[doc = "TPADC Bus Gating Reset Register"]
1250pub mod tpadc_bgr;
1251#[doc = "dsp_clk (rw) register accessor: DSP Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsp_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dsp_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dsp_clk`] module"]
1252pub type DSP_CLK = crate::Reg<dsp_clk::DSP_CLK_SPEC>;
1253#[doc = "DSP Clock Register"]
1254pub mod dsp_clk;
1255#[doc = "dsp_bgr (rw) register accessor: DSP Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsp_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dsp_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dsp_bgr`] module"]
1256pub type DSP_BGR = crate::Reg<dsp_bgr::DSP_BGR_SPEC>;
1257#[doc = "DSP Bus Gating Reset Register"]
1258pub mod dsp_bgr;
1259#[doc = "riscv_clk (rw) register accessor: RISC-V Clock Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`riscv_clk::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`riscv_clk::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@riscv_clk`] module"]
1260pub type RISCV_CLK = crate::Reg<riscv_clk::RISCV_CLK_SPEC>;
1261#[doc = "RISC-V Clock Register"]
1262pub mod riscv_clk;
1263#[doc = "riscv_gating (rw) register accessor: RISC-V GATING Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`riscv_gating::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`riscv_gating::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@riscv_gating`] module"]
1264pub type RISCV_GATING = crate::Reg<riscv_gating::RISCV_GATING_SPEC>;
1265#[doc = "RISC-V GATING Configuration Register"]
1266pub mod riscv_gating;
1267#[doc = "riscv_cfg_bgr (rw) register accessor: RISC-V_CFG Bus Gating Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`riscv_cfg_bgr::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`riscv_cfg_bgr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@riscv_cfg_bgr`] module"]
1268pub type RISCV_CFG_BGR = crate::Reg<riscv_cfg_bgr::RISCV_CFG_BGR_SPEC>;
1269#[doc = "RISC-V_CFG Bus Gating Reset Register"]
1270pub mod riscv_cfg_bgr;
1271#[doc = "pll_lock_dbg_ctrl (rw) register accessor: PLL Lock Debug Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pll_lock_dbg_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pll_lock_dbg_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pll_lock_dbg_ctrl`] module"]
1272pub type PLL_LOCK_DBG_CTRL = crate::Reg<pll_lock_dbg_ctrl::PLL_LOCK_DBG_CTRL_SPEC>;
1273#[doc = "PLL Lock Debug Control Register"]
1274pub mod pll_lock_dbg_ctrl;
1275#[doc = "fre_det_ctrl (rw) register accessor: Frequency Detect Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fre_det_ctrl::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fre_det_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fre_det_ctrl`] module"]
1276pub type FRE_DET_CTRL = crate::Reg<fre_det_ctrl::FRE_DET_CTRL_SPEC>;
1277#[doc = "Frequency Detect Control Register"]
1278pub mod fre_det_ctrl;
1279#[doc = "fre_up_lim (rw) register accessor: Frequency Up Limit Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fre_up_lim::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fre_up_lim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fre_up_lim`] module"]
1280pub type FRE_UP_LIM = crate::Reg<fre_up_lim::FRE_UP_LIM_SPEC>;
1281#[doc = "Frequency Up Limit Register"]
1282pub mod fre_up_lim;
1283#[doc = "fre_down_lim (rw) register accessor: Frequency Down Limit Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fre_down_lim::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fre_down_lim::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fre_down_lim`] module"]
1284pub type FRE_DOWN_LIM = crate::Reg<fre_down_lim::FRE_DOWN_LIM_SPEC>;
1285#[doc = "Frequency Down Limit Register"]
1286pub mod fre_down_lim;
1287#[doc = "ccu_fan_gate (rw) register accessor: CCU FANOUT CLOCK GATE Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccu_fan_gate::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccu_fan_gate::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccu_fan_gate`] module"]
1288pub type CCU_FAN_GATE = crate::Reg<ccu_fan_gate::CCU_FAN_GATE_SPEC>;
1289#[doc = "CCU FANOUT CLOCK GATE Register"]
1290pub mod ccu_fan_gate;
1291#[doc = "clk27m_fan (rw) register accessor: CLK27M FANOUT Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk27m_fan::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk27m_fan::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk27m_fan`] module"]
1292pub type CLK27M_FAN = crate::Reg<clk27m_fan::CLK27M_FAN_SPEC>;
1293#[doc = "CLK27M FANOUT Register"]
1294pub mod clk27m_fan;
1295#[doc = "pclk_fan (rw) register accessor: PCLK FANOUT Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pclk_fan::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pclk_fan::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pclk_fan`] module"]
1296pub type PCLK_FAN = crate::Reg<pclk_fan::PCLK_FAN_SPEC>;
1297#[doc = "PCLK FANOUT Register"]
1298pub mod pclk_fan;
1299#[doc = "ccu_fan (rw) register accessor: CCU FANOUT Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccu_fan::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccu_fan::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccu_fan`] module"]
1300pub type CCU_FAN = crate::Reg<ccu_fan::CCU_FAN_SPEC>;
1301#[doc = "CCU FANOUT Register"]
1302pub mod ccu_fan;