d1_pac/uart/
halt.rs

1#[doc = "Register `halt` reader"]
2pub type R = crate::R<HALT_SPEC>;
3#[doc = "Register `halt` writer"]
4pub type W = crate::W<HALT_SPEC>;
5#[doc = "Field `halt_tx` reader - "]
6pub type HALT_TX_R = crate::BitReader<HALT_TX_A>;
7#[doc = "\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum HALT_TX_A {
10    #[doc = "0: `0`"]
11    DISABLED = 0,
12    #[doc = "1: `1`"]
13    ENABLED = 1,
14}
15impl From<HALT_TX_A> for bool {
16    #[inline(always)]
17    fn from(variant: HALT_TX_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl HALT_TX_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> HALT_TX_A {
25        match self.bits {
26            false => HALT_TX_A::DISABLED,
27            true => HALT_TX_A::ENABLED,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_disabled(&self) -> bool {
33        *self == HALT_TX_A::DISABLED
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_enabled(&self) -> bool {
38        *self == HALT_TX_A::ENABLED
39    }
40}
41#[doc = "Field `halt_tx` writer - "]
42pub type HALT_TX_W<'a, REG> = crate::BitWriter<'a, REG, HALT_TX_A>;
43impl<'a, REG> HALT_TX_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn disabled(self) -> &'a mut crate::W<REG> {
50        self.variant(HALT_TX_A::DISABLED)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn enabled(self) -> &'a mut crate::W<REG> {
55        self.variant(HALT_TX_A::ENABLED)
56    }
57}
58#[doc = "Field `chcfg_at_busy` reader - "]
59pub type CHCFG_AT_BUSY_R = crate::BitReader<CHCFG_AT_BUSY_A>;
60#[doc = "\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum CHCFG_AT_BUSY_A {
63    #[doc = "0: `0`"]
64    DISABLE = 0,
65    #[doc = "1: `1`"]
66    ENABLE = 1,
67}
68impl From<CHCFG_AT_BUSY_A> for bool {
69    #[inline(always)]
70    fn from(variant: CHCFG_AT_BUSY_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl CHCFG_AT_BUSY_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> CHCFG_AT_BUSY_A {
78        match self.bits {
79            false => CHCFG_AT_BUSY_A::DISABLE,
80            true => CHCFG_AT_BUSY_A::ENABLE,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_disable(&self) -> bool {
86        *self == CHCFG_AT_BUSY_A::DISABLE
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_enable(&self) -> bool {
91        *self == CHCFG_AT_BUSY_A::ENABLE
92    }
93}
94#[doc = "Field `chcfg_at_busy` writer - "]
95pub type CHCFG_AT_BUSY_W<'a, REG> = crate::BitWriter<'a, REG, CHCFG_AT_BUSY_A>;
96impl<'a, REG> CHCFG_AT_BUSY_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn disable(self) -> &'a mut crate::W<REG> {
103        self.variant(CHCFG_AT_BUSY_A::DISABLE)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn enable(self) -> &'a mut crate::W<REG> {
108        self.variant(CHCFG_AT_BUSY_A::ENABLE)
109    }
110}
111#[doc = "Field `change_update` reader - "]
112pub type CHANGE_UPDATE_R = crate::BitReader<CHANGE_UPDATE_A>;
113#[doc = "\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum CHANGE_UPDATE_A {
116    #[doc = "0: `0`"]
117    FINISHED = 0,
118    #[doc = "1: `1`"]
119    UPDATE_TRIGGER = 1,
120}
121impl From<CHANGE_UPDATE_A> for bool {
122    #[inline(always)]
123    fn from(variant: CHANGE_UPDATE_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl CHANGE_UPDATE_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> CHANGE_UPDATE_A {
131        match self.bits {
132            false => CHANGE_UPDATE_A::FINISHED,
133            true => CHANGE_UPDATE_A::UPDATE_TRIGGER,
134        }
135    }
136    #[doc = "`0`"]
137    #[inline(always)]
138    pub fn is_finished(&self) -> bool {
139        *self == CHANGE_UPDATE_A::FINISHED
140    }
141    #[doc = "`1`"]
142    #[inline(always)]
143    pub fn is_update_trigger(&self) -> bool {
144        *self == CHANGE_UPDATE_A::UPDATE_TRIGGER
145    }
146}
147#[doc = "Field `change_update` writer - "]
148pub type CHANGE_UPDATE_W<'a, REG> = crate::BitWriter<'a, REG, CHANGE_UPDATE_A>;
149impl<'a, REG> CHANGE_UPDATE_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "`0`"]
154    #[inline(always)]
155    pub fn finished(self) -> &'a mut crate::W<REG> {
156        self.variant(CHANGE_UPDATE_A::FINISHED)
157    }
158    #[doc = "`1`"]
159    #[inline(always)]
160    pub fn update_trigger(self) -> &'a mut crate::W<REG> {
161        self.variant(CHANGE_UPDATE_A::UPDATE_TRIGGER)
162    }
163}
164#[doc = "Field `sir_tx_invert` reader - SIR TX Pulse Polarity Invert"]
165pub type SIR_TX_INVERT_R = crate::BitReader<SIR_TX_INVERT_A>;
166#[doc = "SIR TX Pulse Polarity Invert\n\nValue on reset: 0"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum SIR_TX_INVERT_A {
169    #[doc = "0: `0`"]
170    NOT_INVERT = 0,
171    #[doc = "1: `1`"]
172    INVERT = 1,
173}
174impl From<SIR_TX_INVERT_A> for bool {
175    #[inline(always)]
176    fn from(variant: SIR_TX_INVERT_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl SIR_TX_INVERT_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> SIR_TX_INVERT_A {
184        match self.bits {
185            false => SIR_TX_INVERT_A::NOT_INVERT,
186            true => SIR_TX_INVERT_A::INVERT,
187        }
188    }
189    #[doc = "`0`"]
190    #[inline(always)]
191    pub fn is_not_invert(&self) -> bool {
192        *self == SIR_TX_INVERT_A::NOT_INVERT
193    }
194    #[doc = "`1`"]
195    #[inline(always)]
196    pub fn is_invert(&self) -> bool {
197        *self == SIR_TX_INVERT_A::INVERT
198    }
199}
200#[doc = "Field `sir_tx_invert` writer - SIR TX Pulse Polarity Invert"]
201pub type SIR_TX_INVERT_W<'a, REG> = crate::BitWriter<'a, REG, SIR_TX_INVERT_A>;
202impl<'a, REG> SIR_TX_INVERT_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "`0`"]
207    #[inline(always)]
208    pub fn not_invert(self) -> &'a mut crate::W<REG> {
209        self.variant(SIR_TX_INVERT_A::NOT_INVERT)
210    }
211    #[doc = "`1`"]
212    #[inline(always)]
213    pub fn invert(self) -> &'a mut crate::W<REG> {
214        self.variant(SIR_TX_INVERT_A::INVERT)
215    }
216}
217#[doc = "Field `sir_rx_invert` reader - SIR RX Pulse Polarity Invert"]
218pub type SIR_RX_INVERT_R = crate::BitReader<SIR_RX_INVERT_A>;
219#[doc = "SIR RX Pulse Polarity Invert\n\nValue on reset: 0"]
220#[derive(Clone, Copy, Debug, PartialEq, Eq)]
221pub enum SIR_RX_INVERT_A {
222    #[doc = "0: `0`"]
223    NOT_INVERT = 0,
224    #[doc = "1: `1`"]
225    INVERT = 1,
226}
227impl From<SIR_RX_INVERT_A> for bool {
228    #[inline(always)]
229    fn from(variant: SIR_RX_INVERT_A) -> Self {
230        variant as u8 != 0
231    }
232}
233impl SIR_RX_INVERT_R {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> SIR_RX_INVERT_A {
237        match self.bits {
238            false => SIR_RX_INVERT_A::NOT_INVERT,
239            true => SIR_RX_INVERT_A::INVERT,
240        }
241    }
242    #[doc = "`0`"]
243    #[inline(always)]
244    pub fn is_not_invert(&self) -> bool {
245        *self == SIR_RX_INVERT_A::NOT_INVERT
246    }
247    #[doc = "`1`"]
248    #[inline(always)]
249    pub fn is_invert(&self) -> bool {
250        *self == SIR_RX_INVERT_A::INVERT
251    }
252}
253#[doc = "Field `sir_rx_invert` writer - SIR RX Pulse Polarity Invert"]
254pub type SIR_RX_INVERT_W<'a, REG> = crate::BitWriter<'a, REG, SIR_RX_INVERT_A>;
255impl<'a, REG> SIR_RX_INVERT_W<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258{
259    #[doc = "`0`"]
260    #[inline(always)]
261    pub fn not_invert(self) -> &'a mut crate::W<REG> {
262        self.variant(SIR_RX_INVERT_A::NOT_INVERT)
263    }
264    #[doc = "`1`"]
265    #[inline(always)]
266    pub fn invert(self) -> &'a mut crate::W<REG> {
267        self.variant(SIR_RX_INVERT_A::INVERT)
268    }
269}
270#[doc = "Field `dma_pte_rx` reader - The Transmission of RX_DRQ"]
271pub type DMA_PTE_RX_R = crate::BitReader;
272#[doc = "Field `dma_pte_rx` writer - The Transmission of RX_DRQ"]
273pub type DMA_PTE_RX_W<'a, REG> = crate::BitWriter<'a, REG>;
274#[doc = "Field `pte` reader - The sending of TX_REQ"]
275pub type PTE_R = crate::BitReader;
276#[doc = "Field `pte` writer - The sending of TX_REQ"]
277pub type PTE_W<'a, REG> = crate::BitWriter<'a, REG>;
278impl R {
279    #[doc = "Bit 0"]
280    #[inline(always)]
281    pub fn halt_tx(&self) -> HALT_TX_R {
282        HALT_TX_R::new((self.bits & 1) != 0)
283    }
284    #[doc = "Bit 1"]
285    #[inline(always)]
286    pub fn chcfg_at_busy(&self) -> CHCFG_AT_BUSY_R {
287        CHCFG_AT_BUSY_R::new(((self.bits >> 1) & 1) != 0)
288    }
289    #[doc = "Bit 2"]
290    #[inline(always)]
291    pub fn change_update(&self) -> CHANGE_UPDATE_R {
292        CHANGE_UPDATE_R::new(((self.bits >> 2) & 1) != 0)
293    }
294    #[doc = "Bit 4 - SIR TX Pulse Polarity Invert"]
295    #[inline(always)]
296    pub fn sir_tx_invert(&self) -> SIR_TX_INVERT_R {
297        SIR_TX_INVERT_R::new(((self.bits >> 4) & 1) != 0)
298    }
299    #[doc = "Bit 5 - SIR RX Pulse Polarity Invert"]
300    #[inline(always)]
301    pub fn sir_rx_invert(&self) -> SIR_RX_INVERT_R {
302        SIR_RX_INVERT_R::new(((self.bits >> 5) & 1) != 0)
303    }
304    #[doc = "Bit 6 - The Transmission of RX_DRQ"]
305    #[inline(always)]
306    pub fn dma_pte_rx(&self) -> DMA_PTE_RX_R {
307        DMA_PTE_RX_R::new(((self.bits >> 6) & 1) != 0)
308    }
309    #[doc = "Bit 7 - The sending of TX_REQ"]
310    #[inline(always)]
311    pub fn pte(&self) -> PTE_R {
312        PTE_R::new(((self.bits >> 7) & 1) != 0)
313    }
314}
315impl W {
316    #[doc = "Bit 0"]
317    #[inline(always)]
318    #[must_use]
319    pub fn halt_tx(&mut self) -> HALT_TX_W<HALT_SPEC> {
320        HALT_TX_W::new(self, 0)
321    }
322    #[doc = "Bit 1"]
323    #[inline(always)]
324    #[must_use]
325    pub fn chcfg_at_busy(&mut self) -> CHCFG_AT_BUSY_W<HALT_SPEC> {
326        CHCFG_AT_BUSY_W::new(self, 1)
327    }
328    #[doc = "Bit 2"]
329    #[inline(always)]
330    #[must_use]
331    pub fn change_update(&mut self) -> CHANGE_UPDATE_W<HALT_SPEC> {
332        CHANGE_UPDATE_W::new(self, 2)
333    }
334    #[doc = "Bit 4 - SIR TX Pulse Polarity Invert"]
335    #[inline(always)]
336    #[must_use]
337    pub fn sir_tx_invert(&mut self) -> SIR_TX_INVERT_W<HALT_SPEC> {
338        SIR_TX_INVERT_W::new(self, 4)
339    }
340    #[doc = "Bit 5 - SIR RX Pulse Polarity Invert"]
341    #[inline(always)]
342    #[must_use]
343    pub fn sir_rx_invert(&mut self) -> SIR_RX_INVERT_W<HALT_SPEC> {
344        SIR_RX_INVERT_W::new(self, 5)
345    }
346    #[doc = "Bit 6 - The Transmission of RX_DRQ"]
347    #[inline(always)]
348    #[must_use]
349    pub fn dma_pte_rx(&mut self) -> DMA_PTE_RX_W<HALT_SPEC> {
350        DMA_PTE_RX_W::new(self, 6)
351    }
352    #[doc = "Bit 7 - The sending of TX_REQ"]
353    #[inline(always)]
354    #[must_use]
355    pub fn pte(&mut self) -> PTE_W<HALT_SPEC> {
356        PTE_W::new(self, 7)
357    }
358    #[doc = r" Writes raw bits to the register."]
359    #[doc = r""]
360    #[doc = r" # Safety"]
361    #[doc = r""]
362    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
363    #[inline(always)]
364    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
365        self.bits = bits;
366        self
367    }
368}
369#[doc = "UART Halt TX Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`halt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`halt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
370pub struct HALT_SPEC;
371impl crate::RegisterSpec for HALT_SPEC {
372    type Ux = u32;
373}
374#[doc = "`read()` method returns [`halt::R`](R) reader structure"]
375impl crate::Readable for HALT_SPEC {}
376#[doc = "`write(|w| ..)` method takes [`halt::W`](W) writer structure"]
377impl crate::Writable for HALT_SPEC {
378    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
379    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
380}
381#[doc = "`reset()` method sets halt to value 0"]
382impl crate::Resettable for HALT_SPEC {
383    const RESET_VALUE: Self::Ux = 0;
384}
d1_pac/uart/halt.rs

d1_pac/uart/
halt.rs
