d1_pac/uart/
fcc.rs

1#[doc = "Register `fcc` reader"]
2pub type R = crate::R<FCC_SPEC>;
3#[doc = "Register `fcc` writer"]
4pub type W = crate::W<FCC_SPEC>;
5#[doc = "Field `rx_fifo_clock_enable` reader - "]
6pub type RX_FIFO_CLOCK_ENABLE_R = crate::BitReader<RX_FIFO_CLOCK_ENABLE_A>;
7#[doc = "\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum RX_FIFO_CLOCK_ENABLE_A {
10    #[doc = "0: `0`"]
11    DISABLE = 0,
12    #[doc = "1: `1`"]
13    ENABLE = 1,
14}
15impl From<RX_FIFO_CLOCK_ENABLE_A> for bool {
16    #[inline(always)]
17    fn from(variant: RX_FIFO_CLOCK_ENABLE_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl RX_FIFO_CLOCK_ENABLE_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> RX_FIFO_CLOCK_ENABLE_A {
25        match self.bits {
26            false => RX_FIFO_CLOCK_ENABLE_A::DISABLE,
27            true => RX_FIFO_CLOCK_ENABLE_A::ENABLE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == RX_FIFO_CLOCK_ENABLE_A::DISABLE
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == RX_FIFO_CLOCK_ENABLE_A::ENABLE
39    }
40}
41#[doc = "Field `rx_fifo_clock_enable` writer - "]
42pub type RX_FIFO_CLOCK_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, RX_FIFO_CLOCK_ENABLE_A>;
43impl<'a, REG> RX_FIFO_CLOCK_ENABLE_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(RX_FIFO_CLOCK_ENABLE_A::DISABLE)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(RX_FIFO_CLOCK_ENABLE_A::ENABLE)
56    }
57}
58#[doc = "Field `tx_fifo_clock_enable` reader - "]
59pub type TX_FIFO_CLOCK_ENABLE_R = crate::BitReader<TX_FIFO_CLOCK_ENABLE_A>;
60#[doc = "\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum TX_FIFO_CLOCK_ENABLE_A {
63    #[doc = "0: `0`"]
64    DISABLE = 0,
65    #[doc = "1: `1`"]
66    ENABLE = 1,
67}
68impl From<TX_FIFO_CLOCK_ENABLE_A> for bool {
69    #[inline(always)]
70    fn from(variant: TX_FIFO_CLOCK_ENABLE_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl TX_FIFO_CLOCK_ENABLE_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> TX_FIFO_CLOCK_ENABLE_A {
78        match self.bits {
79            false => TX_FIFO_CLOCK_ENABLE_A::DISABLE,
80            true => TX_FIFO_CLOCK_ENABLE_A::ENABLE,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_disable(&self) -> bool {
86        *self == TX_FIFO_CLOCK_ENABLE_A::DISABLE
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_enable(&self) -> bool {
91        *self == TX_FIFO_CLOCK_ENABLE_A::ENABLE
92    }
93}
94#[doc = "Field `tx_fifo_clock_enable` writer - "]
95pub type TX_FIFO_CLOCK_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, TX_FIFO_CLOCK_ENABLE_A>;
96impl<'a, REG> TX_FIFO_CLOCK_ENABLE_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn disable(self) -> &'a mut crate::W<REG> {
103        self.variant(TX_FIFO_CLOCK_ENABLE_A::DISABLE)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn enable(self) -> &'a mut crate::W<REG> {
108        self.variant(TX_FIFO_CLOCK_ENABLE_A::ENABLE)
109    }
110}
111#[doc = "Field `rx_fifo_clock_mode` reader - "]
112pub type RX_FIFO_CLOCK_MODE_R = crate::BitReader<RX_FIFO_CLOCK_MODE_A>;
113#[doc = "\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum RX_FIFO_CLOCK_MODE_A {
116    #[doc = "0: Sync mode, writing/reading clocks use apb clock"]
117    WR_APB = 0,
118    #[doc = "1: Sync mode, writing clock uses apb clock, reading clock uses ahb clock"]
119    W_APB_R_AHB = 1,
120}
121impl From<RX_FIFO_CLOCK_MODE_A> for bool {
122    #[inline(always)]
123    fn from(variant: RX_FIFO_CLOCK_MODE_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl RX_FIFO_CLOCK_MODE_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> RX_FIFO_CLOCK_MODE_A {
131        match self.bits {
132            false => RX_FIFO_CLOCK_MODE_A::WR_APB,
133            true => RX_FIFO_CLOCK_MODE_A::W_APB_R_AHB,
134        }
135    }
136    #[doc = "Sync mode, writing/reading clocks use apb clock"]
137    #[inline(always)]
138    pub fn is_wr_apb(&self) -> bool {
139        *self == RX_FIFO_CLOCK_MODE_A::WR_APB
140    }
141    #[doc = "Sync mode, writing clock uses apb clock, reading clock uses ahb clock"]
142    #[inline(always)]
143    pub fn is_w_apb_r_ahb(&self) -> bool {
144        *self == RX_FIFO_CLOCK_MODE_A::W_APB_R_AHB
145    }
146}
147#[doc = "Field `rx_fifo_clock_mode` writer - "]
148pub type RX_FIFO_CLOCK_MODE_W<'a, REG> = crate::BitWriter<'a, REG, RX_FIFO_CLOCK_MODE_A>;
149impl<'a, REG> RX_FIFO_CLOCK_MODE_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "Sync mode, writing/reading clocks use apb clock"]
154    #[inline(always)]
155    pub fn wr_apb(self) -> &'a mut crate::W<REG> {
156        self.variant(RX_FIFO_CLOCK_MODE_A::WR_APB)
157    }
158    #[doc = "Sync mode, writing clock uses apb clock, reading clock uses ahb clock"]
159    #[inline(always)]
160    pub fn w_apb_r_ahb(self) -> &'a mut crate::W<REG> {
161        self.variant(RX_FIFO_CLOCK_MODE_A::W_APB_R_AHB)
162    }
163}
164#[doc = "Field `fifo_depth` reader - "]
165pub type FIFO_DEPTH_R = crate::FieldReader<u32>;
166impl R {
167    #[doc = "Bit 0"]
168    #[inline(always)]
169    pub fn rx_fifo_clock_enable(&self) -> RX_FIFO_CLOCK_ENABLE_R {
170        RX_FIFO_CLOCK_ENABLE_R::new((self.bits & 1) != 0)
171    }
172    #[doc = "Bit 1"]
173    #[inline(always)]
174    pub fn tx_fifo_clock_enable(&self) -> TX_FIFO_CLOCK_ENABLE_R {
175        TX_FIFO_CLOCK_ENABLE_R::new(((self.bits >> 1) & 1) != 0)
176    }
177    #[doc = "Bit 2"]
178    #[inline(always)]
179    pub fn rx_fifo_clock_mode(&self) -> RX_FIFO_CLOCK_MODE_R {
180        RX_FIFO_CLOCK_MODE_R::new(((self.bits >> 2) & 1) != 0)
181    }
182    #[doc = "Bits 8:31"]
183    #[inline(always)]
184    pub fn fifo_depth(&self) -> FIFO_DEPTH_R {
185        FIFO_DEPTH_R::new((self.bits >> 8) & 0x00ff_ffff)
186    }
187}
188impl W {
189    #[doc = "Bit 0"]
190    #[inline(always)]
191    #[must_use]
192    pub fn rx_fifo_clock_enable(&mut self) -> RX_FIFO_CLOCK_ENABLE_W<FCC_SPEC> {
193        RX_FIFO_CLOCK_ENABLE_W::new(self, 0)
194    }
195    #[doc = "Bit 1"]
196    #[inline(always)]
197    #[must_use]
198    pub fn tx_fifo_clock_enable(&mut self) -> TX_FIFO_CLOCK_ENABLE_W<FCC_SPEC> {
199        TX_FIFO_CLOCK_ENABLE_W::new(self, 1)
200    }
201    #[doc = "Bit 2"]
202    #[inline(always)]
203    #[must_use]
204    pub fn rx_fifo_clock_mode(&mut self) -> RX_FIFO_CLOCK_MODE_W<FCC_SPEC> {
205        RX_FIFO_CLOCK_MODE_W::new(self, 2)
206    }
207    #[doc = r" Writes raw bits to the register."]
208    #[doc = r""]
209    #[doc = r" # Safety"]
210    #[doc = r""]
211    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
212    #[inline(always)]
213    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
214        self.bits = bits;
215        self
216    }
217}
218#[doc = "UART FIFO Clock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
219pub struct FCC_SPEC;
220impl crate::RegisterSpec for FCC_SPEC {
221    type Ux = u32;
222}
223#[doc = "`read()` method returns [`fcc::R`](R) reader structure"]
224impl crate::Readable for FCC_SPEC {}
225#[doc = "`write(|w| ..)` method takes [`fcc::W`](W) writer structure"]
226impl crate::Writable for FCC_SPEC {
227    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
228    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
229}
230#[doc = "`reset()` method sets fcc to value 0"]
231impl crate::Resettable for FCC_SPEC {
232    const RESET_VALUE: Self::Ux = 0;
233}
d1_pac/uart/fcc.rs

d1_pac/uart/
fcc.rs
