d1_pac/tpadc/
tp_int_fifo_stat.rs

1#[doc = "Register `tp_int_fifo_stat` reader"]
2pub type R = crate::R<TP_INT_FIFO_STAT_SPEC>;
3#[doc = "Register `tp_int_fifo_stat` writer"]
4pub type W = crate::W<TP_INT_FIFO_STAT_SPEC>;
5#[doc = "Field `tp_down_pending` reader - TP First Touch (Stylus DOWN) Pending"]
6pub type TP_DOWN_PENDING_R = crate::BitReader<TP_DOWN_PENDING_A>;
7#[doc = "TP First Touch (Stylus DOWN) Pending\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum TP_DOWN_PENDING_A {
10    #[doc = "0: `0`"]
11    NO_PENDING = 0,
12    #[doc = "1: `1`"]
13    PENDING = 1,
14}
15impl From<TP_DOWN_PENDING_A> for bool {
16    #[inline(always)]
17    fn from(variant: TP_DOWN_PENDING_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl TP_DOWN_PENDING_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> TP_DOWN_PENDING_A {
25        match self.bits {
26            false => TP_DOWN_PENDING_A::NO_PENDING,
27            true => TP_DOWN_PENDING_A::PENDING,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_no_pending(&self) -> bool {
33        *self == TP_DOWN_PENDING_A::NO_PENDING
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_pending(&self) -> bool {
38        *self == TP_DOWN_PENDING_A::PENDING
39    }
40}
41#[doc = "Field `tp_down_pending` writer - TP First Touch (Stylus DOWN) Pending"]
42pub type TP_DOWN_PENDING_W<'a, REG> = crate::BitWriter1C<'a, REG, TP_DOWN_PENDING_A>;
43impl<'a, REG> TP_DOWN_PENDING_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn no_pending(self) -> &'a mut crate::W<REG> {
50        self.variant(TP_DOWN_PENDING_A::NO_PENDING)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn pending(self) -> &'a mut crate::W<REG> {
55        self.variant(TP_DOWN_PENDING_A::PENDING)
56    }
57}
58#[doc = "Field `tp_up_pending` reader - TP Last Touch (Stylus UP) Pending"]
59pub type TP_UP_PENDING_R = crate::BitReader<TP_UP_PENDING_A>;
60#[doc = "TP Last Touch (Stylus UP) Pending\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum TP_UP_PENDING_A {
63    #[doc = "0: `0`"]
64    NO_PENDING = 0,
65    #[doc = "1: `1`"]
66    PENDING = 1,
67}
68impl From<TP_UP_PENDING_A> for bool {
69    #[inline(always)]
70    fn from(variant: TP_UP_PENDING_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl TP_UP_PENDING_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> TP_UP_PENDING_A {
78        match self.bits {
79            false => TP_UP_PENDING_A::NO_PENDING,
80            true => TP_UP_PENDING_A::PENDING,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_no_pending(&self) -> bool {
86        *self == TP_UP_PENDING_A::NO_PENDING
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_pending(&self) -> bool {
91        *self == TP_UP_PENDING_A::PENDING
92    }
93}
94#[doc = "Field `tp_up_pending` writer - TP Last Touch (Stylus UP) Pending"]
95pub type TP_UP_PENDING_W<'a, REG> = crate::BitWriter1C<'a, REG, TP_UP_PENDING_A>;
96impl<'a, REG> TP_UP_PENDING_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn no_pending(self) -> &'a mut crate::W<REG> {
103        self.variant(TP_UP_PENDING_A::NO_PENDING)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn pending(self) -> &'a mut crate::W<REG> {
108        self.variant(TP_UP_PENDING_A::PENDING)
109    }
110}
111#[doc = "Field `tp_idle_flg` reader - TP Idle Flag"]
112pub type TP_IDLE_FLG_R = crate::BitReader<TP_IDLE_FLG_A>;
113#[doc = "TP Idle Flag\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum TP_IDLE_FLG_A {
116    #[doc = "0: `0`"]
117    IDLE = 0,
118    #[doc = "1: `1`"]
119    NOT_IDLE = 1,
120}
121impl From<TP_IDLE_FLG_A> for bool {
122    #[inline(always)]
123    fn from(variant: TP_IDLE_FLG_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl TP_IDLE_FLG_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> TP_IDLE_FLG_A {
131        match self.bits {
132            false => TP_IDLE_FLG_A::IDLE,
133            true => TP_IDLE_FLG_A::NOT_IDLE,
134        }
135    }
136    #[doc = "`0`"]
137    #[inline(always)]
138    pub fn is_idle(&self) -> bool {
139        *self == TP_IDLE_FLG_A::IDLE
140    }
141    #[doc = "`1`"]
142    #[inline(always)]
143    pub fn is_not_idle(&self) -> bool {
144        *self == TP_IDLE_FLG_A::NOT_IDLE
145    }
146}
147#[doc = "Field `rxa_cnt` reader - TP FIFO Available Sample Word Count"]
148pub type RXA_CNT_R = crate::FieldReader;
149#[doc = "Field `fifo_data_pending` reader - TP FIFO Data Available Pending"]
150pub type FIFO_DATA_PENDING_R = crate::BitReader<FIFO_DATA_PENDING_A>;
151#[doc = "TP FIFO Data Available Pending\n\nValue on reset: 0"]
152#[derive(Clone, Copy, Debug, PartialEq, Eq)]
153pub enum FIFO_DATA_PENDING_A {
154    #[doc = "0: `0`"]
155    NO_PENDING = 0,
156    #[doc = "1: `1`"]
157    PENDING = 1,
158}
159impl From<FIFO_DATA_PENDING_A> for bool {
160    #[inline(always)]
161    fn from(variant: FIFO_DATA_PENDING_A) -> Self {
162        variant as u8 != 0
163    }
164}
165impl FIFO_DATA_PENDING_R {
166    #[doc = "Get enumerated values variant"]
167    #[inline(always)]
168    pub const fn variant(&self) -> FIFO_DATA_PENDING_A {
169        match self.bits {
170            false => FIFO_DATA_PENDING_A::NO_PENDING,
171            true => FIFO_DATA_PENDING_A::PENDING,
172        }
173    }
174    #[doc = "`0`"]
175    #[inline(always)]
176    pub fn is_no_pending(&self) -> bool {
177        *self == FIFO_DATA_PENDING_A::NO_PENDING
178    }
179    #[doc = "`1`"]
180    #[inline(always)]
181    pub fn is_pending(&self) -> bool {
182        *self == FIFO_DATA_PENDING_A::PENDING
183    }
184}
185#[doc = "Field `fifo_data_pending` writer - TP FIFO Data Available Pending"]
186pub type FIFO_DATA_PENDING_W<'a, REG> = crate::BitWriter1C<'a, REG, FIFO_DATA_PENDING_A>;
187impl<'a, REG> FIFO_DATA_PENDING_W<'a, REG>
188where
189    REG: crate::Writable + crate::RegisterSpec,
190{
191    #[doc = "`0`"]
192    #[inline(always)]
193    pub fn no_pending(self) -> &'a mut crate::W<REG> {
194        self.variant(FIFO_DATA_PENDING_A::NO_PENDING)
195    }
196    #[doc = "`1`"]
197    #[inline(always)]
198    pub fn pending(self) -> &'a mut crate::W<REG> {
199        self.variant(FIFO_DATA_PENDING_A::PENDING)
200    }
201}
202#[doc = "Field `fifo_overrun_pending` reader - TP FIFO Overrun Pending"]
203pub type FIFO_OVERRUN_PENDING_R = crate::BitReader<FIFO_OVERRUN_PENDING_A>;
204#[doc = "TP FIFO Overrun Pending\n\nValue on reset: 0"]
205#[derive(Clone, Copy, Debug, PartialEq, Eq)]
206pub enum FIFO_OVERRUN_PENDING_A {
207    #[doc = "0: `0`"]
208    NO_PENDING = 0,
209    #[doc = "1: `1`"]
210    PENDING = 1,
211}
212impl From<FIFO_OVERRUN_PENDING_A> for bool {
213    #[inline(always)]
214    fn from(variant: FIFO_OVERRUN_PENDING_A) -> Self {
215        variant as u8 != 0
216    }
217}
218impl FIFO_OVERRUN_PENDING_R {
219    #[doc = "Get enumerated values variant"]
220    #[inline(always)]
221    pub const fn variant(&self) -> FIFO_OVERRUN_PENDING_A {
222        match self.bits {
223            false => FIFO_OVERRUN_PENDING_A::NO_PENDING,
224            true => FIFO_OVERRUN_PENDING_A::PENDING,
225        }
226    }
227    #[doc = "`0`"]
228    #[inline(always)]
229    pub fn is_no_pending(&self) -> bool {
230        *self == FIFO_OVERRUN_PENDING_A::NO_PENDING
231    }
232    #[doc = "`1`"]
233    #[inline(always)]
234    pub fn is_pending(&self) -> bool {
235        *self == FIFO_OVERRUN_PENDING_A::PENDING
236    }
237}
238#[doc = "Field `fifo_overrun_pending` writer - TP FIFO Overrun Pending"]
239pub type FIFO_OVERRUN_PENDING_W<'a, REG> = crate::BitWriter1C<'a, REG, FIFO_OVERRUN_PENDING_A>;
240impl<'a, REG> FIFO_OVERRUN_PENDING_W<'a, REG>
241where
242    REG: crate::Writable + crate::RegisterSpec,
243{
244    #[doc = "`0`"]
245    #[inline(always)]
246    pub fn no_pending(self) -> &'a mut crate::W<REG> {
247        self.variant(FIFO_OVERRUN_PENDING_A::NO_PENDING)
248    }
249    #[doc = "`1`"]
250    #[inline(always)]
251    pub fn pending(self) -> &'a mut crate::W<REG> {
252        self.variant(FIFO_OVERRUN_PENDING_A::PENDING)
253    }
254}
255impl R {
256    #[doc = "Bit 0 - TP First Touch (Stylus DOWN) Pending"]
257    #[inline(always)]
258    pub fn tp_down_pending(&self) -> TP_DOWN_PENDING_R {
259        TP_DOWN_PENDING_R::new((self.bits & 1) != 0)
260    }
261    #[doc = "Bit 1 - TP Last Touch (Stylus UP) Pending"]
262    #[inline(always)]
263    pub fn tp_up_pending(&self) -> TP_UP_PENDING_R {
264        TP_UP_PENDING_R::new(((self.bits >> 1) & 1) != 0)
265    }
266    #[doc = "Bit 2 - TP Idle Flag"]
267    #[inline(always)]
268    pub fn tp_idle_flg(&self) -> TP_IDLE_FLG_R {
269        TP_IDLE_FLG_R::new(((self.bits >> 2) & 1) != 0)
270    }
271    #[doc = "Bits 8:13 - TP FIFO Available Sample Word Count"]
272    #[inline(always)]
273    pub fn rxa_cnt(&self) -> RXA_CNT_R {
274        RXA_CNT_R::new(((self.bits >> 8) & 0x3f) as u8)
275    }
276    #[doc = "Bit 16 - TP FIFO Data Available Pending"]
277    #[inline(always)]
278    pub fn fifo_data_pending(&self) -> FIFO_DATA_PENDING_R {
279        FIFO_DATA_PENDING_R::new(((self.bits >> 16) & 1) != 0)
280    }
281    #[doc = "Bit 17 - TP FIFO Overrun Pending"]
282    #[inline(always)]
283    pub fn fifo_overrun_pending(&self) -> FIFO_OVERRUN_PENDING_R {
284        FIFO_OVERRUN_PENDING_R::new(((self.bits >> 17) & 1) != 0)
285    }
286}
287impl W {
288    #[doc = "Bit 0 - TP First Touch (Stylus DOWN) Pending"]
289    #[inline(always)]
290    #[must_use]
291    pub fn tp_down_pending(&mut self) -> TP_DOWN_PENDING_W<TP_INT_FIFO_STAT_SPEC> {
292        TP_DOWN_PENDING_W::new(self, 0)
293    }
294    #[doc = "Bit 1 - TP Last Touch (Stylus UP) Pending"]
295    #[inline(always)]
296    #[must_use]
297    pub fn tp_up_pending(&mut self) -> TP_UP_PENDING_W<TP_INT_FIFO_STAT_SPEC> {
298        TP_UP_PENDING_W::new(self, 1)
299    }
300    #[doc = "Bit 16 - TP FIFO Data Available Pending"]
301    #[inline(always)]
302    #[must_use]
303    pub fn fifo_data_pending(&mut self) -> FIFO_DATA_PENDING_W<TP_INT_FIFO_STAT_SPEC> {
304        FIFO_DATA_PENDING_W::new(self, 16)
305    }
306    #[doc = "Bit 17 - TP FIFO Overrun Pending"]
307    #[inline(always)]
308    #[must_use]
309    pub fn fifo_overrun_pending(&mut self) -> FIFO_OVERRUN_PENDING_W<TP_INT_FIFO_STAT_SPEC> {
310        FIFO_OVERRUN_PENDING_W::new(self, 17)
311    }
312    #[doc = r" Writes raw bits to the register."]
313    #[doc = r""]
314    #[doc = r" # Safety"]
315    #[doc = r""]
316    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
317    #[inline(always)]
318    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
319        self.bits = bits;
320        self
321    }
322}
323#[doc = "TP Interrupt FIFO Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tp_int_fifo_stat::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tp_int_fifo_stat::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
324pub struct TP_INT_FIFO_STAT_SPEC;
325impl crate::RegisterSpec for TP_INT_FIFO_STAT_SPEC {
326    type Ux = u32;
327}
328#[doc = "`read()` method returns [`tp_int_fifo_stat::R`](R) reader structure"]
329impl crate::Readable for TP_INT_FIFO_STAT_SPEC {}
330#[doc = "`write(|w| ..)` method takes [`tp_int_fifo_stat::W`](W) writer structure"]
331impl crate::Writable for TP_INT_FIFO_STAT_SPEC {
332    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
333    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0003_0003;
334}
335#[doc = "`reset()` method sets tp_int_fifo_stat to value 0"]
336impl crate::Resettable for TP_INT_FIFO_STAT_SPEC {
337    const RESET_VALUE: Self::Ux = 0;
338}
d1_pac/tpadc/tp_int_fifo_stat.rs

d1_pac/tpadc/
tp_int_fifo_stat.rs
