d1_pac/tcon_tv0/
tv_data_io_pol1.rs

1#[doc = "Register `tv_data_io_pol1` reader"]
2pub type R = crate::R<TV_DATA_IO_POL1_SPEC>;
3#[doc = "Register `tv_data_io_pol1` writer"]
4pub type W = crate::W<TV_DATA_IO_POL1_SPEC>;
5#[doc = "Field `b_cr_ch_data_inv` reader - B CR CHANNE DATA INV"]
6pub type B_CR_CH_DATA_INV_R = crate::FieldReader<B_CR_CH_DATA_INV_A>;
7#[doc = "B CR CHANNE DATA INV\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u16)]
10pub enum B_CR_CH_DATA_INV_A {
11    #[doc = "0: normal polarity"]
12    NORMAL = 0,
13    #[doc = "1: invert the specify output"]
14    INVERT = 1,
15}
16impl From<B_CR_CH_DATA_INV_A> for u16 {
17    #[inline(always)]
18    fn from(variant: B_CR_CH_DATA_INV_A) -> Self {
19        variant as _
20    }
21}
22impl crate::FieldSpec for B_CR_CH_DATA_INV_A {
23    type Ux = u16;
24}
25impl B_CR_CH_DATA_INV_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> Option<B_CR_CH_DATA_INV_A> {
29        match self.bits {
30            0 => Some(B_CR_CH_DATA_INV_A::NORMAL),
31            1 => Some(B_CR_CH_DATA_INV_A::INVERT),
32            _ => None,
33        }
34    }
35    #[doc = "normal polarity"]
36    #[inline(always)]
37    pub fn is_normal(&self) -> bool {
38        *self == B_CR_CH_DATA_INV_A::NORMAL
39    }
40    #[doc = "invert the specify output"]
41    #[inline(always)]
42    pub fn is_invert(&self) -> bool {
43        *self == B_CR_CH_DATA_INV_A::INVERT
44    }
45}
46#[doc = "Field `b_cr_ch_data_inv` writer - B CR CHANNE DATA INV"]
47pub type B_CR_CH_DATA_INV_W<'a, REG> = crate::FieldWriter<'a, REG, 10, B_CR_CH_DATA_INV_A>;
48impl<'a, REG> B_CR_CH_DATA_INV_W<'a, REG>
49where
50    REG: crate::Writable + crate::RegisterSpec,
51    REG::Ux: From<u16>,
52{
53    #[doc = "normal polarity"]
54    #[inline(always)]
55    pub fn normal(self) -> &'a mut crate::W<REG> {
56        self.variant(B_CR_CH_DATA_INV_A::NORMAL)
57    }
58    #[doc = "invert the specify output"]
59    #[inline(always)]
60    pub fn invert(self) -> &'a mut crate::W<REG> {
61        self.variant(B_CR_CH_DATA_INV_A::INVERT)
62    }
63}
64impl R {
65    #[doc = "Bits 16:25 - B CR CHANNE DATA INV"]
66    #[inline(always)]
67    pub fn b_cr_ch_data_inv(&self) -> B_CR_CH_DATA_INV_R {
68        B_CR_CH_DATA_INV_R::new(((self.bits >> 16) & 0x03ff) as u16)
69    }
70}
71impl W {
72    #[doc = "Bits 16:25 - B CR CHANNE DATA INV"]
73    #[inline(always)]
74    #[must_use]
75    pub fn b_cr_ch_data_inv(&mut self) -> B_CR_CH_DATA_INV_W<TV_DATA_IO_POL1_SPEC> {
76        B_CR_CH_DATA_INV_W::new(self, 16)
77    }
78    #[doc = r" Writes raw bits to the register."]
79    #[doc = r""]
80    #[doc = r" # Safety"]
81    #[doc = r""]
82    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
83    #[inline(always)]
84    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
85        self.bits = bits;
86        self
87    }
88}
89#[doc = "TCON Data IO Polarity Control1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tv_data_io_pol1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tv_data_io_pol1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
90pub struct TV_DATA_IO_POL1_SPEC;
91impl crate::RegisterSpec for TV_DATA_IO_POL1_SPEC {
92    type Ux = u32;
93}
94#[doc = "`read()` method returns [`tv_data_io_pol1::R`](R) reader structure"]
95impl crate::Readable for TV_DATA_IO_POL1_SPEC {}
96#[doc = "`write(|w| ..)` method takes [`tv_data_io_pol1::W`](W) writer structure"]
97impl crate::Writable for TV_DATA_IO_POL1_SPEC {
98    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
99    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
100}
101#[doc = "`reset()` method sets tv_data_io_pol1 to value 0"]
102impl crate::Resettable for TV_DATA_IO_POL1_SPEC {
103    const RESET_VALUE: Self::Ux = 0;
104}
d1_pac/tcon_tv0/tv_data_io_pol1.rs

d1_pac/tcon_tv0/
tv_data_io_pol1.rs
