d1_pac/sys_cfg/
dsp_boot_rammap.rs

1#[doc = "Register `dsp_boot_rammap` reader"]
2pub type R = crate::R<DSP_BOOT_RAMMAP_SPEC>;
3#[doc = "Register `dsp_boot_rammap` writer"]
4pub type W = crate::W<DSP_BOOT_RAMMAP_SPEC>;
5#[doc = "Field `dsp_boot_sram_remap_enable` reader - "]
6pub type DSP_BOOT_SRAM_REMAP_ENABLE_R = crate::BitReader<DSP_BOOT_SRAM_REMAP_ENABLE_A>;
7#[doc = "\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum DSP_BOOT_SRAM_REMAP_ENABLE_A {
10    #[doc = "0: `0`"]
11    DSP_SYS = 0,
12    #[doc = "1: `1`"]
13    SYS_BOOT = 1,
14}
15impl From<DSP_BOOT_SRAM_REMAP_ENABLE_A> for bool {
16    #[inline(always)]
17    fn from(variant: DSP_BOOT_SRAM_REMAP_ENABLE_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl DSP_BOOT_SRAM_REMAP_ENABLE_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> DSP_BOOT_SRAM_REMAP_ENABLE_A {
25        match self.bits {
26            false => DSP_BOOT_SRAM_REMAP_ENABLE_A::DSP_SYS,
27            true => DSP_BOOT_SRAM_REMAP_ENABLE_A::SYS_BOOT,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_dsp_sys(&self) -> bool {
33        *self == DSP_BOOT_SRAM_REMAP_ENABLE_A::DSP_SYS
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_sys_boot(&self) -> bool {
38        *self == DSP_BOOT_SRAM_REMAP_ENABLE_A::SYS_BOOT
39    }
40}
41#[doc = "Field `dsp_boot_sram_remap_enable` writer - "]
42pub type DSP_BOOT_SRAM_REMAP_ENABLE_W<'a, REG> =
43    crate::BitWriter<'a, REG, DSP_BOOT_SRAM_REMAP_ENABLE_A>;
44impl<'a, REG> DSP_BOOT_SRAM_REMAP_ENABLE_W<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "`0`"]
49    #[inline(always)]
50    pub fn dsp_sys(self) -> &'a mut crate::W<REG> {
51        self.variant(DSP_BOOT_SRAM_REMAP_ENABLE_A::DSP_SYS)
52    }
53    #[doc = "`1`"]
54    #[inline(always)]
55    pub fn sys_boot(self) -> &'a mut crate::W<REG> {
56        self.variant(DSP_BOOT_SRAM_REMAP_ENABLE_A::SYS_BOOT)
57    }
58}
59impl R {
60    #[doc = "Bit 0"]
61    #[inline(always)]
62    pub fn dsp_boot_sram_remap_enable(&self) -> DSP_BOOT_SRAM_REMAP_ENABLE_R {
63        DSP_BOOT_SRAM_REMAP_ENABLE_R::new((self.bits & 1) != 0)
64    }
65}
66impl W {
67    #[doc = "Bit 0"]
68    #[inline(always)]
69    #[must_use]
70    pub fn dsp_boot_sram_remap_enable(
71        &mut self,
72    ) -> DSP_BOOT_SRAM_REMAP_ENABLE_W<DSP_BOOT_RAMMAP_SPEC> {
73        DSP_BOOT_SRAM_REMAP_ENABLE_W::new(self, 0)
74    }
75    #[doc = r" Writes raw bits to the register."]
76    #[doc = r""]
77    #[doc = r" # Safety"]
78    #[doc = r""]
79    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
80    #[inline(always)]
81    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
82        self.bits = bits;
83        self
84    }
85}
86#[doc = "DSP Boot SRAM Remap Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dsp_boot_rammap::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dsp_boot_rammap::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
87pub struct DSP_BOOT_RAMMAP_SPEC;
88impl crate::RegisterSpec for DSP_BOOT_RAMMAP_SPEC {
89    type Ux = u32;
90}
91#[doc = "`read()` method returns [`dsp_boot_rammap::R`](R) reader structure"]
92impl crate::Readable for DSP_BOOT_RAMMAP_SPEC {}
93#[doc = "`write(|w| ..)` method takes [`dsp_boot_rammap::W`](W) writer structure"]
94impl crate::Writable for DSP_BOOT_RAMMAP_SPEC {
95    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
96    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
97}
98#[doc = "`reset()` method sets dsp_boot_rammap to value 0"]
99impl crate::Resettable for DSP_BOOT_RAMMAP_SPEC {
100    const RESET_VALUE: Self::Ux = 0;
101}
d1_pac/sys_cfg/dsp_boot_rammap.rs

d1_pac/sys_cfg/
dsp_boot_rammap.rs
