d1_pac/spi_dbi/
dbi_ctl_2.rs

1#[doc = "Register `dbi_ctl_2` reader"]
2pub type R = crate::R<DBI_CTL_2_SPEC>;
3#[doc = "Register `dbi_ctl_2` writer"]
4pub type W = crate::W<DBI_CTL_2_SPEC>;
5#[doc = "Field `te_en` reader - TE Enable"]
6pub type TE_EN_R = crate::BitReader;
7#[doc = "Field `te_en` writer - TE Enable"]
8pub type TE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `te_trig_sel` reader - TE edge trigger select"]
10pub type TE_TRIG_SEL_R = crate::BitReader;
11#[doc = "Field `te_trig_sel` writer - TE edge trigger select"]
12pub type TE_TRIG_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `te_dbc_sel` reader - TE debounce function select"]
14pub type TE_DBC_SEL_R = crate::BitReader;
15#[doc = "Field `te_dbc_sel` writer - TE debounce function select"]
16pub type TE_DBC_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `dbi_sdi_sel` reader - DBI SDI PIN FUnction Select"]
18pub type DBI_SDI_SEL_R = crate::FieldReader<DBI_SDI_SEL_A>;
19#[doc = "DBI SDI PIN FUnction Select\n\nValue on reset: 0"]
20#[derive(Clone, Copy, Debug, PartialEq, Eq)]
21#[repr(u8)]
22pub enum DBI_SDI_SEL_A {
23    #[doc = "0: `0`"]
24    DBI_SDI = 0,
25    #[doc = "1: `1`"]
26    DBI_TE = 1,
27    #[doc = "2: `10`"]
28    DBI_DCX = 2,
29}
30impl From<DBI_SDI_SEL_A> for u8 {
31    #[inline(always)]
32    fn from(variant: DBI_SDI_SEL_A) -> Self {
33        variant as _
34    }
35}
36impl crate::FieldSpec for DBI_SDI_SEL_A {
37    type Ux = u8;
38}
39impl DBI_SDI_SEL_R {
40    #[doc = "Get enumerated values variant"]
41    #[inline(always)]
42    pub const fn variant(&self) -> Option<DBI_SDI_SEL_A> {
43        match self.bits {
44            0 => Some(DBI_SDI_SEL_A::DBI_SDI),
45            1 => Some(DBI_SDI_SEL_A::DBI_TE),
46            2 => Some(DBI_SDI_SEL_A::DBI_DCX),
47            _ => None,
48        }
49    }
50    #[doc = "`0`"]
51    #[inline(always)]
52    pub fn is_dbi_sdi(&self) -> bool {
53        *self == DBI_SDI_SEL_A::DBI_SDI
54    }
55    #[doc = "`1`"]
56    #[inline(always)]
57    pub fn is_dbi_te(&self) -> bool {
58        *self == DBI_SDI_SEL_A::DBI_TE
59    }
60    #[doc = "`10`"]
61    #[inline(always)]
62    pub fn is_dbi_dcx(&self) -> bool {
63        *self == DBI_SDI_SEL_A::DBI_DCX
64    }
65}
66#[doc = "Field `dbi_sdi_sel` writer - DBI SDI PIN FUnction Select"]
67pub type DBI_SDI_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, DBI_SDI_SEL_A>;
68impl<'a, REG> DBI_SDI_SEL_W<'a, REG>
69where
70    REG: crate::Writable + crate::RegisterSpec,
71    REG::Ux: From<u8>,
72{
73    #[doc = "`0`"]
74    #[inline(always)]
75    pub fn dbi_sdi(self) -> &'a mut crate::W<REG> {
76        self.variant(DBI_SDI_SEL_A::DBI_SDI)
77    }
78    #[doc = "`1`"]
79    #[inline(always)]
80    pub fn dbi_te(self) -> &'a mut crate::W<REG> {
81        self.variant(DBI_SDI_SEL_A::DBI_TE)
82    }
83    #[doc = "`10`"]
84    #[inline(always)]
85    pub fn dbi_dcx(self) -> &'a mut crate::W<REG> {
86        self.variant(DBI_SDI_SEL_A::DBI_DCX)
87    }
88}
89#[doc = "Field `dbi_dcx_sel` reader - DBI DCX PIN Function Select"]
90pub type DBI_DCX_SEL_R = crate::BitReader;
91#[doc = "Field `dbi_dcx_sel` writer - DBI DCX PIN Function Select"]
92pub type DBI_DCX_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
93#[doc = "Field `dbi_sdq_out_sel` reader - DBI SDI PIN Output Select"]
94pub type DBI_SDQ_OUT_SEL_R = crate::BitReader;
95#[doc = "Field `dbi_sdq_out_sel` writer - DBI SDI PIN Output Select"]
96pub type DBI_SDQ_OUT_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
97#[doc = "Field `dbi_trig_level` reader - DBI FIFO Empty Request Trigger Level"]
98pub type DBI_TRIG_LEVEL_R = crate::FieldReader;
99#[doc = "Field `dbi_trig_level` writer - DBI FIFO Empty Request Trigger Level"]
100pub type DBI_TRIG_LEVEL_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
101#[doc = "Field `dbi_fifo_drq_en` reader - DBI FIFO DMA Request Enable"]
102pub type DBI_FIFO_DRQ_EN_R = crate::BitReader;
103#[doc = "Field `dbi_fifo_drq_en` writer - DBI FIFO DMA Request Enable"]
104pub type DBI_FIFO_DRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
105impl R {
106    #[doc = "Bit 0 - TE Enable"]
107    #[inline(always)]
108    pub fn te_en(&self) -> TE_EN_R {
109        TE_EN_R::new((self.bits & 1) != 0)
110    }
111    #[doc = "Bit 1 - TE edge trigger select"]
112    #[inline(always)]
113    pub fn te_trig_sel(&self) -> TE_TRIG_SEL_R {
114        TE_TRIG_SEL_R::new(((self.bits >> 1) & 1) != 0)
115    }
116    #[doc = "Bit 2 - TE debounce function select"]
117    #[inline(always)]
118    pub fn te_dbc_sel(&self) -> TE_DBC_SEL_R {
119        TE_DBC_SEL_R::new(((self.bits >> 2) & 1) != 0)
120    }
121    #[doc = "Bits 3:4 - DBI SDI PIN FUnction Select"]
122    #[inline(always)]
123    pub fn dbi_sdi_sel(&self) -> DBI_SDI_SEL_R {
124        DBI_SDI_SEL_R::new(((self.bits >> 3) & 3) as u8)
125    }
126    #[doc = "Bit 5 - DBI DCX PIN Function Select"]
127    #[inline(always)]
128    pub fn dbi_dcx_sel(&self) -> DBI_DCX_SEL_R {
129        DBI_DCX_SEL_R::new(((self.bits >> 5) & 1) != 0)
130    }
131    #[doc = "Bit 6 - DBI SDI PIN Output Select"]
132    #[inline(always)]
133    pub fn dbi_sdq_out_sel(&self) -> DBI_SDQ_OUT_SEL_R {
134        DBI_SDQ_OUT_SEL_R::new(((self.bits >> 6) & 1) != 0)
135    }
136    #[doc = "Bits 8:14 - DBI FIFO Empty Request Trigger Level"]
137    #[inline(always)]
138    pub fn dbi_trig_level(&self) -> DBI_TRIG_LEVEL_R {
139        DBI_TRIG_LEVEL_R::new(((self.bits >> 8) & 0x7f) as u8)
140    }
141    #[doc = "Bit 15 - DBI FIFO DMA Request Enable"]
142    #[inline(always)]
143    pub fn dbi_fifo_drq_en(&self) -> DBI_FIFO_DRQ_EN_R {
144        DBI_FIFO_DRQ_EN_R::new(((self.bits >> 15) & 1) != 0)
145    }
146}
147impl W {
148    #[doc = "Bit 0 - TE Enable"]
149    #[inline(always)]
150    #[must_use]
151    pub fn te_en(&mut self) -> TE_EN_W<DBI_CTL_2_SPEC> {
152        TE_EN_W::new(self, 0)
153    }
154    #[doc = "Bit 1 - TE edge trigger select"]
155    #[inline(always)]
156    #[must_use]
157    pub fn te_trig_sel(&mut self) -> TE_TRIG_SEL_W<DBI_CTL_2_SPEC> {
158        TE_TRIG_SEL_W::new(self, 1)
159    }
160    #[doc = "Bit 2 - TE debounce function select"]
161    #[inline(always)]
162    #[must_use]
163    pub fn te_dbc_sel(&mut self) -> TE_DBC_SEL_W<DBI_CTL_2_SPEC> {
164        TE_DBC_SEL_W::new(self, 2)
165    }
166    #[doc = "Bits 3:4 - DBI SDI PIN FUnction Select"]
167    #[inline(always)]
168    #[must_use]
169    pub fn dbi_sdi_sel(&mut self) -> DBI_SDI_SEL_W<DBI_CTL_2_SPEC> {
170        DBI_SDI_SEL_W::new(self, 3)
171    }
172    #[doc = "Bit 5 - DBI DCX PIN Function Select"]
173    #[inline(always)]
174    #[must_use]
175    pub fn dbi_dcx_sel(&mut self) -> DBI_DCX_SEL_W<DBI_CTL_2_SPEC> {
176        DBI_DCX_SEL_W::new(self, 5)
177    }
178    #[doc = "Bit 6 - DBI SDI PIN Output Select"]
179    #[inline(always)]
180    #[must_use]
181    pub fn dbi_sdq_out_sel(&mut self) -> DBI_SDQ_OUT_SEL_W<DBI_CTL_2_SPEC> {
182        DBI_SDQ_OUT_SEL_W::new(self, 6)
183    }
184    #[doc = "Bits 8:14 - DBI FIFO Empty Request Trigger Level"]
185    #[inline(always)]
186    #[must_use]
187    pub fn dbi_trig_level(&mut self) -> DBI_TRIG_LEVEL_W<DBI_CTL_2_SPEC> {
188        DBI_TRIG_LEVEL_W::new(self, 8)
189    }
190    #[doc = "Bit 15 - DBI FIFO DMA Request Enable"]
191    #[inline(always)]
192    #[must_use]
193    pub fn dbi_fifo_drq_en(&mut self) -> DBI_FIFO_DRQ_EN_W<DBI_CTL_2_SPEC> {
194        DBI_FIFO_DRQ_EN_W::new(self, 15)
195    }
196    #[doc = r" Writes raw bits to the register."]
197    #[doc = r""]
198    #[doc = r" # Safety"]
199    #[doc = r""]
200    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
201    #[inline(always)]
202    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
203        self.bits = bits;
204        self
205    }
206}
207#[doc = "DBI Control Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbi_ctl_2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbi_ctl_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
208pub struct DBI_CTL_2_SPEC;
209impl crate::RegisterSpec for DBI_CTL_2_SPEC {
210    type Ux = u32;
211}
212#[doc = "`read()` method returns [`dbi_ctl_2::R`](R) reader structure"]
213impl crate::Readable for DBI_CTL_2_SPEC {}
214#[doc = "`write(|w| ..)` method takes [`dbi_ctl_2::W`](W) writer structure"]
215impl crate::Writable for DBI_CTL_2_SPEC {
216    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
217    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
218}
219#[doc = "`reset()` method sets dbi_ctl_2 to value 0"]
220impl crate::Resettable for DBI_CTL_2_SPEC {
221    const RESET_VALUE: Self::Ux = 0;
222}
d1_pac/spi_dbi/dbi_ctl_2.rs

d1_pac/spi_dbi/
dbi_ctl_2.rs
