d1_pac/spi0/
spi_tcr.rs

1#[doc = "Register `spi_tcr` reader"]
2pub type R = crate::R<SPI_TCR_SPEC>;
3#[doc = "Register `spi_tcr` writer"]
4pub type W = crate::W<SPI_TCR_SPEC>;
5#[doc = "Field `cpha` reader - SPI Clock/Data Phase Control"]
6pub type CPHA_R = crate::BitReader<CPHA_A>;
7#[doc = "SPI Clock/Data Phase Control\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum CPHA_A {
10    #[doc = "0: Phase 0 (Leading edge for sample data)"]
11    P0 = 0,
12    #[doc = "1: Phase 1 (Leading edge for setup data)"]
13    P1 = 1,
14}
15impl From<CPHA_A> for bool {
16    #[inline(always)]
17    fn from(variant: CPHA_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl CPHA_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> CPHA_A {
25        match self.bits {
26            false => CPHA_A::P0,
27            true => CPHA_A::P1,
28        }
29    }
30    #[doc = "Phase 0 (Leading edge for sample data)"]
31    #[inline(always)]
32    pub fn is_p0(&self) -> bool {
33        *self == CPHA_A::P0
34    }
35    #[doc = "Phase 1 (Leading edge for setup data)"]
36    #[inline(always)]
37    pub fn is_p1(&self) -> bool {
38        *self == CPHA_A::P1
39    }
40}
41#[doc = "Field `cpha` writer - SPI Clock/Data Phase Control"]
42pub type CPHA_W<'a, REG> = crate::BitWriter<'a, REG, CPHA_A>;
43impl<'a, REG> CPHA_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Phase 0 (Leading edge for sample data)"]
48    #[inline(always)]
49    pub fn p0(self) -> &'a mut crate::W<REG> {
50        self.variant(CPHA_A::P0)
51    }
52    #[doc = "Phase 1 (Leading edge for setup data)"]
53    #[inline(always)]
54    pub fn p1(self) -> &'a mut crate::W<REG> {
55        self.variant(CPHA_A::P1)
56    }
57}
58#[doc = "Field `cpol` reader - SPI Clock Polarity Control"]
59pub type CPOL_R = crate::BitReader<CPOL_A>;
60#[doc = "SPI Clock Polarity Control\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum CPOL_A {
63    #[doc = "0: Active high polarity"]
64    HIGH = 0,
65    #[doc = "1: Active low polarity"]
66    LOW = 1,
67}
68impl From<CPOL_A> for bool {
69    #[inline(always)]
70    fn from(variant: CPOL_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl CPOL_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> CPOL_A {
78        match self.bits {
79            false => CPOL_A::HIGH,
80            true => CPOL_A::LOW,
81        }
82    }
83    #[doc = "Active high polarity"]
84    #[inline(always)]
85    pub fn is_high(&self) -> bool {
86        *self == CPOL_A::HIGH
87    }
88    #[doc = "Active low polarity"]
89    #[inline(always)]
90    pub fn is_low(&self) -> bool {
91        *self == CPOL_A::LOW
92    }
93}
94#[doc = "Field `cpol` writer - SPI Clock Polarity Control"]
95pub type CPOL_W<'a, REG> = crate::BitWriter<'a, REG, CPOL_A>;
96impl<'a, REG> CPOL_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Active high polarity"]
101    #[inline(always)]
102    pub fn high(self) -> &'a mut crate::W<REG> {
103        self.variant(CPOL_A::HIGH)
104    }
105    #[doc = "Active low polarity"]
106    #[inline(always)]
107    pub fn low(self) -> &'a mut crate::W<REG> {
108        self.variant(CPOL_A::LOW)
109    }
110}
111#[doc = "Field `spol` reader - SPI Chip Select Signal Polarity Control"]
112pub type SPOL_R = crate::BitReader<SPOL_A>;
113#[doc = "SPI Chip Select Signal Polarity Control\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum SPOL_A {
116    #[doc = "0: Active high polarity"]
117    HIGH = 0,
118    #[doc = "1: Active low polarity"]
119    LOW = 1,
120}
121impl From<SPOL_A> for bool {
122    #[inline(always)]
123    fn from(variant: SPOL_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl SPOL_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> SPOL_A {
131        match self.bits {
132            false => SPOL_A::HIGH,
133            true => SPOL_A::LOW,
134        }
135    }
136    #[doc = "Active high polarity"]
137    #[inline(always)]
138    pub fn is_high(&self) -> bool {
139        *self == SPOL_A::HIGH
140    }
141    #[doc = "Active low polarity"]
142    #[inline(always)]
143    pub fn is_low(&self) -> bool {
144        *self == SPOL_A::LOW
145    }
146}
147#[doc = "Field `spol` writer - SPI Chip Select Signal Polarity Control"]
148pub type SPOL_W<'a, REG> = crate::BitWriter<'a, REG, SPOL_A>;
149impl<'a, REG> SPOL_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "Active high polarity"]
154    #[inline(always)]
155    pub fn high(self) -> &'a mut crate::W<REG> {
156        self.variant(SPOL_A::HIGH)
157    }
158    #[doc = "Active low polarity"]
159    #[inline(always)]
160    pub fn low(self) -> &'a mut crate::W<REG> {
161        self.variant(SPOL_A::LOW)
162    }
163}
164#[doc = "Field `ssctl` reader - "]
165pub type SSCTL_R = crate::BitReader<SSCTL_A>;
166#[doc = "\n\nValue on reset: 0"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum SSCTL_A {
169    #[doc = "0: SPI_SSx remains asserted between SPI bursts"]
170    ASSERT = 0,
171    #[doc = "1: Negate SPI_SSx between SPI bursts"]
172    NEGATE = 1,
173}
174impl From<SSCTL_A> for bool {
175    #[inline(always)]
176    fn from(variant: SSCTL_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl SSCTL_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> SSCTL_A {
184        match self.bits {
185            false => SSCTL_A::ASSERT,
186            true => SSCTL_A::NEGATE,
187        }
188    }
189    #[doc = "SPI_SSx remains asserted between SPI bursts"]
190    #[inline(always)]
191    pub fn is_assert(&self) -> bool {
192        *self == SSCTL_A::ASSERT
193    }
194    #[doc = "Negate SPI_SSx between SPI bursts"]
195    #[inline(always)]
196    pub fn is_negate(&self) -> bool {
197        *self == SSCTL_A::NEGATE
198    }
199}
200#[doc = "Field `ssctl` writer - "]
201pub type SSCTL_W<'a, REG> = crate::BitWriter<'a, REG, SSCTL_A>;
202impl<'a, REG> SSCTL_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "SPI_SSx remains asserted between SPI bursts"]
207    #[inline(always)]
208    pub fn assert(self) -> &'a mut crate::W<REG> {
209        self.variant(SSCTL_A::ASSERT)
210    }
211    #[doc = "Negate SPI_SSx between SPI bursts"]
212    #[inline(always)]
213    pub fn negate(self) -> &'a mut crate::W<REG> {
214        self.variant(SSCTL_A::NEGATE)
215    }
216}
217#[doc = "Field `ss_sel` reader - "]
218pub type SS_SEL_R = crate::FieldReader<SS_SEL_A>;
219#[doc = "\n\nValue on reset: 0"]
220#[derive(Clone, Copy, Debug, PartialEq, Eq)]
221#[repr(u8)]
222pub enum SS_SEL_A {
223    #[doc = "0: `0`"]
224    SS0 = 0,
225    #[doc = "1: `1`"]
226    SS1 = 1,
227    #[doc = "2: `10`"]
228    SS2 = 2,
229    #[doc = "3: `11`"]
230    SS3 = 3,
231}
232impl From<SS_SEL_A> for u8 {
233    #[inline(always)]
234    fn from(variant: SS_SEL_A) -> Self {
235        variant as _
236    }
237}
238impl crate::FieldSpec for SS_SEL_A {
239    type Ux = u8;
240}
241impl SS_SEL_R {
242    #[doc = "Get enumerated values variant"]
243    #[inline(always)]
244    pub const fn variant(&self) -> SS_SEL_A {
245        match self.bits {
246            0 => SS_SEL_A::SS0,
247            1 => SS_SEL_A::SS1,
248            2 => SS_SEL_A::SS2,
249            3 => SS_SEL_A::SS3,
250            _ => unreachable!(),
251        }
252    }
253    #[doc = "`0`"]
254    #[inline(always)]
255    pub fn is_ss0(&self) -> bool {
256        *self == SS_SEL_A::SS0
257    }
258    #[doc = "`1`"]
259    #[inline(always)]
260    pub fn is_ss1(&self) -> bool {
261        *self == SS_SEL_A::SS1
262    }
263    #[doc = "`10`"]
264    #[inline(always)]
265    pub fn is_ss2(&self) -> bool {
266        *self == SS_SEL_A::SS2
267    }
268    #[doc = "`11`"]
269    #[inline(always)]
270    pub fn is_ss3(&self) -> bool {
271        *self == SS_SEL_A::SS3
272    }
273}
274#[doc = "Field `ss_sel` writer - "]
275pub type SS_SEL_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, SS_SEL_A>;
276impl<'a, REG> SS_SEL_W<'a, REG>
277where
278    REG: crate::Writable + crate::RegisterSpec,
279    REG::Ux: From<u8>,
280{
281    #[doc = "`0`"]
282    #[inline(always)]
283    pub fn ss0(self) -> &'a mut crate::W<REG> {
284        self.variant(SS_SEL_A::SS0)
285    }
286    #[doc = "`1`"]
287    #[inline(always)]
288    pub fn ss1(self) -> &'a mut crate::W<REG> {
289        self.variant(SS_SEL_A::SS1)
290    }
291    #[doc = "`10`"]
292    #[inline(always)]
293    pub fn ss2(self) -> &'a mut crate::W<REG> {
294        self.variant(SS_SEL_A::SS2)
295    }
296    #[doc = "`11`"]
297    #[inline(always)]
298    pub fn ss3(self) -> &'a mut crate::W<REG> {
299        self.variant(SS_SEL_A::SS3)
300    }
301}
302#[doc = "Field `ss_owner` reader - "]
303pub type SS_OWNER_R = crate::BitReader<SS_OWNER_A>;
304#[doc = "\n\nValue on reset: 0"]
305#[derive(Clone, Copy, Debug, PartialEq, Eq)]
306pub enum SS_OWNER_A {
307    #[doc = "0: `0`"]
308    SPI_CONTROLLER = 0,
309    #[doc = "1: `1`"]
310    SOFTWARE = 1,
311}
312impl From<SS_OWNER_A> for bool {
313    #[inline(always)]
314    fn from(variant: SS_OWNER_A) -> Self {
315        variant as u8 != 0
316    }
317}
318impl SS_OWNER_R {
319    #[doc = "Get enumerated values variant"]
320    #[inline(always)]
321    pub const fn variant(&self) -> SS_OWNER_A {
322        match self.bits {
323            false => SS_OWNER_A::SPI_CONTROLLER,
324            true => SS_OWNER_A::SOFTWARE,
325        }
326    }
327    #[doc = "`0`"]
328    #[inline(always)]
329    pub fn is_spi_controller(&self) -> bool {
330        *self == SS_OWNER_A::SPI_CONTROLLER
331    }
332    #[doc = "`1`"]
333    #[inline(always)]
334    pub fn is_software(&self) -> bool {
335        *self == SS_OWNER_A::SOFTWARE
336    }
337}
338#[doc = "Field `ss_owner` writer - "]
339pub type SS_OWNER_W<'a, REG> = crate::BitWriter<'a, REG, SS_OWNER_A>;
340impl<'a, REG> SS_OWNER_W<'a, REG>
341where
342    REG: crate::Writable + crate::RegisterSpec,
343{
344    #[doc = "`0`"]
345    #[inline(always)]
346    pub fn spi_controller(self) -> &'a mut crate::W<REG> {
347        self.variant(SS_OWNER_A::SPI_CONTROLLER)
348    }
349    #[doc = "`1`"]
350    #[inline(always)]
351    pub fn software(self) -> &'a mut crate::W<REG> {
352        self.variant(SS_OWNER_A::SOFTWARE)
353    }
354}
355#[doc = "Field `ss_level` reader - "]
356pub type SS_LEVEL_R = crate::BitReader<SS_LEVEL_A>;
357#[doc = "\n\nValue on reset: 0"]
358#[derive(Clone, Copy, Debug, PartialEq, Eq)]
359pub enum SS_LEVEL_A {
360    #[doc = "0: `0`"]
361    LOW = 0,
362    #[doc = "1: `1`"]
363    HIGH = 1,
364}
365impl From<SS_LEVEL_A> for bool {
366    #[inline(always)]
367    fn from(variant: SS_LEVEL_A) -> Self {
368        variant as u8 != 0
369    }
370}
371impl SS_LEVEL_R {
372    #[doc = "Get enumerated values variant"]
373    #[inline(always)]
374    pub const fn variant(&self) -> SS_LEVEL_A {
375        match self.bits {
376            false => SS_LEVEL_A::LOW,
377            true => SS_LEVEL_A::HIGH,
378        }
379    }
380    #[doc = "`0`"]
381    #[inline(always)]
382    pub fn is_low(&self) -> bool {
383        *self == SS_LEVEL_A::LOW
384    }
385    #[doc = "`1`"]
386    #[inline(always)]
387    pub fn is_high(&self) -> bool {
388        *self == SS_LEVEL_A::HIGH
389    }
390}
391#[doc = "Field `ss_level` writer - "]
392pub type SS_LEVEL_W<'a, REG> = crate::BitWriter<'a, REG, SS_LEVEL_A>;
393impl<'a, REG> SS_LEVEL_W<'a, REG>
394where
395    REG: crate::Writable + crate::RegisterSpec,
396{
397    #[doc = "`0`"]
398    #[inline(always)]
399    pub fn low(self) -> &'a mut crate::W<REG> {
400        self.variant(SS_LEVEL_A::LOW)
401    }
402    #[doc = "`1`"]
403    #[inline(always)]
404    pub fn high(self) -> &'a mut crate::W<REG> {
405        self.variant(SS_LEVEL_A::HIGH)
406    }
407}
408#[doc = "Field `dhb` reader - Discard Hash Burst"]
409pub type DHB_R = crate::BitReader<DHB_A>;
410#[doc = "Discard Hash Burst\n\nValue on reset: 0"]
411#[derive(Clone, Copy, Debug, PartialEq, Eq)]
412pub enum DHB_A {
413    #[doc = "0: Receiving all SPI bursts in the BC period"]
414    RECEIVE = 0,
415    #[doc = "1: Discard unused SPI bursts"]
416    DISCARD = 1,
417}
418impl From<DHB_A> for bool {
419    #[inline(always)]
420    fn from(variant: DHB_A) -> Self {
421        variant as u8 != 0
422    }
423}
424impl DHB_R {
425    #[doc = "Get enumerated values variant"]
426    #[inline(always)]
427    pub const fn variant(&self) -> DHB_A {
428        match self.bits {
429            false => DHB_A::RECEIVE,
430            true => DHB_A::DISCARD,
431        }
432    }
433    #[doc = "Receiving all SPI bursts in the BC period"]
434    #[inline(always)]
435    pub fn is_receive(&self) -> bool {
436        *self == DHB_A::RECEIVE
437    }
438    #[doc = "Discard unused SPI bursts"]
439    #[inline(always)]
440    pub fn is_discard(&self) -> bool {
441        *self == DHB_A::DISCARD
442    }
443}
444#[doc = "Field `dhb` writer - Discard Hash Burst"]
445pub type DHB_W<'a, REG> = crate::BitWriter<'a, REG, DHB_A>;
446impl<'a, REG> DHB_W<'a, REG>
447where
448    REG: crate::Writable + crate::RegisterSpec,
449{
450    #[doc = "Receiving all SPI bursts in the BC period"]
451    #[inline(always)]
452    pub fn receive(self) -> &'a mut crate::W<REG> {
453        self.variant(DHB_A::RECEIVE)
454    }
455    #[doc = "Discard unused SPI bursts"]
456    #[inline(always)]
457    pub fn discard(self) -> &'a mut crate::W<REG> {
458        self.variant(DHB_A::DISCARD)
459    }
460}
461#[doc = "Field `ddb` reader - Dummy Burst Type"]
462pub type DDB_R = crate::BitReader<DDB_A>;
463#[doc = "Dummy Burst Type\n\nValue on reset: 0"]
464#[derive(Clone, Copy, Debug, PartialEq, Eq)]
465pub enum DDB_A {
466    #[doc = "0: The bit value of dummy SPI burst is zero"]
467    ZERO = 0,
468    #[doc = "1: The bit value of dummy SPI burst is one"]
469    ONE = 1,
470}
471impl From<DDB_A> for bool {
472    #[inline(always)]
473    fn from(variant: DDB_A) -> Self {
474        variant as u8 != 0
475    }
476}
477impl DDB_R {
478    #[doc = "Get enumerated values variant"]
479    #[inline(always)]
480    pub const fn variant(&self) -> DDB_A {
481        match self.bits {
482            false => DDB_A::ZERO,
483            true => DDB_A::ONE,
484        }
485    }
486    #[doc = "The bit value of dummy SPI burst is zero"]
487    #[inline(always)]
488    pub fn is_zero(&self) -> bool {
489        *self == DDB_A::ZERO
490    }
491    #[doc = "The bit value of dummy SPI burst is one"]
492    #[inline(always)]
493    pub fn is_one(&self) -> bool {
494        *self == DDB_A::ONE
495    }
496}
497#[doc = "Field `ddb` writer - Dummy Burst Type"]
498pub type DDB_W<'a, REG> = crate::BitWriter<'a, REG, DDB_A>;
499impl<'a, REG> DDB_W<'a, REG>
500where
501    REG: crate::Writable + crate::RegisterSpec,
502{
503    #[doc = "The bit value of dummy SPI burst is zero"]
504    #[inline(always)]
505    pub fn zero(self) -> &'a mut crate::W<REG> {
506        self.variant(DDB_A::ZERO)
507    }
508    #[doc = "The bit value of dummy SPI burst is one"]
509    #[inline(always)]
510    pub fn one(self) -> &'a mut crate::W<REG> {
511        self.variant(DDB_A::ONE)
512    }
513}
514#[doc = "Field `rpsm` reader - Rapids Mode Select"]
515pub type RPSM_R = crate::BitReader<RPSM_A>;
516#[doc = "Rapids Mode Select\n\nValue on reset: 0"]
517#[derive(Clone, Copy, Debug, PartialEq, Eq)]
518pub enum RPSM_A {
519    #[doc = "0: Normal write mode"]
520    NORMAL = 0,
521    #[doc = "1: Rapid write mode"]
522    RAPID = 1,
523}
524impl From<RPSM_A> for bool {
525    #[inline(always)]
526    fn from(variant: RPSM_A) -> Self {
527        variant as u8 != 0
528    }
529}
530impl RPSM_R {
531    #[doc = "Get enumerated values variant"]
532    #[inline(always)]
533    pub const fn variant(&self) -> RPSM_A {
534        match self.bits {
535            false => RPSM_A::NORMAL,
536            true => RPSM_A::RAPID,
537        }
538    }
539    #[doc = "Normal write mode"]
540    #[inline(always)]
541    pub fn is_normal(&self) -> bool {
542        *self == RPSM_A::NORMAL
543    }
544    #[doc = "Rapid write mode"]
545    #[inline(always)]
546    pub fn is_rapid(&self) -> bool {
547        *self == RPSM_A::RAPID
548    }
549}
550#[doc = "Field `rpsm` writer - Rapids Mode Select"]
551pub type RPSM_W<'a, REG> = crate::BitWriter<'a, REG, RPSM_A>;
552impl<'a, REG> RPSM_W<'a, REG>
553where
554    REG: crate::Writable + crate::RegisterSpec,
555{
556    #[doc = "Normal write mode"]
557    #[inline(always)]
558    pub fn normal(self) -> &'a mut crate::W<REG> {
559        self.variant(RPSM_A::NORMAL)
560    }
561    #[doc = "Rapid write mode"]
562    #[inline(always)]
563    pub fn rapid(self) -> &'a mut crate::W<REG> {
564        self.variant(RPSM_A::RAPID)
565    }
566}
567#[doc = "Field `sdc` reader - Master Sample Data Control"]
568pub type SDC_R = crate::BitReader<SDC_A>;
569#[doc = "Master Sample Data Control\n\nValue on reset: 0"]
570#[derive(Clone, Copy, Debug, PartialEq, Eq)]
571pub enum SDC_A {
572    #[doc = "0: Normal operation, do not delay the internal read sample point"]
573    NORMAL = 0,
574    #[doc = "1: Delay the internal read sample point"]
575    DELAY = 1,
576}
577impl From<SDC_A> for bool {
578    #[inline(always)]
579    fn from(variant: SDC_A) -> Self {
580        variant as u8 != 0
581    }
582}
583impl SDC_R {
584    #[doc = "Get enumerated values variant"]
585    #[inline(always)]
586    pub const fn variant(&self) -> SDC_A {
587        match self.bits {
588            false => SDC_A::NORMAL,
589            true => SDC_A::DELAY,
590        }
591    }
592    #[doc = "Normal operation, do not delay the internal read sample point"]
593    #[inline(always)]
594    pub fn is_normal(&self) -> bool {
595        *self == SDC_A::NORMAL
596    }
597    #[doc = "Delay the internal read sample point"]
598    #[inline(always)]
599    pub fn is_delay(&self) -> bool {
600        *self == SDC_A::DELAY
601    }
602}
603#[doc = "Field `sdc` writer - Master Sample Data Control"]
604pub type SDC_W<'a, REG> = crate::BitWriter<'a, REG, SDC_A>;
605impl<'a, REG> SDC_W<'a, REG>
606where
607    REG: crate::Writable + crate::RegisterSpec,
608{
609    #[doc = "Normal operation, do not delay the internal read sample point"]
610    #[inline(always)]
611    pub fn normal(self) -> &'a mut crate::W<REG> {
612        self.variant(SDC_A::NORMAL)
613    }
614    #[doc = "Delay the internal read sample point"]
615    #[inline(always)]
616    pub fn delay(self) -> &'a mut crate::W<REG> {
617        self.variant(SDC_A::DELAY)
618    }
619}
620#[doc = "Field `fbs` reader - First Transmit Bit Select"]
621pub type FBS_R = crate::BitReader<FBS_A>;
622#[doc = "First Transmit Bit Select\n\nValue on reset: 0"]
623#[derive(Clone, Copy, Debug, PartialEq, Eq)]
624pub enum FBS_A {
625    #[doc = "0: MSB first"]
626    MSB = 0,
627    #[doc = "1: LSB first"]
628    LSB = 1,
629}
630impl From<FBS_A> for bool {
631    #[inline(always)]
632    fn from(variant: FBS_A) -> Self {
633        variant as u8 != 0
634    }
635}
636impl FBS_R {
637    #[doc = "Get enumerated values variant"]
638    #[inline(always)]
639    pub const fn variant(&self) -> FBS_A {
640        match self.bits {
641            false => FBS_A::MSB,
642            true => FBS_A::LSB,
643        }
644    }
645    #[doc = "MSB first"]
646    #[inline(always)]
647    pub fn is_msb(&self) -> bool {
648        *self == FBS_A::MSB
649    }
650    #[doc = "LSB first"]
651    #[inline(always)]
652    pub fn is_lsb(&self) -> bool {
653        *self == FBS_A::LSB
654    }
655}
656#[doc = "Field `fbs` writer - First Transmit Bit Select"]
657pub type FBS_W<'a, REG> = crate::BitWriter<'a, REG, FBS_A>;
658impl<'a, REG> FBS_W<'a, REG>
659where
660    REG: crate::Writable + crate::RegisterSpec,
661{
662    #[doc = "MSB first"]
663    #[inline(always)]
664    pub fn msb(self) -> &'a mut crate::W<REG> {
665        self.variant(FBS_A::MSB)
666    }
667    #[doc = "LSB first"]
668    #[inline(always)]
669    pub fn lsb(self) -> &'a mut crate::W<REG> {
670        self.variant(FBS_A::LSB)
671    }
672}
673#[doc = "Field `sdm` reader - Master Sample Data Mode"]
674pub type SDM_R = crate::BitReader<SDM_A>;
675#[doc = "Master Sample Data Mode\n\nValue on reset: 0"]
676#[derive(Clone, Copy, Debug, PartialEq, Eq)]
677pub enum SDM_A {
678    #[doc = "0: delay sample mode"]
679    DELAY = 0,
680    #[doc = "1: normal sample mode"]
681    NORMAL = 1,
682}
683impl From<SDM_A> for bool {
684    #[inline(always)]
685    fn from(variant: SDM_A) -> Self {
686        variant as u8 != 0
687    }
688}
689impl SDM_R {
690    #[doc = "Get enumerated values variant"]
691    #[inline(always)]
692    pub const fn variant(&self) -> SDM_A {
693        match self.bits {
694            false => SDM_A::DELAY,
695            true => SDM_A::NORMAL,
696        }
697    }
698    #[doc = "delay sample mode"]
699    #[inline(always)]
700    pub fn is_delay(&self) -> bool {
701        *self == SDM_A::DELAY
702    }
703    #[doc = "normal sample mode"]
704    #[inline(always)]
705    pub fn is_normal(&self) -> bool {
706        *self == SDM_A::NORMAL
707    }
708}
709#[doc = "Field `sdm` writer - Master Sample Data Mode"]
710pub type SDM_W<'a, REG> = crate::BitWriter<'a, REG, SDM_A>;
711impl<'a, REG> SDM_W<'a, REG>
712where
713    REG: crate::Writable + crate::RegisterSpec,
714{
715    #[doc = "delay sample mode"]
716    #[inline(always)]
717    pub fn delay(self) -> &'a mut crate::W<REG> {
718        self.variant(SDM_A::DELAY)
719    }
720    #[doc = "normal sample mode"]
721    #[inline(always)]
722    pub fn normal(self) -> &'a mut crate::W<REG> {
723        self.variant(SDM_A::NORMAL)
724    }
725}
726#[doc = "Field `sddm` reader - Sending Data Delay Mode"]
727pub type SDDM_R = crate::BitReader<SDDM_A>;
728#[doc = "Sending Data Delay Mode\n\nValue on reset: 0"]
729#[derive(Clone, Copy, Debug, PartialEq, Eq)]
730pub enum SDDM_A {
731    #[doc = "0: normal sending"]
732    NORMAL = 0,
733    #[doc = "1: delay sending"]
734    DELAY = 1,
735}
736impl From<SDDM_A> for bool {
737    #[inline(always)]
738    fn from(variant: SDDM_A) -> Self {
739        variant as u8 != 0
740    }
741}
742impl SDDM_R {
743    #[doc = "Get enumerated values variant"]
744    #[inline(always)]
745    pub const fn variant(&self) -> SDDM_A {
746        match self.bits {
747            false => SDDM_A::NORMAL,
748            true => SDDM_A::DELAY,
749        }
750    }
751    #[doc = "normal sending"]
752    #[inline(always)]
753    pub fn is_normal(&self) -> bool {
754        *self == SDDM_A::NORMAL
755    }
756    #[doc = "delay sending"]
757    #[inline(always)]
758    pub fn is_delay(&self) -> bool {
759        *self == SDDM_A::DELAY
760    }
761}
762#[doc = "Field `sddm` writer - Sending Data Delay Mode"]
763pub type SDDM_W<'a, REG> = crate::BitWriter<'a, REG, SDDM_A>;
764impl<'a, REG> SDDM_W<'a, REG>
765where
766    REG: crate::Writable + crate::RegisterSpec,
767{
768    #[doc = "normal sending"]
769    #[inline(always)]
770    pub fn normal(self) -> &'a mut crate::W<REG> {
771        self.variant(SDDM_A::NORMAL)
772    }
773    #[doc = "delay sending"]
774    #[inline(always)]
775    pub fn delay(self) -> &'a mut crate::W<REG> {
776        self.variant(SDDM_A::DELAY)
777    }
778}
779#[doc = "Field `sdc1` reader - Master Sample Data Control register1"]
780pub type SDC1_R = crate::BitReader<SDC1_A>;
781#[doc = "Master Sample Data Control register1\n\nValue on reset: 0"]
782#[derive(Clone, Copy, Debug, PartialEq, Eq)]
783pub enum SDC1_A {
784    #[doc = "0: normal operation, do not delay the internal read sample point"]
785    NORMAL = 0,
786    #[doc = "1: delay the internal read sample point"]
787    DELAY = 1,
788}
789impl From<SDC1_A> for bool {
790    #[inline(always)]
791    fn from(variant: SDC1_A) -> Self {
792        variant as u8 != 0
793    }
794}
795impl SDC1_R {
796    #[doc = "Get enumerated values variant"]
797    #[inline(always)]
798    pub const fn variant(&self) -> SDC1_A {
799        match self.bits {
800            false => SDC1_A::NORMAL,
801            true => SDC1_A::DELAY,
802        }
803    }
804    #[doc = "normal operation, do not delay the internal read sample point"]
805    #[inline(always)]
806    pub fn is_normal(&self) -> bool {
807        *self == SDC1_A::NORMAL
808    }
809    #[doc = "delay the internal read sample point"]
810    #[inline(always)]
811    pub fn is_delay(&self) -> bool {
812        *self == SDC1_A::DELAY
813    }
814}
815#[doc = "Field `sdc1` writer - Master Sample Data Control register1"]
816pub type SDC1_W<'a, REG> = crate::BitWriter<'a, REG, SDC1_A>;
817impl<'a, REG> SDC1_W<'a, REG>
818where
819    REG: crate::Writable + crate::RegisterSpec,
820{
821    #[doc = "normal operation, do not delay the internal read sample point"]
822    #[inline(always)]
823    pub fn normal(self) -> &'a mut crate::W<REG> {
824        self.variant(SDC1_A::NORMAL)
825    }
826    #[doc = "delay the internal read sample point"]
827    #[inline(always)]
828    pub fn delay(self) -> &'a mut crate::W<REG> {
829        self.variant(SDC1_A::DELAY)
830    }
831}
832#[doc = "Field `xch` reader - Exchange Burst"]
833pub type XCH_R = crate::BitReader<XCH_A>;
834#[doc = "Exchange Burst\n\nValue on reset: 0"]
835#[derive(Clone, Copy, Debug, PartialEq, Eq)]
836pub enum XCH_A {
837    #[doc = "0: `0`"]
838    IDLE = 0,
839    #[doc = "1: `1`"]
840    INITIATE_EXCHANGE = 1,
841}
842impl From<XCH_A> for bool {
843    #[inline(always)]
844    fn from(variant: XCH_A) -> Self {
845        variant as u8 != 0
846    }
847}
848impl XCH_R {
849    #[doc = "Get enumerated values variant"]
850    #[inline(always)]
851    pub const fn variant(&self) -> XCH_A {
852        match self.bits {
853            false => XCH_A::IDLE,
854            true => XCH_A::INITIATE_EXCHANGE,
855        }
856    }
857    #[doc = "`0`"]
858    #[inline(always)]
859    pub fn is_idle(&self) -> bool {
860        *self == XCH_A::IDLE
861    }
862    #[doc = "`1`"]
863    #[inline(always)]
864    pub fn is_initiate_exchange(&self) -> bool {
865        *self == XCH_A::INITIATE_EXCHANGE
866    }
867}
868#[doc = "Field `xch` writer - Exchange Burst"]
869pub type XCH_W<'a, REG> = crate::BitWriter<'a, REG, XCH_A>;
870impl<'a, REG> XCH_W<'a, REG>
871where
872    REG: crate::Writable + crate::RegisterSpec,
873{
874    #[doc = "`0`"]
875    #[inline(always)]
876    pub fn idle(self) -> &'a mut crate::W<REG> {
877        self.variant(XCH_A::IDLE)
878    }
879    #[doc = "`1`"]
880    #[inline(always)]
881    pub fn initiate_exchange(self) -> &'a mut crate::W<REG> {
882        self.variant(XCH_A::INITIATE_EXCHANGE)
883    }
884}
885impl R {
886    #[doc = "Bit 0 - SPI Clock/Data Phase Control"]
887    #[inline(always)]
888    pub fn cpha(&self) -> CPHA_R {
889        CPHA_R::new((self.bits & 1) != 0)
890    }
891    #[doc = "Bit 1 - SPI Clock Polarity Control"]
892    #[inline(always)]
893    pub fn cpol(&self) -> CPOL_R {
894        CPOL_R::new(((self.bits >> 1) & 1) != 0)
895    }
896    #[doc = "Bit 2 - SPI Chip Select Signal Polarity Control"]
897    #[inline(always)]
898    pub fn spol(&self) -> SPOL_R {
899        SPOL_R::new(((self.bits >> 2) & 1) != 0)
900    }
901    #[doc = "Bit 3"]
902    #[inline(always)]
903    pub fn ssctl(&self) -> SSCTL_R {
904        SSCTL_R::new(((self.bits >> 3) & 1) != 0)
905    }
906    #[doc = "Bits 4:5"]
907    #[inline(always)]
908    pub fn ss_sel(&self) -> SS_SEL_R {
909        SS_SEL_R::new(((self.bits >> 4) & 3) as u8)
910    }
911    #[doc = "Bit 6"]
912    #[inline(always)]
913    pub fn ss_owner(&self) -> SS_OWNER_R {
914        SS_OWNER_R::new(((self.bits >> 6) & 1) != 0)
915    }
916    #[doc = "Bit 7"]
917    #[inline(always)]
918    pub fn ss_level(&self) -> SS_LEVEL_R {
919        SS_LEVEL_R::new(((self.bits >> 7) & 1) != 0)
920    }
921    #[doc = "Bit 8 - Discard Hash Burst"]
922    #[inline(always)]
923    pub fn dhb(&self) -> DHB_R {
924        DHB_R::new(((self.bits >> 8) & 1) != 0)
925    }
926    #[doc = "Bit 9 - Dummy Burst Type"]
927    #[inline(always)]
928    pub fn ddb(&self) -> DDB_R {
929        DDB_R::new(((self.bits >> 9) & 1) != 0)
930    }
931    #[doc = "Bit 10 - Rapids Mode Select"]
932    #[inline(always)]
933    pub fn rpsm(&self) -> RPSM_R {
934        RPSM_R::new(((self.bits >> 10) & 1) != 0)
935    }
936    #[doc = "Bit 11 - Master Sample Data Control"]
937    #[inline(always)]
938    pub fn sdc(&self) -> SDC_R {
939        SDC_R::new(((self.bits >> 11) & 1) != 0)
940    }
941    #[doc = "Bit 12 - First Transmit Bit Select"]
942    #[inline(always)]
943    pub fn fbs(&self) -> FBS_R {
944        FBS_R::new(((self.bits >> 12) & 1) != 0)
945    }
946    #[doc = "Bit 13 - Master Sample Data Mode"]
947    #[inline(always)]
948    pub fn sdm(&self) -> SDM_R {
949        SDM_R::new(((self.bits >> 13) & 1) != 0)
950    }
951    #[doc = "Bit 14 - Sending Data Delay Mode"]
952    #[inline(always)]
953    pub fn sddm(&self) -> SDDM_R {
954        SDDM_R::new(((self.bits >> 14) & 1) != 0)
955    }
956    #[doc = "Bit 15 - Master Sample Data Control register1"]
957    #[inline(always)]
958    pub fn sdc1(&self) -> SDC1_R {
959        SDC1_R::new(((self.bits >> 15) & 1) != 0)
960    }
961    #[doc = "Bit 31 - Exchange Burst"]
962    #[inline(always)]
963    pub fn xch(&self) -> XCH_R {
964        XCH_R::new(((self.bits >> 31) & 1) != 0)
965    }
966}
967impl W {
968    #[doc = "Bit 0 - SPI Clock/Data Phase Control"]
969    #[inline(always)]
970    #[must_use]
971    pub fn cpha(&mut self) -> CPHA_W<SPI_TCR_SPEC> {
972        CPHA_W::new(self, 0)
973    }
974    #[doc = "Bit 1 - SPI Clock Polarity Control"]
975    #[inline(always)]
976    #[must_use]
977    pub fn cpol(&mut self) -> CPOL_W<SPI_TCR_SPEC> {
978        CPOL_W::new(self, 1)
979    }
980    #[doc = "Bit 2 - SPI Chip Select Signal Polarity Control"]
981    #[inline(always)]
982    #[must_use]
983    pub fn spol(&mut self) -> SPOL_W<SPI_TCR_SPEC> {
984        SPOL_W::new(self, 2)
985    }
986    #[doc = "Bit 3"]
987    #[inline(always)]
988    #[must_use]
989    pub fn ssctl(&mut self) -> SSCTL_W<SPI_TCR_SPEC> {
990        SSCTL_W::new(self, 3)
991    }
992    #[doc = "Bits 4:5"]
993    #[inline(always)]
994    #[must_use]
995    pub fn ss_sel(&mut self) -> SS_SEL_W<SPI_TCR_SPEC> {
996        SS_SEL_W::new(self, 4)
997    }
998    #[doc = "Bit 6"]
999    #[inline(always)]
1000    #[must_use]
1001    pub fn ss_owner(&mut self) -> SS_OWNER_W<SPI_TCR_SPEC> {
1002        SS_OWNER_W::new(self, 6)
1003    }
1004    #[doc = "Bit 7"]
1005    #[inline(always)]
1006    #[must_use]
1007    pub fn ss_level(&mut self) -> SS_LEVEL_W<SPI_TCR_SPEC> {
1008        SS_LEVEL_W::new(self, 7)
1009    }
1010    #[doc = "Bit 8 - Discard Hash Burst"]
1011    #[inline(always)]
1012    #[must_use]
1013    pub fn dhb(&mut self) -> DHB_W<SPI_TCR_SPEC> {
1014        DHB_W::new(self, 8)
1015    }
1016    #[doc = "Bit 9 - Dummy Burst Type"]
1017    #[inline(always)]
1018    #[must_use]
1019    pub fn ddb(&mut self) -> DDB_W<SPI_TCR_SPEC> {
1020        DDB_W::new(self, 9)
1021    }
1022    #[doc = "Bit 10 - Rapids Mode Select"]
1023    #[inline(always)]
1024    #[must_use]
1025    pub fn rpsm(&mut self) -> RPSM_W<SPI_TCR_SPEC> {
1026        RPSM_W::new(self, 10)
1027    }
1028    #[doc = "Bit 11 - Master Sample Data Control"]
1029    #[inline(always)]
1030    #[must_use]
1031    pub fn sdc(&mut self) -> SDC_W<SPI_TCR_SPEC> {
1032        SDC_W::new(self, 11)
1033    }
1034    #[doc = "Bit 12 - First Transmit Bit Select"]
1035    #[inline(always)]
1036    #[must_use]
1037    pub fn fbs(&mut self) -> FBS_W<SPI_TCR_SPEC> {
1038        FBS_W::new(self, 12)
1039    }
1040    #[doc = "Bit 13 - Master Sample Data Mode"]
1041    #[inline(always)]
1042    #[must_use]
1043    pub fn sdm(&mut self) -> SDM_W<SPI_TCR_SPEC> {
1044        SDM_W::new(self, 13)
1045    }
1046    #[doc = "Bit 14 - Sending Data Delay Mode"]
1047    #[inline(always)]
1048    #[must_use]
1049    pub fn sddm(&mut self) -> SDDM_W<SPI_TCR_SPEC> {
1050        SDDM_W::new(self, 14)
1051    }
1052    #[doc = "Bit 15 - Master Sample Data Control register1"]
1053    #[inline(always)]
1054    #[must_use]
1055    pub fn sdc1(&mut self) -> SDC1_W<SPI_TCR_SPEC> {
1056        SDC1_W::new(self, 15)
1057    }
1058    #[doc = "Bit 31 - Exchange Burst"]
1059    #[inline(always)]
1060    #[must_use]
1061    pub fn xch(&mut self) -> XCH_W<SPI_TCR_SPEC> {
1062        XCH_W::new(self, 31)
1063    }
1064    #[doc = r" Writes raw bits to the register."]
1065    #[doc = r""]
1066    #[doc = r" # Safety"]
1067    #[doc = r""]
1068    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
1069    #[inline(always)]
1070    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1071        self.bits = bits;
1072        self
1073    }
1074}
1075#[doc = "SPI Transfer Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_tcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_tcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1076pub struct SPI_TCR_SPEC;
1077impl crate::RegisterSpec for SPI_TCR_SPEC {
1078    type Ux = u32;
1079}
1080#[doc = "`read()` method returns [`spi_tcr::R`](R) reader structure"]
1081impl crate::Readable for SPI_TCR_SPEC {}
1082#[doc = "`write(|w| ..)` method takes [`spi_tcr::W`](W) writer structure"]
1083impl crate::Writable for SPI_TCR_SPEC {
1084    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
1085    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
1086}
1087#[doc = "`reset()` method sets spi_tcr to value 0"]
1088impl crate::Resettable for SPI_TCR_SPEC {
1089    const RESET_VALUE: Self::Ux = 0;
1090}
d1_pac/spi0/spi_tcr.rs

d1_pac/spi0/
spi_tcr.rs
