d1_pac/smhc/
smhc_thld.rs

1#[doc = "Register `smhc_thld` reader"]
2pub type R = crate::R<SMHC_THLD_SPEC>;
3#[doc = "Register `smhc_thld` writer"]
4pub type W = crate::W<SMHC_THLD_SPEC>;
5#[doc = "Field `card_rd_thld_enb` reader - Card Read Threshold Enable"]
6pub type CARD_RD_THLD_ENB_R = crate::BitReader<CARD_RD_THLD_ENB_A>;
7#[doc = "Card Read Threshold Enable\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum CARD_RD_THLD_ENB_A {
10    #[doc = "0: Card read threshold disabled"]
11    DISABLED = 0,
12    #[doc = "1: Card read threshold enabled"]
13    ENABLED = 1,
14}
15impl From<CARD_RD_THLD_ENB_A> for bool {
16    #[inline(always)]
17    fn from(variant: CARD_RD_THLD_ENB_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl CARD_RD_THLD_ENB_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> CARD_RD_THLD_ENB_A {
25        match self.bits {
26            false => CARD_RD_THLD_ENB_A::DISABLED,
27            true => CARD_RD_THLD_ENB_A::ENABLED,
28        }
29    }
30    #[doc = "Card read threshold disabled"]
31    #[inline(always)]
32    pub fn is_disabled(&self) -> bool {
33        *self == CARD_RD_THLD_ENB_A::DISABLED
34    }
35    #[doc = "Card read threshold enabled"]
36    #[inline(always)]
37    pub fn is_enabled(&self) -> bool {
38        *self == CARD_RD_THLD_ENB_A::ENABLED
39    }
40}
41#[doc = "Field `card_rd_thld_enb` writer - Card Read Threshold Enable"]
42pub type CARD_RD_THLD_ENB_W<'a, REG> = crate::BitWriter<'a, REG, CARD_RD_THLD_ENB_A>;
43impl<'a, REG> CARD_RD_THLD_ENB_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Card read threshold disabled"]
48    #[inline(always)]
49    pub fn disabled(self) -> &'a mut crate::W<REG> {
50        self.variant(CARD_RD_THLD_ENB_A::DISABLED)
51    }
52    #[doc = "Card read threshold enabled"]
53    #[inline(always)]
54    pub fn enabled(self) -> &'a mut crate::W<REG> {
55        self.variant(CARD_RD_THLD_ENB_A::ENABLED)
56    }
57}
58#[doc = "Field `bcig` reader - Busy Clear Interrupt Generation"]
59pub type BCIG_R = crate::BitReader<BCIG_A>;
60#[doc = "Busy Clear Interrupt Generation\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum BCIG_A {
63    #[doc = "0: Busy clear interrupt disabled"]
64    DISABLED = 0,
65    #[doc = "1: Busy clear interrupt enabled"]
66    ENABLED = 1,
67}
68impl From<BCIG_A> for bool {
69    #[inline(always)]
70    fn from(variant: BCIG_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl BCIG_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> BCIG_A {
78        match self.bits {
79            false => BCIG_A::DISABLED,
80            true => BCIG_A::ENABLED,
81        }
82    }
83    #[doc = "Busy clear interrupt disabled"]
84    #[inline(always)]
85    pub fn is_disabled(&self) -> bool {
86        *self == BCIG_A::DISABLED
87    }
88    #[doc = "Busy clear interrupt enabled"]
89    #[inline(always)]
90    pub fn is_enabled(&self) -> bool {
91        *self == BCIG_A::ENABLED
92    }
93}
94#[doc = "Field `bcig` writer - Busy Clear Interrupt Generation"]
95pub type BCIG_W<'a, REG> = crate::BitWriter<'a, REG, BCIG_A>;
96impl<'a, REG> BCIG_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Busy clear interrupt disabled"]
101    #[inline(always)]
102    pub fn disabled(self) -> &'a mut crate::W<REG> {
103        self.variant(BCIG_A::DISABLED)
104    }
105    #[doc = "Busy clear interrupt enabled"]
106    #[inline(always)]
107    pub fn enabled(self) -> &'a mut crate::W<REG> {
108        self.variant(BCIG_A::ENABLED)
109    }
110}
111#[doc = "Field `card_wr_thld_enb` reader - Card Read/Write Threshold Enable"]
112pub type CARD_WR_THLD_ENB_R = crate::BitReader<CARD_WR_THLD_ENB_A>;
113#[doc = "Card Read/Write Threshold Enable\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum CARD_WR_THLD_ENB_A {
116    #[doc = "0: Card write threshold disabled"]
117    DISABLED = 0,
118    #[doc = "1: Card write threshold enabled"]
119    ENABLED = 1,
120}
121impl From<CARD_WR_THLD_ENB_A> for bool {
122    #[inline(always)]
123    fn from(variant: CARD_WR_THLD_ENB_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl CARD_WR_THLD_ENB_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> CARD_WR_THLD_ENB_A {
131        match self.bits {
132            false => CARD_WR_THLD_ENB_A::DISABLED,
133            true => CARD_WR_THLD_ENB_A::ENABLED,
134        }
135    }
136    #[doc = "Card write threshold disabled"]
137    #[inline(always)]
138    pub fn is_disabled(&self) -> bool {
139        *self == CARD_WR_THLD_ENB_A::DISABLED
140    }
141    #[doc = "Card write threshold enabled"]
142    #[inline(always)]
143    pub fn is_enabled(&self) -> bool {
144        *self == CARD_WR_THLD_ENB_A::ENABLED
145    }
146}
147#[doc = "Field `card_wr_thld_enb` writer - Card Read/Write Threshold Enable"]
148pub type CARD_WR_THLD_ENB_W<'a, REG> = crate::BitWriter<'a, REG, CARD_WR_THLD_ENB_A>;
149impl<'a, REG> CARD_WR_THLD_ENB_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "Card write threshold disabled"]
154    #[inline(always)]
155    pub fn disabled(self) -> &'a mut crate::W<REG> {
156        self.variant(CARD_WR_THLD_ENB_A::DISABLED)
157    }
158    #[doc = "Card write threshold enabled"]
159    #[inline(always)]
160    pub fn enabled(self) -> &'a mut crate::W<REG> {
161        self.variant(CARD_WR_THLD_ENB_A::ENABLED)
162    }
163}
164#[doc = "Field `card_wr_thld` reader - Card Read/Write Threshold Size"]
165pub type CARD_WR_THLD_R = crate::FieldReader<u16>;
166#[doc = "Field `card_wr_thld` writer - Card Read/Write Threshold Size"]
167pub type CARD_WR_THLD_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
168impl R {
169    #[doc = "Bit 0 - Card Read Threshold Enable"]
170    #[inline(always)]
171    pub fn card_rd_thld_enb(&self) -> CARD_RD_THLD_ENB_R {
172        CARD_RD_THLD_ENB_R::new((self.bits & 1) != 0)
173    }
174    #[doc = "Bit 1 - Busy Clear Interrupt Generation"]
175    #[inline(always)]
176    pub fn bcig(&self) -> BCIG_R {
177        BCIG_R::new(((self.bits >> 1) & 1) != 0)
178    }
179    #[doc = "Bit 2 - Card Read/Write Threshold Enable"]
180    #[inline(always)]
181    pub fn card_wr_thld_enb(&self) -> CARD_WR_THLD_ENB_R {
182        CARD_WR_THLD_ENB_R::new(((self.bits >> 2) & 1) != 0)
183    }
184    #[doc = "Bits 16:27 - Card Read/Write Threshold Size"]
185    #[inline(always)]
186    pub fn card_wr_thld(&self) -> CARD_WR_THLD_R {
187        CARD_WR_THLD_R::new(((self.bits >> 16) & 0x0fff) as u16)
188    }
189}
190impl W {
191    #[doc = "Bit 0 - Card Read Threshold Enable"]
192    #[inline(always)]
193    #[must_use]
194    pub fn card_rd_thld_enb(&mut self) -> CARD_RD_THLD_ENB_W<SMHC_THLD_SPEC> {
195        CARD_RD_THLD_ENB_W::new(self, 0)
196    }
197    #[doc = "Bit 1 - Busy Clear Interrupt Generation"]
198    #[inline(always)]
199    #[must_use]
200    pub fn bcig(&mut self) -> BCIG_W<SMHC_THLD_SPEC> {
201        BCIG_W::new(self, 1)
202    }
203    #[doc = "Bit 2 - Card Read/Write Threshold Enable"]
204    #[inline(always)]
205    #[must_use]
206    pub fn card_wr_thld_enb(&mut self) -> CARD_WR_THLD_ENB_W<SMHC_THLD_SPEC> {
207        CARD_WR_THLD_ENB_W::new(self, 2)
208    }
209    #[doc = "Bits 16:27 - Card Read/Write Threshold Size"]
210    #[inline(always)]
211    #[must_use]
212    pub fn card_wr_thld(&mut self) -> CARD_WR_THLD_W<SMHC_THLD_SPEC> {
213        CARD_WR_THLD_W::new(self, 16)
214    }
215    #[doc = r" Writes raw bits to the register."]
216    #[doc = r""]
217    #[doc = r" # Safety"]
218    #[doc = r""]
219    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
220    #[inline(always)]
221    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
222        self.bits = bits;
223        self
224    }
225}
226#[doc = "Card Threshold Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_thld::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_thld::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
227pub struct SMHC_THLD_SPEC;
228impl crate::RegisterSpec for SMHC_THLD_SPEC {
229    type Ux = u32;
230}
231#[doc = "`read()` method returns [`smhc_thld::R`](R) reader structure"]
232impl crate::Readable for SMHC_THLD_SPEC {}
233#[doc = "`write(|w| ..)` method takes [`smhc_thld::W`](W) writer structure"]
234impl crate::Writable for SMHC_THLD_SPEC {
235    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
236    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
237}
238#[doc = "`reset()` method sets smhc_thld to value 0"]
239impl crate::Resettable for SMHC_THLD_SPEC {
240    const RESET_VALUE: Self::Ux = 0;
241}
d1_pac/smhc/smhc_thld.rs

d1_pac/smhc/
smhc_thld.rs
