d1_pac/smhc/
smhc_fifoth.rs

1#[doc = "Register `smhc_fifoth` reader"]
2pub type R = crate::R<SMHC_FIFOTH_SPEC>;
3#[doc = "Register `smhc_fifoth` writer"]
4pub type W = crate::W<SMHC_FIFOTH_SPEC>;
5#[doc = "Field `tx_tl` reader - TX Trigger Level"]
6pub type TX_TL_R = crate::FieldReader;
7#[doc = "Field `tx_tl` writer - TX Trigger Level"]
8pub type TX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `rx_tl` reader - RX Trigger Level"]
10pub type RX_TL_R = crate::FieldReader;
11#[doc = "Field `rx_tl` writer - RX Trigger Level"]
12pub type RX_TL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `bsize_of_trans` reader - sBurst Size of Multiple Transaction"]
14pub type BSIZE_OF_TRANS_R = crate::FieldReader<BSIZE_OF_TRANS_A>;
15#[doc = "sBurst Size of Multiple Transaction\n\nValue on reset: 0"]
16#[derive(Clone, Copy, Debug, PartialEq, Eq)]
17#[repr(u8)]
18pub enum BSIZE_OF_TRANS_A {
19    #[doc = "0: 1 transfer"]
20    T1 = 0,
21    #[doc = "1: 4 transfers"]
22    T4 = 1,
23    #[doc = "2: 8 transfers"]
24    T8 = 2,
25    #[doc = "3: 16 transfers"]
26    T16 = 3,
27}
28impl From<BSIZE_OF_TRANS_A> for u8 {
29    #[inline(always)]
30    fn from(variant: BSIZE_OF_TRANS_A) -> Self {
31        variant as _
32    }
33}
34impl crate::FieldSpec for BSIZE_OF_TRANS_A {
35    type Ux = u8;
36}
37impl BSIZE_OF_TRANS_R {
38    #[doc = "Get enumerated values variant"]
39    #[inline(always)]
40    pub const fn variant(&self) -> Option<BSIZE_OF_TRANS_A> {
41        match self.bits {
42            0 => Some(BSIZE_OF_TRANS_A::T1),
43            1 => Some(BSIZE_OF_TRANS_A::T4),
44            2 => Some(BSIZE_OF_TRANS_A::T8),
45            3 => Some(BSIZE_OF_TRANS_A::T16),
46            _ => None,
47        }
48    }
49    #[doc = "1 transfer"]
50    #[inline(always)]
51    pub fn is_t1(&self) -> bool {
52        *self == BSIZE_OF_TRANS_A::T1
53    }
54    #[doc = "4 transfers"]
55    #[inline(always)]
56    pub fn is_t4(&self) -> bool {
57        *self == BSIZE_OF_TRANS_A::T4
58    }
59    #[doc = "8 transfers"]
60    #[inline(always)]
61    pub fn is_t8(&self) -> bool {
62        *self == BSIZE_OF_TRANS_A::T8
63    }
64    #[doc = "16 transfers"]
65    #[inline(always)]
66    pub fn is_t16(&self) -> bool {
67        *self == BSIZE_OF_TRANS_A::T16
68    }
69}
70#[doc = "Field `bsize_of_trans` writer - sBurst Size of Multiple Transaction"]
71pub type BSIZE_OF_TRANS_W<'a, REG> = crate::FieldWriter<'a, REG, 3, BSIZE_OF_TRANS_A>;
72impl<'a, REG> BSIZE_OF_TRANS_W<'a, REG>
73where
74    REG: crate::Writable + crate::RegisterSpec,
75    REG::Ux: From<u8>,
76{
77    #[doc = "1 transfer"]
78    #[inline(always)]
79    pub fn t1(self) -> &'a mut crate::W<REG> {
80        self.variant(BSIZE_OF_TRANS_A::T1)
81    }
82    #[doc = "4 transfers"]
83    #[inline(always)]
84    pub fn t4(self) -> &'a mut crate::W<REG> {
85        self.variant(BSIZE_OF_TRANS_A::T4)
86    }
87    #[doc = "8 transfers"]
88    #[inline(always)]
89    pub fn t8(self) -> &'a mut crate::W<REG> {
90        self.variant(BSIZE_OF_TRANS_A::T8)
91    }
92    #[doc = "16 transfers"]
93    #[inline(always)]
94    pub fn t16(self) -> &'a mut crate::W<REG> {
95        self.variant(BSIZE_OF_TRANS_A::T16)
96    }
97}
98impl R {
99    #[doc = "Bits 0:7 - TX Trigger Level"]
100    #[inline(always)]
101    pub fn tx_tl(&self) -> TX_TL_R {
102        TX_TL_R::new((self.bits & 0xff) as u8)
103    }
104    #[doc = "Bits 16:23 - RX Trigger Level"]
105    #[inline(always)]
106    pub fn rx_tl(&self) -> RX_TL_R {
107        RX_TL_R::new(((self.bits >> 16) & 0xff) as u8)
108    }
109    #[doc = "Bits 28:30 - sBurst Size of Multiple Transaction"]
110    #[inline(always)]
111    pub fn bsize_of_trans(&self) -> BSIZE_OF_TRANS_R {
112        BSIZE_OF_TRANS_R::new(((self.bits >> 28) & 7) as u8)
113    }
114}
115impl W {
116    #[doc = "Bits 0:7 - TX Trigger Level"]
117    #[inline(always)]
118    #[must_use]
119    pub fn tx_tl(&mut self) -> TX_TL_W<SMHC_FIFOTH_SPEC> {
120        TX_TL_W::new(self, 0)
121    }
122    #[doc = "Bits 16:23 - RX Trigger Level"]
123    #[inline(always)]
124    #[must_use]
125    pub fn rx_tl(&mut self) -> RX_TL_W<SMHC_FIFOTH_SPEC> {
126        RX_TL_W::new(self, 16)
127    }
128    #[doc = "Bits 28:30 - sBurst Size of Multiple Transaction"]
129    #[inline(always)]
130    #[must_use]
131    pub fn bsize_of_trans(&mut self) -> BSIZE_OF_TRANS_W<SMHC_FIFOTH_SPEC> {
132        BSIZE_OF_TRANS_W::new(self, 28)
133    }
134    #[doc = r" Writes raw bits to the register."]
135    #[doc = r""]
136    #[doc = r" # Safety"]
137    #[doc = r""]
138    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
139    #[inline(always)]
140    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
141        self.bits = bits;
142        self
143    }
144}
145#[doc = "FIFO Water Level Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_fifoth::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_fifoth::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
146pub struct SMHC_FIFOTH_SPEC;
147impl crate::RegisterSpec for SMHC_FIFOTH_SPEC {
148    type Ux = u32;
149}
150#[doc = "`read()` method returns [`smhc_fifoth::R`](R) reader structure"]
151impl crate::Readable for SMHC_FIFOTH_SPEC {}
152#[doc = "`write(|w| ..)` method takes [`smhc_fifoth::W`](W) writer structure"]
153impl crate::Writable for SMHC_FIFOTH_SPEC {
154    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
155    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
156}
157#[doc = "`reset()` method sets smhc_fifoth to value 0"]
158impl crate::Resettable for SMHC_FIFOTH_SPEC {
159    const RESET_VALUE: Self::Ux = 0;
160}
d1_pac/smhc/smhc_fifoth.rs

d1_pac/smhc/
smhc_fifoth.rs
