1#[doc = "Register `cier` reader"]
2pub type R = crate::R<CIER_SPEC>;
3#[doc = "Register `cier` writer"]
4pub type W = crate::W<CIER_SPEC>;
5#[doc = "Field `crie[0-7]` reader - If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending."]
6pub type CRIE_R = crate::BitReader<CRIE_A>;
7#[doc = "If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending.\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum CRIE_A {
10 #[doc = "0: Capture channel rise lock interrupt disable"]
11 DISABLE = 0,
12 #[doc = "1: Capture channel rise lock interrupt enable"]
13 ENABLE = 1,
14}
15impl From<CRIE_A> for bool {
16 #[inline(always)]
17 fn from(variant: CRIE_A) -> Self {
18 variant as u8 != 0
19 }
20}
21impl CRIE_R {
22 #[doc = "Get enumerated values variant"]
23 #[inline(always)]
24 pub const fn variant(&self) -> CRIE_A {
25 match self.bits {
26 false => CRIE_A::DISABLE,
27 true => CRIE_A::ENABLE,
28 }
29 }
30 #[doc = "Capture channel rise lock interrupt disable"]
31 #[inline(always)]
32 pub fn is_disable(&self) -> bool {
33 *self == CRIE_A::DISABLE
34 }
35 #[doc = "Capture channel rise lock interrupt enable"]
36 #[inline(always)]
37 pub fn is_enable(&self) -> bool {
38 *self == CRIE_A::ENABLE
39 }
40}
41#[doc = "Field `crie[0-7]` writer - If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending."]
42pub type CRIE_W<'a, REG> = crate::BitWriter<'a, REG, CRIE_A>;
43impl<'a, REG> CRIE_W<'a, REG>
44where
45 REG: crate::Writable + crate::RegisterSpec,
46{
47 #[doc = "Capture channel rise lock interrupt disable"]
48 #[inline(always)]
49 pub fn disable(self) -> &'a mut crate::W<REG> {
50 self.variant(CRIE_A::DISABLE)
51 }
52 #[doc = "Capture channel rise lock interrupt enable"]
53 #[inline(always)]
54 pub fn enable(self) -> &'a mut crate::W<REG> {
55 self.variant(CRIE_A::ENABLE)
56 }
57}
58#[doc = "Field `cfie[0-7]` reader - If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending."]
59pub type CFIE_R = crate::BitReader<CFIE_A>;
60#[doc = "If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending.\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum CFIE_A {
63 #[doc = "0: Capture channel fall lock interrupt disable"]
64 DISABLE = 0,
65 #[doc = "1: Capture channel fall lock interrupt enable"]
66 ENABLE = 1,
67}
68impl From<CFIE_A> for bool {
69 #[inline(always)]
70 fn from(variant: CFIE_A) -> Self {
71 variant as u8 != 0
72 }
73}
74impl CFIE_R {
75 #[doc = "Get enumerated values variant"]
76 #[inline(always)]
77 pub const fn variant(&self) -> CFIE_A {
78 match self.bits {
79 false => CFIE_A::DISABLE,
80 true => CFIE_A::ENABLE,
81 }
82 }
83 #[doc = "Capture channel fall lock interrupt disable"]
84 #[inline(always)]
85 pub fn is_disable(&self) -> bool {
86 *self == CFIE_A::DISABLE
87 }
88 #[doc = "Capture channel fall lock interrupt enable"]
89 #[inline(always)]
90 pub fn is_enable(&self) -> bool {
91 *self == CFIE_A::ENABLE
92 }
93}
94#[doc = "Field `cfie[0-7]` writer - If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending."]
95pub type CFIE_W<'a, REG> = crate::BitWriter<'a, REG, CFIE_A>;
96impl<'a, REG> CFIE_W<'a, REG>
97where
98 REG: crate::Writable + crate::RegisterSpec,
99{
100 #[doc = "Capture channel fall lock interrupt disable"]
101 #[inline(always)]
102 pub fn disable(self) -> &'a mut crate::W<REG> {
103 self.variant(CFIE_A::DISABLE)
104 }
105 #[doc = "Capture channel fall lock interrupt enable"]
106 #[inline(always)]
107 pub fn enable(self) -> &'a mut crate::W<REG> {
108 self.variant(CFIE_A::ENABLE)
109 }
110}
111impl R {
112 #[doc = "If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending.\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `crie0` field"]
113 #[inline(always)]
114 pub fn crie(&self, n: u8) -> CRIE_R {
115 #[allow(clippy::no_effect)]
116 [(); 8][n as usize];
117 CRIE_R::new(((self.bits >> (n * 2)) & 1) != 0)
118 }
119 #[doc = "Bit 0 - If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending."]
120 #[inline(always)]
121 pub fn crie0(&self) -> CRIE_R {
122 CRIE_R::new((self.bits & 1) != 0)
123 }
124 #[doc = "Bit 2 - If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending."]
125 #[inline(always)]
126 pub fn crie1(&self) -> CRIE_R {
127 CRIE_R::new(((self.bits >> 2) & 1) != 0)
128 }
129 #[doc = "Bit 4 - If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending."]
130 #[inline(always)]
131 pub fn crie2(&self) -> CRIE_R {
132 CRIE_R::new(((self.bits >> 4) & 1) != 0)
133 }
134 #[doc = "Bit 6 - If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending."]
135 #[inline(always)]
136 pub fn crie3(&self) -> CRIE_R {
137 CRIE_R::new(((self.bits >> 6) & 1) != 0)
138 }
139 #[doc = "Bit 8 - If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending."]
140 #[inline(always)]
141 pub fn crie4(&self) -> CRIE_R {
142 CRIE_R::new(((self.bits >> 8) & 1) != 0)
143 }
144 #[doc = "Bit 10 - If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending."]
145 #[inline(always)]
146 pub fn crie5(&self) -> CRIE_R {
147 CRIE_R::new(((self.bits >> 10) & 1) != 0)
148 }
149 #[doc = "Bit 12 - If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending."]
150 #[inline(always)]
151 pub fn crie6(&self) -> CRIE_R {
152 CRIE_R::new(((self.bits >> 12) & 1) != 0)
153 }
154 #[doc = "Bit 14 - If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending."]
155 #[inline(always)]
156 pub fn crie7(&self) -> CRIE_R {
157 CRIE_R::new(((self.bits >> 14) & 1) != 0)
158 }
159 #[doc = "If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending.\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `cfie0` field"]
160 #[inline(always)]
161 pub fn cfie(&self, n: u8) -> CFIE_R {
162 #[allow(clippy::no_effect)]
163 [(); 8][n as usize];
164 CFIE_R::new(((self.bits >> (n * 2 + 1)) & 1) != 0)
165 }
166 #[doc = "Bit 1 - If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending."]
167 #[inline(always)]
168 pub fn cfie0(&self) -> CFIE_R {
169 CFIE_R::new(((self.bits >> 1) & 1) != 0)
170 }
171 #[doc = "Bit 3 - If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending."]
172 #[inline(always)]
173 pub fn cfie1(&self) -> CFIE_R {
174 CFIE_R::new(((self.bits >> 3) & 1) != 0)
175 }
176 #[doc = "Bit 5 - If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending."]
177 #[inline(always)]
178 pub fn cfie2(&self) -> CFIE_R {
179 CFIE_R::new(((self.bits >> 5) & 1) != 0)
180 }
181 #[doc = "Bit 7 - If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending."]
182 #[inline(always)]
183 pub fn cfie3(&self) -> CFIE_R {
184 CFIE_R::new(((self.bits >> 7) & 1) != 0)
185 }
186 #[doc = "Bit 9 - If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending."]
187 #[inline(always)]
188 pub fn cfie4(&self) -> CFIE_R {
189 CFIE_R::new(((self.bits >> 9) & 1) != 0)
190 }
191 #[doc = "Bit 11 - If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending."]
192 #[inline(always)]
193 pub fn cfie5(&self) -> CFIE_R {
194 CFIE_R::new(((self.bits >> 11) & 1) != 0)
195 }
196 #[doc = "Bit 13 - If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending."]
197 #[inline(always)]
198 pub fn cfie6(&self) -> CFIE_R {
199 CFIE_R::new(((self.bits >> 13) & 1) != 0)
200 }
201 #[doc = "Bit 15 - If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending."]
202 #[inline(always)]
203 pub fn cfie7(&self) -> CFIE_R {
204 CFIE_R::new(((self.bits >> 15) & 1) != 0)
205 }
206}
207impl W {
208 #[doc = "If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending.\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `crie0` field"]
209 #[inline(always)]
210 #[must_use]
211 pub fn crie(&mut self, n: u8) -> CRIE_W<CIER_SPEC> {
212 #[allow(clippy::no_effect)]
213 [(); 8][n as usize];
214 CRIE_W::new(self, n * 2)
215 }
216 #[doc = "Bit 0 - If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending."]
217 #[inline(always)]
218 #[must_use]
219 pub fn crie0(&mut self) -> CRIE_W<CIER_SPEC> {
220 CRIE_W::new(self, 0)
221 }
222 #[doc = "Bit 2 - If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending."]
223 #[inline(always)]
224 #[must_use]
225 pub fn crie1(&mut self) -> CRIE_W<CIER_SPEC> {
226 CRIE_W::new(self, 2)
227 }
228 #[doc = "Bit 4 - If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending."]
229 #[inline(always)]
230 #[must_use]
231 pub fn crie2(&mut self) -> CRIE_W<CIER_SPEC> {
232 CRIE_W::new(self, 4)
233 }
234 #[doc = "Bit 6 - If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending."]
235 #[inline(always)]
236 #[must_use]
237 pub fn crie3(&mut self) -> CRIE_W<CIER_SPEC> {
238 CRIE_W::new(self, 6)
239 }
240 #[doc = "Bit 8 - If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending."]
241 #[inline(always)]
242 #[must_use]
243 pub fn crie4(&mut self) -> CRIE_W<CIER_SPEC> {
244 CRIE_W::new(self, 8)
245 }
246 #[doc = "Bit 10 - If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending."]
247 #[inline(always)]
248 #[must_use]
249 pub fn crie5(&mut self) -> CRIE_W<CIER_SPEC> {
250 CRIE_W::new(self, 10)
251 }
252 #[doc = "Bit 12 - If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending."]
253 #[inline(always)]
254 #[must_use]
255 pub fn crie6(&mut self) -> CRIE_W<CIER_SPEC> {
256 CRIE_W::new(self, 12)
257 }
258 #[doc = "Bit 14 - If the enable bit is set to 1, when the capture channel captures rising edge, it generates a capture channel pending."]
259 #[inline(always)]
260 #[must_use]
261 pub fn crie7(&mut self) -> CRIE_W<CIER_SPEC> {
262 CRIE_W::new(self, 14)
263 }
264 #[doc = "If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending.\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `cfie0` field"]
265 #[inline(always)]
266 #[must_use]
267 pub fn cfie(&mut self, n: u8) -> CFIE_W<CIER_SPEC> {
268 #[allow(clippy::no_effect)]
269 [(); 8][n as usize];
270 CFIE_W::new(self, n * 2 + 1)
271 }
272 #[doc = "Bit 1 - If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending."]
273 #[inline(always)]
274 #[must_use]
275 pub fn cfie0(&mut self) -> CFIE_W<CIER_SPEC> {
276 CFIE_W::new(self, 1)
277 }
278 #[doc = "Bit 3 - If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending."]
279 #[inline(always)]
280 #[must_use]
281 pub fn cfie1(&mut self) -> CFIE_W<CIER_SPEC> {
282 CFIE_W::new(self, 3)
283 }
284 #[doc = "Bit 5 - If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending."]
285 #[inline(always)]
286 #[must_use]
287 pub fn cfie2(&mut self) -> CFIE_W<CIER_SPEC> {
288 CFIE_W::new(self, 5)
289 }
290 #[doc = "Bit 7 - If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending."]
291 #[inline(always)]
292 #[must_use]
293 pub fn cfie3(&mut self) -> CFIE_W<CIER_SPEC> {
294 CFIE_W::new(self, 7)
295 }
296 #[doc = "Bit 9 - If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending."]
297 #[inline(always)]
298 #[must_use]
299 pub fn cfie4(&mut self) -> CFIE_W<CIER_SPEC> {
300 CFIE_W::new(self, 9)
301 }
302 #[doc = "Bit 11 - If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending."]
303 #[inline(always)]
304 #[must_use]
305 pub fn cfie5(&mut self) -> CFIE_W<CIER_SPEC> {
306 CFIE_W::new(self, 11)
307 }
308 #[doc = "Bit 13 - If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending."]
309 #[inline(always)]
310 #[must_use]
311 pub fn cfie6(&mut self) -> CFIE_W<CIER_SPEC> {
312 CFIE_W::new(self, 13)
313 }
314 #[doc = "Bit 15 - If the enable bit is set to 1, when the capture channel captures falling edge, it generates a capture channel pending."]
315 #[inline(always)]
316 #[must_use]
317 pub fn cfie7(&mut self) -> CFIE_W<CIER_SPEC> {
318 CFIE_W::new(self, 15)
319 }
320 #[doc = r" Writes raw bits to the register."]
321 #[doc = r""]
322 #[doc = r" # Safety"]
323 #[doc = r""]
324 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
325 #[inline(always)]
326 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
327 self.bits = bits;
328 self
329 }
330}
331#[doc = "Capture IRQ Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cier::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cier::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
332pub struct CIER_SPEC;
333impl crate::RegisterSpec for CIER_SPEC {
334 type Ux = u32;
335}
336#[doc = "`read()` method returns [`cier::R`](R) reader structure"]
337impl crate::Readable for CIER_SPEC {}
338#[doc = "`write(|w| ..)` method takes [`cier::W`](W) writer structure"]
339impl crate::Writable for CIER_SPEC {
340 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
341 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
342}
343#[doc = "`reset()` method sets cier to value 0"]
344impl crate::Resettable for CIER_SPEC {
345 const RESET_VALUE: Self::Ux = 0;
346}