d1_pac/iommu/
iommu_pc_ivld_enable.rs

1#[doc = "Register `iommu_pc_ivld_enable` reader"]
2pub type R = crate::R<IOMMU_PC_IVLD_ENABLE_SPEC>;
3#[doc = "Register `iommu_pc_ivld_enable` writer"]
4pub type W = crate::W<IOMMU_PC_IVLD_ENABLE_SPEC>;
5#[doc = "Field `pc_ivld_enable` reader - Enable PTW Cache invalidation operation\n\nAfter invalidation operation is completed, the bit can clear automatically.\n\nAfter or before invalidation operation starts, there is no absolute relationship between the same address switch operation and invalidation operation."]
6pub type PC_IVLD_ENABLE_R = crate::BitReader<PC_IVLD_ENABLE_A>;
7#[doc = "Enable PTW Cache invalidation operation\n\nAfter invalidation operation is completed, the bit can clear automatically.\n\nAfter or before invalidation operation starts, there is no absolute relationship between the same address switch operation and invalidation operation.\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum PC_IVLD_ENABLE_A {
10    #[doc = "0: No operation or operation is completed"]
11    NO_OPERATION_OR_COMPLETED = 0,
12    #[doc = "1: Enable invalidation operation"]
13    ENABLE = 1,
14}
15impl From<PC_IVLD_ENABLE_A> for bool {
16    #[inline(always)]
17    fn from(variant: PC_IVLD_ENABLE_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl PC_IVLD_ENABLE_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> PC_IVLD_ENABLE_A {
25        match self.bits {
26            false => PC_IVLD_ENABLE_A::NO_OPERATION_OR_COMPLETED,
27            true => PC_IVLD_ENABLE_A::ENABLE,
28        }
29    }
30    #[doc = "No operation or operation is completed"]
31    #[inline(always)]
32    pub fn is_no_operation_or_completed(&self) -> bool {
33        *self == PC_IVLD_ENABLE_A::NO_OPERATION_OR_COMPLETED
34    }
35    #[doc = "Enable invalidation operation"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == PC_IVLD_ENABLE_A::ENABLE
39    }
40}
41#[doc = "Field `pc_ivld_enable` writer - Enable PTW Cache invalidation operation\n\nAfter invalidation operation is completed, the bit can clear automatically.\n\nAfter or before invalidation operation starts, there is no absolute relationship between the same address switch operation and invalidation operation."]
42pub type PC_IVLD_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, PC_IVLD_ENABLE_A>;
43impl<'a, REG> PC_IVLD_ENABLE_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "No operation or operation is completed"]
48    #[inline(always)]
49    pub fn no_operation_or_completed(self) -> &'a mut crate::W<REG> {
50        self.variant(PC_IVLD_ENABLE_A::NO_OPERATION_OR_COMPLETED)
51    }
52    #[doc = "Enable invalidation operation"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(PC_IVLD_ENABLE_A::ENABLE)
56    }
57}
58impl R {
59    #[doc = "Bit 0 - Enable PTW Cache invalidation operation\n\nAfter invalidation operation is completed, the bit can clear automatically.\n\nAfter or before invalidation operation starts, there is no absolute relationship between the same address switch operation and invalidation operation."]
60    #[inline(always)]
61    pub fn pc_ivld_enable(&self) -> PC_IVLD_ENABLE_R {
62        PC_IVLD_ENABLE_R::new((self.bits & 1) != 0)
63    }
64}
65impl W {
66    #[doc = "Bit 0 - Enable PTW Cache invalidation operation\n\nAfter invalidation operation is completed, the bit can clear automatically.\n\nAfter or before invalidation operation starts, there is no absolute relationship between the same address switch operation and invalidation operation."]
67    #[inline(always)]
68    #[must_use]
69    pub fn pc_ivld_enable(&mut self) -> PC_IVLD_ENABLE_W<IOMMU_PC_IVLD_ENABLE_SPEC> {
70        PC_IVLD_ENABLE_W::new(self, 0)
71    }
72    #[doc = r" Writes raw bits to the register."]
73    #[doc = r""]
74    #[doc = r" # Safety"]
75    #[doc = r""]
76    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
77    #[inline(always)]
78    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
79        self.bits = bits;
80        self
81    }
82}
83#[doc = "IOMMU PC Invalidation Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_pc_ivld_enable::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_pc_ivld_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
84pub struct IOMMU_PC_IVLD_ENABLE_SPEC;
85impl crate::RegisterSpec for IOMMU_PC_IVLD_ENABLE_SPEC {
86    type Ux = u32;
87}
88#[doc = "`read()` method returns [`iommu_pc_ivld_enable::R`](R) reader structure"]
89impl crate::Readable for IOMMU_PC_IVLD_ENABLE_SPEC {}
90#[doc = "`write(|w| ..)` method takes [`iommu_pc_ivld_enable::W`](W) writer structure"]
91impl crate::Writable for IOMMU_PC_IVLD_ENABLE_SPEC {
92    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
93    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
94}
95#[doc = "`reset()` method sets iommu_pc_ivld_enable to value 0"]
96impl crate::Resettable for IOMMU_PC_IVLD_ENABLE_SPEC {
97    const RESET_VALUE: Self::Ux = 0;
98}
d1_pac/iommu/iommu_pc_ivld_enable.rs

d1_pac/iommu/
iommu_pc_ivld_enable.rs
