d1_pac/i2s_pcm/
i2s_pcm_fmt1.rs

1#[doc = "Register `i2s_pcm_fmt1` reader"]
2pub type R = crate::R<I2S_PCM_FMT1_SPEC>;
3#[doc = "Register `i2s_pcm_fmt1` writer"]
4pub type W = crate::W<I2S_PCM_FMT1_SPEC>;
5#[doc = "Field `tx_pdm` reader - Tx PCM Data Mode"]
6pub type TX_PDM_R = crate::FieldReader<TX_PDM_A>;
7#[doc = "Tx PCM Data Mode\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum TX_PDM_A {
11    #[doc = "0: Linear PCM"]
12    LINEAR = 0,
13    #[doc = "2: 8-bit u-law"]
14    U_LAW = 2,
15    #[doc = "3: 8-bit A-law"]
16    A_LAW = 3,
17}
18impl From<TX_PDM_A> for u8 {
19    #[inline(always)]
20    fn from(variant: TX_PDM_A) -> Self {
21        variant as _
22    }
23}
24impl crate::FieldSpec for TX_PDM_A {
25    type Ux = u8;
26}
27impl TX_PDM_R {
28    #[doc = "Get enumerated values variant"]
29    #[inline(always)]
30    pub const fn variant(&self) -> TX_PDM_A {
31        match self.bits {
32            0 => TX_PDM_A::LINEAR,
33            2 => TX_PDM_A::U_LAW,
34            3 => TX_PDM_A::A_LAW,
35            _ => unreachable!(),
36        }
37    }
38    #[doc = "Linear PCM"]
39    #[inline(always)]
40    pub fn is_linear(&self) -> bool {
41        *self == TX_PDM_A::LINEAR
42    }
43    #[doc = "8-bit u-law"]
44    #[inline(always)]
45    pub fn is_u_law(&self) -> bool {
46        *self == TX_PDM_A::U_LAW
47    }
48    #[doc = "8-bit A-law"]
49    #[inline(always)]
50    pub fn is_a_law(&self) -> bool {
51        *self == TX_PDM_A::A_LAW
52    }
53}
54#[doc = "Field `tx_pdm` writer - Tx PCM Data Mode"]
55pub type TX_PDM_W<'a, REG> = crate::FieldWriter<'a, REG, 2, TX_PDM_A>;
56impl<'a, REG> TX_PDM_W<'a, REG>
57where
58    REG: crate::Writable + crate::RegisterSpec,
59    REG::Ux: From<u8>,
60{
61    #[doc = "Linear PCM"]
62    #[inline(always)]
63    pub fn linear(self) -> &'a mut crate::W<REG> {
64        self.variant(TX_PDM_A::LINEAR)
65    }
66    #[doc = "8-bit u-law"]
67    #[inline(always)]
68    pub fn u_law(self) -> &'a mut crate::W<REG> {
69        self.variant(TX_PDM_A::U_LAW)
70    }
71    #[doc = "8-bit A-law"]
72    #[inline(always)]
73    pub fn a_law(self) -> &'a mut crate::W<REG> {
74        self.variant(TX_PDM_A::A_LAW)
75    }
76}
77#[doc = "Field `rx_pdm` reader - Rx PCM Data Mode"]
78pub type RX_PDM_R = crate::FieldReader<RX_PDM_A>;
79#[doc = "Rx PCM Data Mode\n\nValue on reset: 0"]
80#[derive(Clone, Copy, Debug, PartialEq, Eq)]
81#[repr(u8)]
82pub enum RX_PDM_A {
83    #[doc = "0: Linear PCM"]
84    LINEAR = 0,
85    #[doc = "2: 8-bit u-law"]
86    U_LAW = 2,
87    #[doc = "3: 8-bit A-law"]
88    A_LAW = 3,
89}
90impl From<RX_PDM_A> for u8 {
91    #[inline(always)]
92    fn from(variant: RX_PDM_A) -> Self {
93        variant as _
94    }
95}
96impl crate::FieldSpec for RX_PDM_A {
97    type Ux = u8;
98}
99impl RX_PDM_R {
100    #[doc = "Get enumerated values variant"]
101    #[inline(always)]
102    pub const fn variant(&self) -> RX_PDM_A {
103        match self.bits {
104            0 => RX_PDM_A::LINEAR,
105            2 => RX_PDM_A::U_LAW,
106            3 => RX_PDM_A::A_LAW,
107            _ => unreachable!(),
108        }
109    }
110    #[doc = "Linear PCM"]
111    #[inline(always)]
112    pub fn is_linear(&self) -> bool {
113        *self == RX_PDM_A::LINEAR
114    }
115    #[doc = "8-bit u-law"]
116    #[inline(always)]
117    pub fn is_u_law(&self) -> bool {
118        *self == RX_PDM_A::U_LAW
119    }
120    #[doc = "8-bit A-law"]
121    #[inline(always)]
122    pub fn is_a_law(&self) -> bool {
123        *self == RX_PDM_A::A_LAW
124    }
125}
126#[doc = "Field `rx_pdm` writer - Rx PCM Data Mode"]
127pub type RX_PDM_W<'a, REG> = crate::FieldWriter<'a, REG, 2, RX_PDM_A>;
128impl<'a, REG> RX_PDM_W<'a, REG>
129where
130    REG: crate::Writable + crate::RegisterSpec,
131    REG::Ux: From<u8>,
132{
133    #[doc = "Linear PCM"]
134    #[inline(always)]
135    pub fn linear(self) -> &'a mut crate::W<REG> {
136        self.variant(RX_PDM_A::LINEAR)
137    }
138    #[doc = "8-bit u-law"]
139    #[inline(always)]
140    pub fn u_law(self) -> &'a mut crate::W<REG> {
141        self.variant(RX_PDM_A::U_LAW)
142    }
143    #[doc = "8-bit A-law"]
144    #[inline(always)]
145    pub fn a_law(self) -> &'a mut crate::W<REG> {
146        self.variant(RX_PDM_A::A_LAW)
147    }
148}
149#[doc = "Field `sext` reader - Sign Extended in Slot (Sample Resolution &lt; Slot Width)"]
150pub type SEXT_R = crate::FieldReader<SEXT_A>;
151#[doc = "Sign Extended in Slot (Sample Resolution &lt; Slot Width)\n\nValue on reset: 0"]
152#[derive(Clone, Copy, Debug, PartialEq, Eq)]
153#[repr(u8)]
154pub enum SEXT_A {
155    #[doc = "0: Zeros or audio gain padding at LSB position"]
156    ZERO = 0,
157    #[doc = "1: Sign extension at MSB position"]
158    SIGN = 1,
159    #[doc = "3: Transfer 0 after each sample in each slot"]
160    TRANSFER0 = 3,
161}
162impl From<SEXT_A> for u8 {
163    #[inline(always)]
164    fn from(variant: SEXT_A) -> Self {
165        variant as _
166    }
167}
168impl crate::FieldSpec for SEXT_A {
169    type Ux = u8;
170}
171impl SEXT_R {
172    #[doc = "Get enumerated values variant"]
173    #[inline(always)]
174    pub const fn variant(&self) -> SEXT_A {
175        match self.bits {
176            0 => SEXT_A::ZERO,
177            1 => SEXT_A::SIGN,
178            3 => SEXT_A::TRANSFER0,
179            _ => unreachable!(),
180        }
181    }
182    #[doc = "Zeros or audio gain padding at LSB position"]
183    #[inline(always)]
184    pub fn is_zero(&self) -> bool {
185        *self == SEXT_A::ZERO
186    }
187    #[doc = "Sign extension at MSB position"]
188    #[inline(always)]
189    pub fn is_sign(&self) -> bool {
190        *self == SEXT_A::SIGN
191    }
192    #[doc = "Transfer 0 after each sample in each slot"]
193    #[inline(always)]
194    pub fn is_transfer0(&self) -> bool {
195        *self == SEXT_A::TRANSFER0
196    }
197}
198#[doc = "Field `sext` writer - Sign Extended in Slot (Sample Resolution &lt; Slot Width)"]
199pub type SEXT_W<'a, REG> = crate::FieldWriter<'a, REG, 2, SEXT_A>;
200impl<'a, REG> SEXT_W<'a, REG>
201where
202    REG: crate::Writable + crate::RegisterSpec,
203    REG::Ux: From<u8>,
204{
205    #[doc = "Zeros or audio gain padding at LSB position"]
206    #[inline(always)]
207    pub fn zero(self) -> &'a mut crate::W<REG> {
208        self.variant(SEXT_A::ZERO)
209    }
210    #[doc = "Sign extension at MSB position"]
211    #[inline(always)]
212    pub fn sign(self) -> &'a mut crate::W<REG> {
213        self.variant(SEXT_A::SIGN)
214    }
215    #[doc = "Transfer 0 after each sample in each slot"]
216    #[inline(always)]
217    pub fn transfer0(self) -> &'a mut crate::W<REG> {
218        self.variant(SEXT_A::TRANSFER0)
219    }
220}
221#[doc = "Field `tx_mls` reader - Tx MSB/LSB First Select"]
222pub type TX_MLS_R = crate::BitReader<TX_MLS_A>;
223#[doc = "Tx MSB/LSB First Select\n\nValue on reset: 0"]
224#[derive(Clone, Copy, Debug, PartialEq, Eq)]
225pub enum TX_MLS_A {
226    #[doc = "0: `0`"]
227    MSB = 0,
228    #[doc = "1: `1`"]
229    LSB = 1,
230}
231impl From<TX_MLS_A> for bool {
232    #[inline(always)]
233    fn from(variant: TX_MLS_A) -> Self {
234        variant as u8 != 0
235    }
236}
237impl TX_MLS_R {
238    #[doc = "Get enumerated values variant"]
239    #[inline(always)]
240    pub const fn variant(&self) -> TX_MLS_A {
241        match self.bits {
242            false => TX_MLS_A::MSB,
243            true => TX_MLS_A::LSB,
244        }
245    }
246    #[doc = "`0`"]
247    #[inline(always)]
248    pub fn is_msb(&self) -> bool {
249        *self == TX_MLS_A::MSB
250    }
251    #[doc = "`1`"]
252    #[inline(always)]
253    pub fn is_lsb(&self) -> bool {
254        *self == TX_MLS_A::LSB
255    }
256}
257#[doc = "Field `tx_mls` writer - Tx MSB/LSB First Select"]
258pub type TX_MLS_W<'a, REG> = crate::BitWriter<'a, REG, TX_MLS_A>;
259impl<'a, REG> TX_MLS_W<'a, REG>
260where
261    REG: crate::Writable + crate::RegisterSpec,
262{
263    #[doc = "`0`"]
264    #[inline(always)]
265    pub fn msb(self) -> &'a mut crate::W<REG> {
266        self.variant(TX_MLS_A::MSB)
267    }
268    #[doc = "`1`"]
269    #[inline(always)]
270    pub fn lsb(self) -> &'a mut crate::W<REG> {
271        self.variant(TX_MLS_A::LSB)
272    }
273}
274#[doc = "Field `rx_mls` reader - Rx MSB/LSB First Select"]
275pub type RX_MLS_R = crate::BitReader<RX_MLS_A>;
276#[doc = "Rx MSB/LSB First Select\n\nValue on reset: 0"]
277#[derive(Clone, Copy, Debug, PartialEq, Eq)]
278pub enum RX_MLS_A {
279    #[doc = "0: `0`"]
280    MSB = 0,
281    #[doc = "1: `1`"]
282    LSB = 1,
283}
284impl From<RX_MLS_A> for bool {
285    #[inline(always)]
286    fn from(variant: RX_MLS_A) -> Self {
287        variant as u8 != 0
288    }
289}
290impl RX_MLS_R {
291    #[doc = "Get enumerated values variant"]
292    #[inline(always)]
293    pub const fn variant(&self) -> RX_MLS_A {
294        match self.bits {
295            false => RX_MLS_A::MSB,
296            true => RX_MLS_A::LSB,
297        }
298    }
299    #[doc = "`0`"]
300    #[inline(always)]
301    pub fn is_msb(&self) -> bool {
302        *self == RX_MLS_A::MSB
303    }
304    #[doc = "`1`"]
305    #[inline(always)]
306    pub fn is_lsb(&self) -> bool {
307        *self == RX_MLS_A::LSB
308    }
309}
310#[doc = "Field `rx_mls` writer - Rx MSB/LSB First Select"]
311pub type RX_MLS_W<'a, REG> = crate::BitWriter<'a, REG, RX_MLS_A>;
312impl<'a, REG> RX_MLS_W<'a, REG>
313where
314    REG: crate::Writable + crate::RegisterSpec,
315{
316    #[doc = "`0`"]
317    #[inline(always)]
318    pub fn msb(self) -> &'a mut crate::W<REG> {
319        self.variant(RX_MLS_A::MSB)
320    }
321    #[doc = "`1`"]
322    #[inline(always)]
323    pub fn lsb(self) -> &'a mut crate::W<REG> {
324        self.variant(RX_MLS_A::LSB)
325    }
326}
327impl R {
328    #[doc = "Bits 0:1 - Tx PCM Data Mode"]
329    #[inline(always)]
330    pub fn tx_pdm(&self) -> TX_PDM_R {
331        TX_PDM_R::new((self.bits & 3) as u8)
332    }
333    #[doc = "Bits 2:3 - Rx PCM Data Mode"]
334    #[inline(always)]
335    pub fn rx_pdm(&self) -> RX_PDM_R {
336        RX_PDM_R::new(((self.bits >> 2) & 3) as u8)
337    }
338    #[doc = "Bits 4:5 - Sign Extended in Slot (Sample Resolution &lt; Slot Width)"]
339    #[inline(always)]
340    pub fn sext(&self) -> SEXT_R {
341        SEXT_R::new(((self.bits >> 4) & 3) as u8)
342    }
343    #[doc = "Bit 6 - Tx MSB/LSB First Select"]
344    #[inline(always)]
345    pub fn tx_mls(&self) -> TX_MLS_R {
346        TX_MLS_R::new(((self.bits >> 6) & 1) != 0)
347    }
348    #[doc = "Bit 7 - Rx MSB/LSB First Select"]
349    #[inline(always)]
350    pub fn rx_mls(&self) -> RX_MLS_R {
351        RX_MLS_R::new(((self.bits >> 7) & 1) != 0)
352    }
353}
354impl W {
355    #[doc = "Bits 0:1 - Tx PCM Data Mode"]
356    #[inline(always)]
357    #[must_use]
358    pub fn tx_pdm(&mut self) -> TX_PDM_W<I2S_PCM_FMT1_SPEC> {
359        TX_PDM_W::new(self, 0)
360    }
361    #[doc = "Bits 2:3 - Rx PCM Data Mode"]
362    #[inline(always)]
363    #[must_use]
364    pub fn rx_pdm(&mut self) -> RX_PDM_W<I2S_PCM_FMT1_SPEC> {
365        RX_PDM_W::new(self, 2)
366    }
367    #[doc = "Bits 4:5 - Sign Extended in Slot (Sample Resolution &lt; Slot Width)"]
368    #[inline(always)]
369    #[must_use]
370    pub fn sext(&mut self) -> SEXT_W<I2S_PCM_FMT1_SPEC> {
371        SEXT_W::new(self, 4)
372    }
373    #[doc = "Bit 6 - Tx MSB/LSB First Select"]
374    #[inline(always)]
375    #[must_use]
376    pub fn tx_mls(&mut self) -> TX_MLS_W<I2S_PCM_FMT1_SPEC> {
377        TX_MLS_W::new(self, 6)
378    }
379    #[doc = "Bit 7 - Rx MSB/LSB First Select"]
380    #[inline(always)]
381    #[must_use]
382    pub fn rx_mls(&mut self) -> RX_MLS_W<I2S_PCM_FMT1_SPEC> {
383        RX_MLS_W::new(self, 7)
384    }
385    #[doc = r" Writes raw bits to the register."]
386    #[doc = r""]
387    #[doc = r" # Safety"]
388    #[doc = r""]
389    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
390    #[inline(always)]
391    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
392        self.bits = bits;
393        self
394    }
395}
396#[doc = "I2S/PCM Format Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s_pcm_fmt1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s_pcm_fmt1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
397pub struct I2S_PCM_FMT1_SPEC;
398impl crate::RegisterSpec for I2S_PCM_FMT1_SPEC {
399    type Ux = u32;
400}
401#[doc = "`read()` method returns [`i2s_pcm_fmt1::R`](R) reader structure"]
402impl crate::Readable for I2S_PCM_FMT1_SPEC {}
403#[doc = "`write(|w| ..)` method takes [`i2s_pcm_fmt1::W`](W) writer structure"]
404impl crate::Writable for I2S_PCM_FMT1_SPEC {
405    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
406    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
407}
408#[doc = "`reset()` method sets i2s_pcm_fmt1 to value 0"]
409impl crate::Resettable for I2S_PCM_FMT1_SPEC {
410    const RESET_VALUE: Self::Ux = 0;
411}
d1_pac/i2s_pcm/i2s_pcm_fmt1.rs

d1_pac/i2s_pcm/
i2s_pcm_fmt1.rs
