d1_pac/i2s_pcm/
i2s_pcm_clkd.rs

1#[doc = "Register `i2s_pcm_clkd` reader"]
2pub type R = crate::R<I2S_PCM_CLKD_SPEC>;
3#[doc = "Register `i2s_pcm_clkd` writer"]
4pub type W = crate::W<I2S_PCM_CLKD_SPEC>;
5#[doc = "Field `mclkdiv` reader - MCLK Divide ratio from PLL_AUDIO"]
6pub type MCLKDIV_R = crate::FieldReader<MCLKDIV_A>;
7#[doc = "MCLK Divide ratio from PLL_AUDIO\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum MCLKDIV_A {
11    #[doc = "1: Divide by 1"]
12    DIV_1 = 1,
13    #[doc = "2: Divide by 2"]
14    DIV_2 = 2,
15    #[doc = "3: Divide by 4"]
16    DIV_4 = 3,
17    #[doc = "4: Divide by 6"]
18    DIV_6 = 4,
19    #[doc = "5: Divide by 8"]
20    DIV_8 = 5,
21    #[doc = "6: Divide by 12"]
22    DIV_12 = 6,
23    #[doc = "7: Divide by 16"]
24    DIV_16 = 7,
25    #[doc = "8: Divide by 24"]
26    DIV_24 = 8,
27    #[doc = "9: Divide by 32"]
28    DIV_32 = 9,
29    #[doc = "10: Divide by 48"]
30    DIV_48 = 10,
31    #[doc = "11: Divide by 64"]
32    DIV_64 = 11,
33    #[doc = "12: Divide by 96"]
34    DIV_96 = 12,
35    #[doc = "13: Divide by 128"]
36    DIV_128 = 13,
37    #[doc = "14: Divide by 176"]
38    DIV_176 = 14,
39    #[doc = "15: Divide by 192"]
40    DIV_192 = 15,
41}
42impl From<MCLKDIV_A> for u8 {
43    #[inline(always)]
44    fn from(variant: MCLKDIV_A) -> Self {
45        variant as _
46    }
47}
48impl crate::FieldSpec for MCLKDIV_A {
49    type Ux = u8;
50}
51impl MCLKDIV_R {
52    #[doc = "Get enumerated values variant"]
53    #[inline(always)]
54    pub const fn variant(&self) -> MCLKDIV_A {
55        match self.bits {
56            1 => MCLKDIV_A::DIV_1,
57            2 => MCLKDIV_A::DIV_2,
58            3 => MCLKDIV_A::DIV_4,
59            4 => MCLKDIV_A::DIV_6,
60            5 => MCLKDIV_A::DIV_8,
61            6 => MCLKDIV_A::DIV_12,
62            7 => MCLKDIV_A::DIV_16,
63            8 => MCLKDIV_A::DIV_24,
64            9 => MCLKDIV_A::DIV_32,
65            10 => MCLKDIV_A::DIV_48,
66            11 => MCLKDIV_A::DIV_64,
67            12 => MCLKDIV_A::DIV_96,
68            13 => MCLKDIV_A::DIV_128,
69            14 => MCLKDIV_A::DIV_176,
70            15 => MCLKDIV_A::DIV_192,
71            _ => unreachable!(),
72        }
73    }
74    #[doc = "Divide by 1"]
75    #[inline(always)]
76    pub fn is_div_1(&self) -> bool {
77        *self == MCLKDIV_A::DIV_1
78    }
79    #[doc = "Divide by 2"]
80    #[inline(always)]
81    pub fn is_div_2(&self) -> bool {
82        *self == MCLKDIV_A::DIV_2
83    }
84    #[doc = "Divide by 4"]
85    #[inline(always)]
86    pub fn is_div_4(&self) -> bool {
87        *self == MCLKDIV_A::DIV_4
88    }
89    #[doc = "Divide by 6"]
90    #[inline(always)]
91    pub fn is_div_6(&self) -> bool {
92        *self == MCLKDIV_A::DIV_6
93    }
94    #[doc = "Divide by 8"]
95    #[inline(always)]
96    pub fn is_div_8(&self) -> bool {
97        *self == MCLKDIV_A::DIV_8
98    }
99    #[doc = "Divide by 12"]
100    #[inline(always)]
101    pub fn is_div_12(&self) -> bool {
102        *self == MCLKDIV_A::DIV_12
103    }
104    #[doc = "Divide by 16"]
105    #[inline(always)]
106    pub fn is_div_16(&self) -> bool {
107        *self == MCLKDIV_A::DIV_16
108    }
109    #[doc = "Divide by 24"]
110    #[inline(always)]
111    pub fn is_div_24(&self) -> bool {
112        *self == MCLKDIV_A::DIV_24
113    }
114    #[doc = "Divide by 32"]
115    #[inline(always)]
116    pub fn is_div_32(&self) -> bool {
117        *self == MCLKDIV_A::DIV_32
118    }
119    #[doc = "Divide by 48"]
120    #[inline(always)]
121    pub fn is_div_48(&self) -> bool {
122        *self == MCLKDIV_A::DIV_48
123    }
124    #[doc = "Divide by 64"]
125    #[inline(always)]
126    pub fn is_div_64(&self) -> bool {
127        *self == MCLKDIV_A::DIV_64
128    }
129    #[doc = "Divide by 96"]
130    #[inline(always)]
131    pub fn is_div_96(&self) -> bool {
132        *self == MCLKDIV_A::DIV_96
133    }
134    #[doc = "Divide by 128"]
135    #[inline(always)]
136    pub fn is_div_128(&self) -> bool {
137        *self == MCLKDIV_A::DIV_128
138    }
139    #[doc = "Divide by 176"]
140    #[inline(always)]
141    pub fn is_div_176(&self) -> bool {
142        *self == MCLKDIV_A::DIV_176
143    }
144    #[doc = "Divide by 192"]
145    #[inline(always)]
146    pub fn is_div_192(&self) -> bool {
147        *self == MCLKDIV_A::DIV_192
148    }
149}
150#[doc = "Field `mclkdiv` writer - MCLK Divide ratio from PLL_AUDIO"]
151pub type MCLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 4, MCLKDIV_A>;
152impl<'a, REG> MCLKDIV_W<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155    REG::Ux: From<u8>,
156{
157    #[doc = "Divide by 1"]
158    #[inline(always)]
159    pub fn div_1(self) -> &'a mut crate::W<REG> {
160        self.variant(MCLKDIV_A::DIV_1)
161    }
162    #[doc = "Divide by 2"]
163    #[inline(always)]
164    pub fn div_2(self) -> &'a mut crate::W<REG> {
165        self.variant(MCLKDIV_A::DIV_2)
166    }
167    #[doc = "Divide by 4"]
168    #[inline(always)]
169    pub fn div_4(self) -> &'a mut crate::W<REG> {
170        self.variant(MCLKDIV_A::DIV_4)
171    }
172    #[doc = "Divide by 6"]
173    #[inline(always)]
174    pub fn div_6(self) -> &'a mut crate::W<REG> {
175        self.variant(MCLKDIV_A::DIV_6)
176    }
177    #[doc = "Divide by 8"]
178    #[inline(always)]
179    pub fn div_8(self) -> &'a mut crate::W<REG> {
180        self.variant(MCLKDIV_A::DIV_8)
181    }
182    #[doc = "Divide by 12"]
183    #[inline(always)]
184    pub fn div_12(self) -> &'a mut crate::W<REG> {
185        self.variant(MCLKDIV_A::DIV_12)
186    }
187    #[doc = "Divide by 16"]
188    #[inline(always)]
189    pub fn div_16(self) -> &'a mut crate::W<REG> {
190        self.variant(MCLKDIV_A::DIV_16)
191    }
192    #[doc = "Divide by 24"]
193    #[inline(always)]
194    pub fn div_24(self) -> &'a mut crate::W<REG> {
195        self.variant(MCLKDIV_A::DIV_24)
196    }
197    #[doc = "Divide by 32"]
198    #[inline(always)]
199    pub fn div_32(self) -> &'a mut crate::W<REG> {
200        self.variant(MCLKDIV_A::DIV_32)
201    }
202    #[doc = "Divide by 48"]
203    #[inline(always)]
204    pub fn div_48(self) -> &'a mut crate::W<REG> {
205        self.variant(MCLKDIV_A::DIV_48)
206    }
207    #[doc = "Divide by 64"]
208    #[inline(always)]
209    pub fn div_64(self) -> &'a mut crate::W<REG> {
210        self.variant(MCLKDIV_A::DIV_64)
211    }
212    #[doc = "Divide by 96"]
213    #[inline(always)]
214    pub fn div_96(self) -> &'a mut crate::W<REG> {
215        self.variant(MCLKDIV_A::DIV_96)
216    }
217    #[doc = "Divide by 128"]
218    #[inline(always)]
219    pub fn div_128(self) -> &'a mut crate::W<REG> {
220        self.variant(MCLKDIV_A::DIV_128)
221    }
222    #[doc = "Divide by 176"]
223    #[inline(always)]
224    pub fn div_176(self) -> &'a mut crate::W<REG> {
225        self.variant(MCLKDIV_A::DIV_176)
226    }
227    #[doc = "Divide by 192"]
228    #[inline(always)]
229    pub fn div_192(self) -> &'a mut crate::W<REG> {
230        self.variant(MCLKDIV_A::DIV_192)
231    }
232}
233#[doc = "Field `bclkdiv` reader - BCLK Divide ratio from PLL_AUDIO"]
234pub type BCLKDIV_R = crate::FieldReader<BCLKDIV_A>;
235#[doc = "BCLK Divide ratio from PLL_AUDIO\n\nValue on reset: 0"]
236#[derive(Clone, Copy, Debug, PartialEq, Eq)]
237#[repr(u8)]
238pub enum BCLKDIV_A {
239    #[doc = "1: Divide by 1"]
240    DIV_1 = 1,
241    #[doc = "2: Divide by 2"]
242    DIV_2 = 2,
243    #[doc = "3: Divide by 4"]
244    DIV_4 = 3,
245    #[doc = "4: Divide by 6"]
246    DIV_6 = 4,
247    #[doc = "5: Divide by 8"]
248    DIV_8 = 5,
249    #[doc = "6: Divide by 12"]
250    DIV_12 = 6,
251    #[doc = "7: Divide by 16"]
252    DIV_16 = 7,
253    #[doc = "8: Divide by 24"]
254    DIV_24 = 8,
255    #[doc = "9: Divide by 32"]
256    DIV_32 = 9,
257    #[doc = "10: Divide by 48"]
258    DIV_48 = 10,
259    #[doc = "11: Divide by 64"]
260    DIV_64 = 11,
261    #[doc = "12: Divide by 96"]
262    DIV_96 = 12,
263    #[doc = "13: Divide by 128"]
264    DIV_128 = 13,
265    #[doc = "14: Divide by 176"]
266    DIV_176 = 14,
267    #[doc = "15: Divide by 192"]
268    DIV_192 = 15,
269}
270impl From<BCLKDIV_A> for u8 {
271    #[inline(always)]
272    fn from(variant: BCLKDIV_A) -> Self {
273        variant as _
274    }
275}
276impl crate::FieldSpec for BCLKDIV_A {
277    type Ux = u8;
278}
279impl BCLKDIV_R {
280    #[doc = "Get enumerated values variant"]
281    #[inline(always)]
282    pub const fn variant(&self) -> BCLKDIV_A {
283        match self.bits {
284            1 => BCLKDIV_A::DIV_1,
285            2 => BCLKDIV_A::DIV_2,
286            3 => BCLKDIV_A::DIV_4,
287            4 => BCLKDIV_A::DIV_6,
288            5 => BCLKDIV_A::DIV_8,
289            6 => BCLKDIV_A::DIV_12,
290            7 => BCLKDIV_A::DIV_16,
291            8 => BCLKDIV_A::DIV_24,
292            9 => BCLKDIV_A::DIV_32,
293            10 => BCLKDIV_A::DIV_48,
294            11 => BCLKDIV_A::DIV_64,
295            12 => BCLKDIV_A::DIV_96,
296            13 => BCLKDIV_A::DIV_128,
297            14 => BCLKDIV_A::DIV_176,
298            15 => BCLKDIV_A::DIV_192,
299            _ => unreachable!(),
300        }
301    }
302    #[doc = "Divide by 1"]
303    #[inline(always)]
304    pub fn is_div_1(&self) -> bool {
305        *self == BCLKDIV_A::DIV_1
306    }
307    #[doc = "Divide by 2"]
308    #[inline(always)]
309    pub fn is_div_2(&self) -> bool {
310        *self == BCLKDIV_A::DIV_2
311    }
312    #[doc = "Divide by 4"]
313    #[inline(always)]
314    pub fn is_div_4(&self) -> bool {
315        *self == BCLKDIV_A::DIV_4
316    }
317    #[doc = "Divide by 6"]
318    #[inline(always)]
319    pub fn is_div_6(&self) -> bool {
320        *self == BCLKDIV_A::DIV_6
321    }
322    #[doc = "Divide by 8"]
323    #[inline(always)]
324    pub fn is_div_8(&self) -> bool {
325        *self == BCLKDIV_A::DIV_8
326    }
327    #[doc = "Divide by 12"]
328    #[inline(always)]
329    pub fn is_div_12(&self) -> bool {
330        *self == BCLKDIV_A::DIV_12
331    }
332    #[doc = "Divide by 16"]
333    #[inline(always)]
334    pub fn is_div_16(&self) -> bool {
335        *self == BCLKDIV_A::DIV_16
336    }
337    #[doc = "Divide by 24"]
338    #[inline(always)]
339    pub fn is_div_24(&self) -> bool {
340        *self == BCLKDIV_A::DIV_24
341    }
342    #[doc = "Divide by 32"]
343    #[inline(always)]
344    pub fn is_div_32(&self) -> bool {
345        *self == BCLKDIV_A::DIV_32
346    }
347    #[doc = "Divide by 48"]
348    #[inline(always)]
349    pub fn is_div_48(&self) -> bool {
350        *self == BCLKDIV_A::DIV_48
351    }
352    #[doc = "Divide by 64"]
353    #[inline(always)]
354    pub fn is_div_64(&self) -> bool {
355        *self == BCLKDIV_A::DIV_64
356    }
357    #[doc = "Divide by 96"]
358    #[inline(always)]
359    pub fn is_div_96(&self) -> bool {
360        *self == BCLKDIV_A::DIV_96
361    }
362    #[doc = "Divide by 128"]
363    #[inline(always)]
364    pub fn is_div_128(&self) -> bool {
365        *self == BCLKDIV_A::DIV_128
366    }
367    #[doc = "Divide by 176"]
368    #[inline(always)]
369    pub fn is_div_176(&self) -> bool {
370        *self == BCLKDIV_A::DIV_176
371    }
372    #[doc = "Divide by 192"]
373    #[inline(always)]
374    pub fn is_div_192(&self) -> bool {
375        *self == BCLKDIV_A::DIV_192
376    }
377}
378#[doc = "Field `bclkdiv` writer - BCLK Divide ratio from PLL_AUDIO"]
379pub type BCLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 4, BCLKDIV_A>;
380impl<'a, REG> BCLKDIV_W<'a, REG>
381where
382    REG: crate::Writable + crate::RegisterSpec,
383    REG::Ux: From<u8>,
384{
385    #[doc = "Divide by 1"]
386    #[inline(always)]
387    pub fn div_1(self) -> &'a mut crate::W<REG> {
388        self.variant(BCLKDIV_A::DIV_1)
389    }
390    #[doc = "Divide by 2"]
391    #[inline(always)]
392    pub fn div_2(self) -> &'a mut crate::W<REG> {
393        self.variant(BCLKDIV_A::DIV_2)
394    }
395    #[doc = "Divide by 4"]
396    #[inline(always)]
397    pub fn div_4(self) -> &'a mut crate::W<REG> {
398        self.variant(BCLKDIV_A::DIV_4)
399    }
400    #[doc = "Divide by 6"]
401    #[inline(always)]
402    pub fn div_6(self) -> &'a mut crate::W<REG> {
403        self.variant(BCLKDIV_A::DIV_6)
404    }
405    #[doc = "Divide by 8"]
406    #[inline(always)]
407    pub fn div_8(self) -> &'a mut crate::W<REG> {
408        self.variant(BCLKDIV_A::DIV_8)
409    }
410    #[doc = "Divide by 12"]
411    #[inline(always)]
412    pub fn div_12(self) -> &'a mut crate::W<REG> {
413        self.variant(BCLKDIV_A::DIV_12)
414    }
415    #[doc = "Divide by 16"]
416    #[inline(always)]
417    pub fn div_16(self) -> &'a mut crate::W<REG> {
418        self.variant(BCLKDIV_A::DIV_16)
419    }
420    #[doc = "Divide by 24"]
421    #[inline(always)]
422    pub fn div_24(self) -> &'a mut crate::W<REG> {
423        self.variant(BCLKDIV_A::DIV_24)
424    }
425    #[doc = "Divide by 32"]
426    #[inline(always)]
427    pub fn div_32(self) -> &'a mut crate::W<REG> {
428        self.variant(BCLKDIV_A::DIV_32)
429    }
430    #[doc = "Divide by 48"]
431    #[inline(always)]
432    pub fn div_48(self) -> &'a mut crate::W<REG> {
433        self.variant(BCLKDIV_A::DIV_48)
434    }
435    #[doc = "Divide by 64"]
436    #[inline(always)]
437    pub fn div_64(self) -> &'a mut crate::W<REG> {
438        self.variant(BCLKDIV_A::DIV_64)
439    }
440    #[doc = "Divide by 96"]
441    #[inline(always)]
442    pub fn div_96(self) -> &'a mut crate::W<REG> {
443        self.variant(BCLKDIV_A::DIV_96)
444    }
445    #[doc = "Divide by 128"]
446    #[inline(always)]
447    pub fn div_128(self) -> &'a mut crate::W<REG> {
448        self.variant(BCLKDIV_A::DIV_128)
449    }
450    #[doc = "Divide by 176"]
451    #[inline(always)]
452    pub fn div_176(self) -> &'a mut crate::W<REG> {
453        self.variant(BCLKDIV_A::DIV_176)
454    }
455    #[doc = "Divide by 192"]
456    #[inline(always)]
457    pub fn div_192(self) -> &'a mut crate::W<REG> {
458        self.variant(BCLKDIV_A::DIV_192)
459    }
460}
461#[doc = "Field `mclko_en` reader - MCLK Output Enable\n\nNote: Whether in slave or master mode, when this bit is set to ‘1’, MCLK should be output."]
462pub type MCLKO_EN_R = crate::BitReader<MCLKO_EN_A>;
463#[doc = "MCLK Output Enable\n\nNote: Whether in slave or master mode, when this bit is set to ‘1’, MCLK should be output.\n\nValue on reset: 0"]
464#[derive(Clone, Copy, Debug, PartialEq, Eq)]
465pub enum MCLKO_EN_A {
466    #[doc = "0: Disable MCLK Output"]
467    DISABLE = 0,
468    #[doc = "1: Enable MCLK Output"]
469    ENABLE = 1,
470}
471impl From<MCLKO_EN_A> for bool {
472    #[inline(always)]
473    fn from(variant: MCLKO_EN_A) -> Self {
474        variant as u8 != 0
475    }
476}
477impl MCLKO_EN_R {
478    #[doc = "Get enumerated values variant"]
479    #[inline(always)]
480    pub const fn variant(&self) -> MCLKO_EN_A {
481        match self.bits {
482            false => MCLKO_EN_A::DISABLE,
483            true => MCLKO_EN_A::ENABLE,
484        }
485    }
486    #[doc = "Disable MCLK Output"]
487    #[inline(always)]
488    pub fn is_disable(&self) -> bool {
489        *self == MCLKO_EN_A::DISABLE
490    }
491    #[doc = "Enable MCLK Output"]
492    #[inline(always)]
493    pub fn is_enable(&self) -> bool {
494        *self == MCLKO_EN_A::ENABLE
495    }
496}
497#[doc = "Field `mclko_en` writer - MCLK Output Enable\n\nNote: Whether in slave or master mode, when this bit is set to ‘1’, MCLK should be output."]
498pub type MCLKO_EN_W<'a, REG> = crate::BitWriter<'a, REG, MCLKO_EN_A>;
499impl<'a, REG> MCLKO_EN_W<'a, REG>
500where
501    REG: crate::Writable + crate::RegisterSpec,
502{
503    #[doc = "Disable MCLK Output"]
504    #[inline(always)]
505    pub fn disable(self) -> &'a mut crate::W<REG> {
506        self.variant(MCLKO_EN_A::DISABLE)
507    }
508    #[doc = "Enable MCLK Output"]
509    #[inline(always)]
510    pub fn enable(self) -> &'a mut crate::W<REG> {
511        self.variant(MCLKO_EN_A::ENABLE)
512    }
513}
514impl R {
515    #[doc = "Bits 0:3 - MCLK Divide ratio from PLL_AUDIO"]
516    #[inline(always)]
517    pub fn mclkdiv(&self) -> MCLKDIV_R {
518        MCLKDIV_R::new((self.bits & 0x0f) as u8)
519    }
520    #[doc = "Bits 4:7 - BCLK Divide ratio from PLL_AUDIO"]
521    #[inline(always)]
522    pub fn bclkdiv(&self) -> BCLKDIV_R {
523        BCLKDIV_R::new(((self.bits >> 4) & 0x0f) as u8)
524    }
525    #[doc = "Bit 8 - MCLK Output Enable\n\nNote: Whether in slave or master mode, when this bit is set to ‘1’, MCLK should be output."]
526    #[inline(always)]
527    pub fn mclko_en(&self) -> MCLKO_EN_R {
528        MCLKO_EN_R::new(((self.bits >> 8) & 1) != 0)
529    }
530}
531impl W {
532    #[doc = "Bits 0:3 - MCLK Divide ratio from PLL_AUDIO"]
533    #[inline(always)]
534    #[must_use]
535    pub fn mclkdiv(&mut self) -> MCLKDIV_W<I2S_PCM_CLKD_SPEC> {
536        MCLKDIV_W::new(self, 0)
537    }
538    #[doc = "Bits 4:7 - BCLK Divide ratio from PLL_AUDIO"]
539    #[inline(always)]
540    #[must_use]
541    pub fn bclkdiv(&mut self) -> BCLKDIV_W<I2S_PCM_CLKD_SPEC> {
542        BCLKDIV_W::new(self, 4)
543    }
544    #[doc = "Bit 8 - MCLK Output Enable\n\nNote: Whether in slave or master mode, when this bit is set to ‘1’, MCLK should be output."]
545    #[inline(always)]
546    #[must_use]
547    pub fn mclko_en(&mut self) -> MCLKO_EN_W<I2S_PCM_CLKD_SPEC> {
548        MCLKO_EN_W::new(self, 8)
549    }
550    #[doc = r" Writes raw bits to the register."]
551    #[doc = r""]
552    #[doc = r" # Safety"]
553    #[doc = r""]
554    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
555    #[inline(always)]
556    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
557        self.bits = bits;
558        self
559    }
560}
561#[doc = "I2S/PCM Clock Divide Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s_pcm_clkd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s_pcm_clkd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
562pub struct I2S_PCM_CLKD_SPEC;
563impl crate::RegisterSpec for I2S_PCM_CLKD_SPEC {
564    type Ux = u32;
565}
566#[doc = "`read()` method returns [`i2s_pcm_clkd::R`](R) reader structure"]
567impl crate::Readable for I2S_PCM_CLKD_SPEC {}
568#[doc = "`write(|w| ..)` method takes [`i2s_pcm_clkd::W`](W) writer structure"]
569impl crate::Writable for I2S_PCM_CLKD_SPEC {
570    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
571    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
572}
573#[doc = "`reset()` method sets i2s_pcm_clkd to value 0"]
574impl crate::Resettable for I2S_PCM_CLKD_SPEC {
575    const RESET_VALUE: Self::Ux = 0;
576}
d1_pac/i2s_pcm/i2s_pcm_clkd.rs

d1_pac/i2s_pcm/
i2s_pcm_clkd.rs
