d1_pac/hs_timer/
hs_tmr_irq_stas.rs

1#[doc = "Register `hs_tmr_irq_stas` reader"]
2pub type R = crate::R<HS_TMR_IRQ_STAS_SPEC>;
3#[doc = "Register `hs_tmr_irq_stas` writer"]
4pub type W = crate::W<HS_TMR_IRQ_STAS_SPEC>;
5#[doc = "Field `hs_tmr_irq_pend[0-1]` reader - HSTimer IRQ Pending"]
6pub type HS_TMR_IRQ_PEND_R = crate::BitReader<HS_TMR_IRQ_PEND_A>;
7#[doc = "HSTimer IRQ Pending\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum HS_TMR_IRQ_PEND_A {
10    #[doc = "0: `0`"]
11    NO_EFFECT = 0,
12    #[doc = "1: `1`"]
13    PENDING = 1,
14}
15impl From<HS_TMR_IRQ_PEND_A> for bool {
16    #[inline(always)]
17    fn from(variant: HS_TMR_IRQ_PEND_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl HS_TMR_IRQ_PEND_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> HS_TMR_IRQ_PEND_A {
25        match self.bits {
26            false => HS_TMR_IRQ_PEND_A::NO_EFFECT,
27            true => HS_TMR_IRQ_PEND_A::PENDING,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_no_effect(&self) -> bool {
33        *self == HS_TMR_IRQ_PEND_A::NO_EFFECT
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_pending(&self) -> bool {
38        *self == HS_TMR_IRQ_PEND_A::PENDING
39    }
40}
41#[doc = "Field `hs_tmr_irq_pend[0-1]` writer - HSTimer IRQ Pending"]
42pub type HS_TMR_IRQ_PEND_W<'a, REG> = crate::BitWriter1C<'a, REG, HS_TMR_IRQ_PEND_A>;
43impl<'a, REG> HS_TMR_IRQ_PEND_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn no_effect(self) -> &'a mut crate::W<REG> {
50        self.variant(HS_TMR_IRQ_PEND_A::NO_EFFECT)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn pending(self) -> &'a mut crate::W<REG> {
55        self.variant(HS_TMR_IRQ_PEND_A::PENDING)
56    }
57}
58impl R {
59    #[doc = "HSTimer IRQ Pending\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `hs_tmr0_irq_pend` field"]
60    #[inline(always)]
61    pub fn hs_tmr_irq_pend(&self, n: u8) -> HS_TMR_IRQ_PEND_R {
62        #[allow(clippy::no_effect)]
63        [(); 2][n as usize];
64        HS_TMR_IRQ_PEND_R::new(((self.bits >> n) & 1) != 0)
65    }
66    #[doc = "Bit 0 - HSTimer IRQ Pending"]
67    #[inline(always)]
68    pub fn hs_tmr0_irq_pend(&self) -> HS_TMR_IRQ_PEND_R {
69        HS_TMR_IRQ_PEND_R::new((self.bits & 1) != 0)
70    }
71    #[doc = "Bit 1 - HSTimer IRQ Pending"]
72    #[inline(always)]
73    pub fn hs_tmr1_irq_pend(&self) -> HS_TMR_IRQ_PEND_R {
74        HS_TMR_IRQ_PEND_R::new(((self.bits >> 1) & 1) != 0)
75    }
76}
77impl W {
78    #[doc = "HSTimer IRQ Pending\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `hs_tmr0_irq_pend` field"]
79    #[inline(always)]
80    #[must_use]
81    pub fn hs_tmr_irq_pend(&mut self, n: u8) -> HS_TMR_IRQ_PEND_W<HS_TMR_IRQ_STAS_SPEC> {
82        #[allow(clippy::no_effect)]
83        [(); 2][n as usize];
84        HS_TMR_IRQ_PEND_W::new(self, n)
85    }
86    #[doc = "Bit 0 - HSTimer IRQ Pending"]
87    #[inline(always)]
88    #[must_use]
89    pub fn hs_tmr0_irq_pend(&mut self) -> HS_TMR_IRQ_PEND_W<HS_TMR_IRQ_STAS_SPEC> {
90        HS_TMR_IRQ_PEND_W::new(self, 0)
91    }
92    #[doc = "Bit 1 - HSTimer IRQ Pending"]
93    #[inline(always)]
94    #[must_use]
95    pub fn hs_tmr1_irq_pend(&mut self) -> HS_TMR_IRQ_PEND_W<HS_TMR_IRQ_STAS_SPEC> {
96        HS_TMR_IRQ_PEND_W::new(self, 1)
97    }
98    #[doc = r" Writes raw bits to the register."]
99    #[doc = r""]
100    #[doc = r" # Safety"]
101    #[doc = r""]
102    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
103    #[inline(always)]
104    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
105        self.bits = bits;
106        self
107    }
108}
109#[doc = "HS Timer Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hs_tmr_irq_stas::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hs_tmr_irq_stas::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
110pub struct HS_TMR_IRQ_STAS_SPEC;
111impl crate::RegisterSpec for HS_TMR_IRQ_STAS_SPEC {
112    type Ux = u32;
113}
114#[doc = "`read()` method returns [`hs_tmr_irq_stas::R`](R) reader structure"]
115impl crate::Readable for HS_TMR_IRQ_STAS_SPEC {}
116#[doc = "`write(|w| ..)` method takes [`hs_tmr_irq_stas::W`](W) writer structure"]
117impl crate::Writable for HS_TMR_IRQ_STAS_SPEC {
118    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
119    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x01;
120}
121#[doc = "`reset()` method sets hs_tmr_irq_stas to value 0"]
122impl crate::Resettable for HS_TMR_IRQ_STAS_SPEC {
123    const RESET_VALUE: Self::Ux = 0;
124}
d1_pac/hs_timer/hs_tmr_irq_stas.rs

d1_pac/hs_timer/
hs_tmr_irq_stas.rs
