d1_pac/gpio/
pg_drv1.rs

1#[doc = "Register `pg_drv1` reader"]
2pub type R = crate::R<PG_DRV1_SPEC>;
3#[doc = "Register `pg_drv1` writer"]
4pub type W = crate::W<PG_DRV1_SPEC>;
5#[doc = "Field `pg_drv[8-15]` reader - PG Multi_Driving Select"]
6pub type PG_DRV_R = crate::FieldReader<PG_DRV_A>;
7#[doc = "PG Multi_Driving Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum PG_DRV_A {
11    #[doc = "0: `0`"]
12    L0 = 0,
13    #[doc = "1: `1`"]
14    L1 = 1,
15    #[doc = "2: `10`"]
16    L2 = 2,
17    #[doc = "3: `11`"]
18    L3 = 3,
19}
20impl From<PG_DRV_A> for u8 {
21    #[inline(always)]
22    fn from(variant: PG_DRV_A) -> Self {
23        variant as _
24    }
25}
26impl crate::FieldSpec for PG_DRV_A {
27    type Ux = u8;
28}
29impl PG_DRV_R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> PG_DRV_A {
33        match self.bits {
34            0 => PG_DRV_A::L0,
35            1 => PG_DRV_A::L1,
36            2 => PG_DRV_A::L2,
37            3 => PG_DRV_A::L3,
38            _ => unreachable!(),
39        }
40    }
41    #[doc = "`0`"]
42    #[inline(always)]
43    pub fn is_l0(&self) -> bool {
44        *self == PG_DRV_A::L0
45    }
46    #[doc = "`1`"]
47    #[inline(always)]
48    pub fn is_l1(&self) -> bool {
49        *self == PG_DRV_A::L1
50    }
51    #[doc = "`10`"]
52    #[inline(always)]
53    pub fn is_l2(&self) -> bool {
54        *self == PG_DRV_A::L2
55    }
56    #[doc = "`11`"]
57    #[inline(always)]
58    pub fn is_l3(&self) -> bool {
59        *self == PG_DRV_A::L3
60    }
61}
62#[doc = "Field `pg_drv[8-15]` writer - PG Multi_Driving Select"]
63pub type PG_DRV_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, PG_DRV_A>;
64impl<'a, REG> PG_DRV_W<'a, REG>
65where
66    REG: crate::Writable + crate::RegisterSpec,
67    REG::Ux: From<u8>,
68{
69    #[doc = "`0`"]
70    #[inline(always)]
71    pub fn l0(self) -> &'a mut crate::W<REG> {
72        self.variant(PG_DRV_A::L0)
73    }
74    #[doc = "`1`"]
75    #[inline(always)]
76    pub fn l1(self) -> &'a mut crate::W<REG> {
77        self.variant(PG_DRV_A::L1)
78    }
79    #[doc = "`10`"]
80    #[inline(always)]
81    pub fn l2(self) -> &'a mut crate::W<REG> {
82        self.variant(PG_DRV_A::L2)
83    }
84    #[doc = "`11`"]
85    #[inline(always)]
86    pub fn l3(self) -> &'a mut crate::W<REG> {
87        self.variant(PG_DRV_A::L3)
88    }
89}
90impl R {
91    #[doc = "PG Multi_Driving Select\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `pg8_drv` field"]
92    #[inline(always)]
93    pub fn pg_drv(&self, n: u8) -> PG_DRV_R {
94        #[allow(clippy::no_effect)]
95        [(); 8][n as usize];
96        PG_DRV_R::new(((self.bits >> (n * 4)) & 3) as u8)
97    }
98    #[doc = "Bits 0:1 - PG Multi_Driving Select"]
99    #[inline(always)]
100    pub fn pg8_drv(&self) -> PG_DRV_R {
101        PG_DRV_R::new((self.bits & 3) as u8)
102    }
103    #[doc = "Bits 4:5 - PG Multi_Driving Select"]
104    #[inline(always)]
105    pub fn pg9_drv(&self) -> PG_DRV_R {
106        PG_DRV_R::new(((self.bits >> 4) & 3) as u8)
107    }
108    #[doc = "Bits 8:9 - PG Multi_Driving Select"]
109    #[inline(always)]
110    pub fn pg10_drv(&self) -> PG_DRV_R {
111        PG_DRV_R::new(((self.bits >> 8) & 3) as u8)
112    }
113    #[doc = "Bits 12:13 - PG Multi_Driving Select"]
114    #[inline(always)]
115    pub fn pg11_drv(&self) -> PG_DRV_R {
116        PG_DRV_R::new(((self.bits >> 12) & 3) as u8)
117    }
118    #[doc = "Bits 16:17 - PG Multi_Driving Select"]
119    #[inline(always)]
120    pub fn pg12_drv(&self) -> PG_DRV_R {
121        PG_DRV_R::new(((self.bits >> 16) & 3) as u8)
122    }
123    #[doc = "Bits 20:21 - PG Multi_Driving Select"]
124    #[inline(always)]
125    pub fn pg13_drv(&self) -> PG_DRV_R {
126        PG_DRV_R::new(((self.bits >> 20) & 3) as u8)
127    }
128    #[doc = "Bits 24:25 - PG Multi_Driving Select"]
129    #[inline(always)]
130    pub fn pg14_drv(&self) -> PG_DRV_R {
131        PG_DRV_R::new(((self.bits >> 24) & 3) as u8)
132    }
133    #[doc = "Bits 28:29 - PG Multi_Driving Select"]
134    #[inline(always)]
135    pub fn pg15_drv(&self) -> PG_DRV_R {
136        PG_DRV_R::new(((self.bits >> 28) & 3) as u8)
137    }
138}
139impl W {
140    #[doc = "PG Multi_Driving Select\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `pg8_drv` field"]
141    #[inline(always)]
142    #[must_use]
143    pub fn pg_drv(&mut self, n: u8) -> PG_DRV_W<PG_DRV1_SPEC> {
144        #[allow(clippy::no_effect)]
145        [(); 8][n as usize];
146        PG_DRV_W::new(self, n * 4)
147    }
148    #[doc = "Bits 0:1 - PG Multi_Driving Select"]
149    #[inline(always)]
150    #[must_use]
151    pub fn pg8_drv(&mut self) -> PG_DRV_W<PG_DRV1_SPEC> {
152        PG_DRV_W::new(self, 0)
153    }
154    #[doc = "Bits 4:5 - PG Multi_Driving Select"]
155    #[inline(always)]
156    #[must_use]
157    pub fn pg9_drv(&mut self) -> PG_DRV_W<PG_DRV1_SPEC> {
158        PG_DRV_W::new(self, 4)
159    }
160    #[doc = "Bits 8:9 - PG Multi_Driving Select"]
161    #[inline(always)]
162    #[must_use]
163    pub fn pg10_drv(&mut self) -> PG_DRV_W<PG_DRV1_SPEC> {
164        PG_DRV_W::new(self, 8)
165    }
166    #[doc = "Bits 12:13 - PG Multi_Driving Select"]
167    #[inline(always)]
168    #[must_use]
169    pub fn pg11_drv(&mut self) -> PG_DRV_W<PG_DRV1_SPEC> {
170        PG_DRV_W::new(self, 12)
171    }
172    #[doc = "Bits 16:17 - PG Multi_Driving Select"]
173    #[inline(always)]
174    #[must_use]
175    pub fn pg12_drv(&mut self) -> PG_DRV_W<PG_DRV1_SPEC> {
176        PG_DRV_W::new(self, 16)
177    }
178    #[doc = "Bits 20:21 - PG Multi_Driving Select"]
179    #[inline(always)]
180    #[must_use]
181    pub fn pg13_drv(&mut self) -> PG_DRV_W<PG_DRV1_SPEC> {
182        PG_DRV_W::new(self, 20)
183    }
184    #[doc = "Bits 24:25 - PG Multi_Driving Select"]
185    #[inline(always)]
186    #[must_use]
187    pub fn pg14_drv(&mut self) -> PG_DRV_W<PG_DRV1_SPEC> {
188        PG_DRV_W::new(self, 24)
189    }
190    #[doc = "Bits 28:29 - PG Multi_Driving Select"]
191    #[inline(always)]
192    #[must_use]
193    pub fn pg15_drv(&mut self) -> PG_DRV_W<PG_DRV1_SPEC> {
194        PG_DRV_W::new(self, 28)
195    }
196    #[doc = r" Writes raw bits to the register."]
197    #[doc = r""]
198    #[doc = r" # Safety"]
199    #[doc = r""]
200    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
201    #[inline(always)]
202    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
203        self.bits = bits;
204        self
205    }
206}
207#[doc = "PG Multi_Driving Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pg_drv1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pg_drv1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
208pub struct PG_DRV1_SPEC;
209impl crate::RegisterSpec for PG_DRV1_SPEC {
210    type Ux = u32;
211}
212#[doc = "`read()` method returns [`pg_drv1::R`](R) reader structure"]
213impl crate::Readable for PG_DRV1_SPEC {}
214#[doc = "`write(|w| ..)` method takes [`pg_drv1::W`](W) writer structure"]
215impl crate::Writable for PG_DRV1_SPEC {
216    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
217    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
218}
219#[doc = "`reset()` method sets pg_drv1 to value 0"]
220impl crate::Resettable for PG_DRV1_SPEC {
221    const RESET_VALUE: Self::Ux = 0;
222}
d1_pac/gpio/pg_drv1.rs

d1_pac/gpio/
pg_drv1.rs
