d1_pac/gpio/
pc_cfg0.rs

1#[doc = "Register `pc_cfg0` reader"]
2pub type R = crate::R<PC_CFG0_SPEC>;
3#[doc = "Register `pc_cfg0` writer"]
4pub type W = crate::W<PC_CFG0_SPEC>;
5#[doc = "Field `pc0_select` reader - PC0 Select"]
6pub type PC0_SELECT_R = crate::FieldReader<PC0_SELECT_A>;
7#[doc = "PC0 Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum PC0_SELECT_A {
11    #[doc = "0: `0`"]
12    INPUT = 0,
13    #[doc = "2: `10`"]
14    UART2_TX = 2,
15    #[doc = "4: `100`"]
16    LEDC_DO = 4,
17    #[doc = "14: `1110`"]
18    PC_EINT0 = 14,
19    #[doc = "1: `1`"]
20    OUTPUT = 1,
21    #[doc = "3: `11`"]
22    TWI2_SCK = 3,
23    #[doc = "15: `1111`"]
24    IO_DISABLE = 15,
25}
26impl From<PC0_SELECT_A> for u8 {
27    #[inline(always)]
28    fn from(variant: PC0_SELECT_A) -> Self {
29        variant as _
30    }
31}
32impl crate::FieldSpec for PC0_SELECT_A {
33    type Ux = u8;
34}
35impl PC0_SELECT_R {
36    #[doc = "Get enumerated values variant"]
37    #[inline(always)]
38    pub const fn variant(&self) -> Option<PC0_SELECT_A> {
39        match self.bits {
40            0 => Some(PC0_SELECT_A::INPUT),
41            2 => Some(PC0_SELECT_A::UART2_TX),
42            4 => Some(PC0_SELECT_A::LEDC_DO),
43            14 => Some(PC0_SELECT_A::PC_EINT0),
44            1 => Some(PC0_SELECT_A::OUTPUT),
45            3 => Some(PC0_SELECT_A::TWI2_SCK),
46            15 => Some(PC0_SELECT_A::IO_DISABLE),
47            _ => None,
48        }
49    }
50    #[doc = "`0`"]
51    #[inline(always)]
52    pub fn is_input(&self) -> bool {
53        *self == PC0_SELECT_A::INPUT
54    }
55    #[doc = "`10`"]
56    #[inline(always)]
57    pub fn is_uart2_tx(&self) -> bool {
58        *self == PC0_SELECT_A::UART2_TX
59    }
60    #[doc = "`100`"]
61    #[inline(always)]
62    pub fn is_ledc_do(&self) -> bool {
63        *self == PC0_SELECT_A::LEDC_DO
64    }
65    #[doc = "`1110`"]
66    #[inline(always)]
67    pub fn is_pc_eint0(&self) -> bool {
68        *self == PC0_SELECT_A::PC_EINT0
69    }
70    #[doc = "`1`"]
71    #[inline(always)]
72    pub fn is_output(&self) -> bool {
73        *self == PC0_SELECT_A::OUTPUT
74    }
75    #[doc = "`11`"]
76    #[inline(always)]
77    pub fn is_twi2_sck(&self) -> bool {
78        *self == PC0_SELECT_A::TWI2_SCK
79    }
80    #[doc = "`1111`"]
81    #[inline(always)]
82    pub fn is_io_disable(&self) -> bool {
83        *self == PC0_SELECT_A::IO_DISABLE
84    }
85}
86#[doc = "Field `pc0_select` writer - PC0 Select"]
87pub type PC0_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PC0_SELECT_A>;
88impl<'a, REG> PC0_SELECT_W<'a, REG>
89where
90    REG: crate::Writable + crate::RegisterSpec,
91    REG::Ux: From<u8>,
92{
93    #[doc = "`0`"]
94    #[inline(always)]
95    pub fn input(self) -> &'a mut crate::W<REG> {
96        self.variant(PC0_SELECT_A::INPUT)
97    }
98    #[doc = "`10`"]
99    #[inline(always)]
100    pub fn uart2_tx(self) -> &'a mut crate::W<REG> {
101        self.variant(PC0_SELECT_A::UART2_TX)
102    }
103    #[doc = "`100`"]
104    #[inline(always)]
105    pub fn ledc_do(self) -> &'a mut crate::W<REG> {
106        self.variant(PC0_SELECT_A::LEDC_DO)
107    }
108    #[doc = "`1110`"]
109    #[inline(always)]
110    pub fn pc_eint0(self) -> &'a mut crate::W<REG> {
111        self.variant(PC0_SELECT_A::PC_EINT0)
112    }
113    #[doc = "`1`"]
114    #[inline(always)]
115    pub fn output(self) -> &'a mut crate::W<REG> {
116        self.variant(PC0_SELECT_A::OUTPUT)
117    }
118    #[doc = "`11`"]
119    #[inline(always)]
120    pub fn twi2_sck(self) -> &'a mut crate::W<REG> {
121        self.variant(PC0_SELECT_A::TWI2_SCK)
122    }
123    #[doc = "`1111`"]
124    #[inline(always)]
125    pub fn io_disable(self) -> &'a mut crate::W<REG> {
126        self.variant(PC0_SELECT_A::IO_DISABLE)
127    }
128}
129#[doc = "Field `pc1_select` reader - PC1 Select."]
130pub type PC1_SELECT_R = crate::FieldReader<PC1_SELECT_A>;
131#[doc = "PC1 Select.\n\nValue on reset: 0"]
132#[derive(Clone, Copy, Debug, PartialEq, Eq)]
133#[repr(u8)]
134pub enum PC1_SELECT_A {
135    #[doc = "0: `0`"]
136    INPUT = 0,
137    #[doc = "2: `10`"]
138    UART2_RX = 2,
139    #[doc = "14: `1110`"]
140    PC_EINT1 = 14,
141    #[doc = "1: `1`"]
142    OUTPUT = 1,
143    #[doc = "3: `11`"]
144    TWI2_SDA = 3,
145    #[doc = "15: `1111`"]
146    IO_DISABLE = 15,
147}
148impl From<PC1_SELECT_A> for u8 {
149    #[inline(always)]
150    fn from(variant: PC1_SELECT_A) -> Self {
151        variant as _
152    }
153}
154impl crate::FieldSpec for PC1_SELECT_A {
155    type Ux = u8;
156}
157impl PC1_SELECT_R {
158    #[doc = "Get enumerated values variant"]
159    #[inline(always)]
160    pub const fn variant(&self) -> Option<PC1_SELECT_A> {
161        match self.bits {
162            0 => Some(PC1_SELECT_A::INPUT),
163            2 => Some(PC1_SELECT_A::UART2_RX),
164            14 => Some(PC1_SELECT_A::PC_EINT1),
165            1 => Some(PC1_SELECT_A::OUTPUT),
166            3 => Some(PC1_SELECT_A::TWI2_SDA),
167            15 => Some(PC1_SELECT_A::IO_DISABLE),
168            _ => None,
169        }
170    }
171    #[doc = "`0`"]
172    #[inline(always)]
173    pub fn is_input(&self) -> bool {
174        *self == PC1_SELECT_A::INPUT
175    }
176    #[doc = "`10`"]
177    #[inline(always)]
178    pub fn is_uart2_rx(&self) -> bool {
179        *self == PC1_SELECT_A::UART2_RX
180    }
181    #[doc = "`1110`"]
182    #[inline(always)]
183    pub fn is_pc_eint1(&self) -> bool {
184        *self == PC1_SELECT_A::PC_EINT1
185    }
186    #[doc = "`1`"]
187    #[inline(always)]
188    pub fn is_output(&self) -> bool {
189        *self == PC1_SELECT_A::OUTPUT
190    }
191    #[doc = "`11`"]
192    #[inline(always)]
193    pub fn is_twi2_sda(&self) -> bool {
194        *self == PC1_SELECT_A::TWI2_SDA
195    }
196    #[doc = "`1111`"]
197    #[inline(always)]
198    pub fn is_io_disable(&self) -> bool {
199        *self == PC1_SELECT_A::IO_DISABLE
200    }
201}
202#[doc = "Field `pc1_select` writer - PC1 Select."]
203pub type PC1_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PC1_SELECT_A>;
204impl<'a, REG> PC1_SELECT_W<'a, REG>
205where
206    REG: crate::Writable + crate::RegisterSpec,
207    REG::Ux: From<u8>,
208{
209    #[doc = "`0`"]
210    #[inline(always)]
211    pub fn input(self) -> &'a mut crate::W<REG> {
212        self.variant(PC1_SELECT_A::INPUT)
213    }
214    #[doc = "`10`"]
215    #[inline(always)]
216    pub fn uart2_rx(self) -> &'a mut crate::W<REG> {
217        self.variant(PC1_SELECT_A::UART2_RX)
218    }
219    #[doc = "`1110`"]
220    #[inline(always)]
221    pub fn pc_eint1(self) -> &'a mut crate::W<REG> {
222        self.variant(PC1_SELECT_A::PC_EINT1)
223    }
224    #[doc = "`1`"]
225    #[inline(always)]
226    pub fn output(self) -> &'a mut crate::W<REG> {
227        self.variant(PC1_SELECT_A::OUTPUT)
228    }
229    #[doc = "`11`"]
230    #[inline(always)]
231    pub fn twi2_sda(self) -> &'a mut crate::W<REG> {
232        self.variant(PC1_SELECT_A::TWI2_SDA)
233    }
234    #[doc = "`1111`"]
235    #[inline(always)]
236    pub fn io_disable(self) -> &'a mut crate::W<REG> {
237        self.variant(PC1_SELECT_A::IO_DISABLE)
238    }
239}
240#[doc = "Field `pc2_select` reader - PC2 Select"]
241pub type PC2_SELECT_R = crate::FieldReader<PC2_SELECT_A>;
242#[doc = "PC2 Select\n\nValue on reset: 0"]
243#[derive(Clone, Copy, Debug, PartialEq, Eq)]
244#[repr(u8)]
245pub enum PC2_SELECT_A {
246    #[doc = "0: `0`"]
247    INPUT = 0,
248    #[doc = "2: `10`"]
249    SPI0_CLK = 2,
250    #[doc = "14: `1110`"]
251    PC_EINT2 = 14,
252    #[doc = "1: `1`"]
253    OUTPUT = 1,
254    #[doc = "3: `11`"]
255    SDC2_CLK = 3,
256    #[doc = "15: `1111`"]
257    IO_DISABLE = 15,
258}
259impl From<PC2_SELECT_A> for u8 {
260    #[inline(always)]
261    fn from(variant: PC2_SELECT_A) -> Self {
262        variant as _
263    }
264}
265impl crate::FieldSpec for PC2_SELECT_A {
266    type Ux = u8;
267}
268impl PC2_SELECT_R {
269    #[doc = "Get enumerated values variant"]
270    #[inline(always)]
271    pub const fn variant(&self) -> Option<PC2_SELECT_A> {
272        match self.bits {
273            0 => Some(PC2_SELECT_A::INPUT),
274            2 => Some(PC2_SELECT_A::SPI0_CLK),
275            14 => Some(PC2_SELECT_A::PC_EINT2),
276            1 => Some(PC2_SELECT_A::OUTPUT),
277            3 => Some(PC2_SELECT_A::SDC2_CLK),
278            15 => Some(PC2_SELECT_A::IO_DISABLE),
279            _ => None,
280        }
281    }
282    #[doc = "`0`"]
283    #[inline(always)]
284    pub fn is_input(&self) -> bool {
285        *self == PC2_SELECT_A::INPUT
286    }
287    #[doc = "`10`"]
288    #[inline(always)]
289    pub fn is_spi0_clk(&self) -> bool {
290        *self == PC2_SELECT_A::SPI0_CLK
291    }
292    #[doc = "`1110`"]
293    #[inline(always)]
294    pub fn is_pc_eint2(&self) -> bool {
295        *self == PC2_SELECT_A::PC_EINT2
296    }
297    #[doc = "`1`"]
298    #[inline(always)]
299    pub fn is_output(&self) -> bool {
300        *self == PC2_SELECT_A::OUTPUT
301    }
302    #[doc = "`11`"]
303    #[inline(always)]
304    pub fn is_sdc2_clk(&self) -> bool {
305        *self == PC2_SELECT_A::SDC2_CLK
306    }
307    #[doc = "`1111`"]
308    #[inline(always)]
309    pub fn is_io_disable(&self) -> bool {
310        *self == PC2_SELECT_A::IO_DISABLE
311    }
312}
313#[doc = "Field `pc2_select` writer - PC2 Select"]
314pub type PC2_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PC2_SELECT_A>;
315impl<'a, REG> PC2_SELECT_W<'a, REG>
316where
317    REG: crate::Writable + crate::RegisterSpec,
318    REG::Ux: From<u8>,
319{
320    #[doc = "`0`"]
321    #[inline(always)]
322    pub fn input(self) -> &'a mut crate::W<REG> {
323        self.variant(PC2_SELECT_A::INPUT)
324    }
325    #[doc = "`10`"]
326    #[inline(always)]
327    pub fn spi0_clk(self) -> &'a mut crate::W<REG> {
328        self.variant(PC2_SELECT_A::SPI0_CLK)
329    }
330    #[doc = "`1110`"]
331    #[inline(always)]
332    pub fn pc_eint2(self) -> &'a mut crate::W<REG> {
333        self.variant(PC2_SELECT_A::PC_EINT2)
334    }
335    #[doc = "`1`"]
336    #[inline(always)]
337    pub fn output(self) -> &'a mut crate::W<REG> {
338        self.variant(PC2_SELECT_A::OUTPUT)
339    }
340    #[doc = "`11`"]
341    #[inline(always)]
342    pub fn sdc2_clk(self) -> &'a mut crate::W<REG> {
343        self.variant(PC2_SELECT_A::SDC2_CLK)
344    }
345    #[doc = "`1111`"]
346    #[inline(always)]
347    pub fn io_disable(self) -> &'a mut crate::W<REG> {
348        self.variant(PC2_SELECT_A::IO_DISABLE)
349    }
350}
351#[doc = "Field `pc3_select` reader - PC3 Select"]
352pub type PC3_SELECT_R = crate::FieldReader<PC3_SELECT_A>;
353#[doc = "PC3 Select\n\nValue on reset: 0"]
354#[derive(Clone, Copy, Debug, PartialEq, Eq)]
355#[repr(u8)]
356pub enum PC3_SELECT_A {
357    #[doc = "0: `0`"]
358    INPUT = 0,
359    #[doc = "2: `10`"]
360    SPI0_CS0 = 2,
361    #[doc = "14: `1110`"]
362    PC_EINT3 = 14,
363    #[doc = "1: `1`"]
364    OUTPUT = 1,
365    #[doc = "3: `11`"]
366    SDC2_CMD = 3,
367    #[doc = "15: `1111`"]
368    IO_DISABLE = 15,
369}
370impl From<PC3_SELECT_A> for u8 {
371    #[inline(always)]
372    fn from(variant: PC3_SELECT_A) -> Self {
373        variant as _
374    }
375}
376impl crate::FieldSpec for PC3_SELECT_A {
377    type Ux = u8;
378}
379impl PC3_SELECT_R {
380    #[doc = "Get enumerated values variant"]
381    #[inline(always)]
382    pub const fn variant(&self) -> Option<PC3_SELECT_A> {
383        match self.bits {
384            0 => Some(PC3_SELECT_A::INPUT),
385            2 => Some(PC3_SELECT_A::SPI0_CS0),
386            14 => Some(PC3_SELECT_A::PC_EINT3),
387            1 => Some(PC3_SELECT_A::OUTPUT),
388            3 => Some(PC3_SELECT_A::SDC2_CMD),
389            15 => Some(PC3_SELECT_A::IO_DISABLE),
390            _ => None,
391        }
392    }
393    #[doc = "`0`"]
394    #[inline(always)]
395    pub fn is_input(&self) -> bool {
396        *self == PC3_SELECT_A::INPUT
397    }
398    #[doc = "`10`"]
399    #[inline(always)]
400    pub fn is_spi0_cs0(&self) -> bool {
401        *self == PC3_SELECT_A::SPI0_CS0
402    }
403    #[doc = "`1110`"]
404    #[inline(always)]
405    pub fn is_pc_eint3(&self) -> bool {
406        *self == PC3_SELECT_A::PC_EINT3
407    }
408    #[doc = "`1`"]
409    #[inline(always)]
410    pub fn is_output(&self) -> bool {
411        *self == PC3_SELECT_A::OUTPUT
412    }
413    #[doc = "`11`"]
414    #[inline(always)]
415    pub fn is_sdc2_cmd(&self) -> bool {
416        *self == PC3_SELECT_A::SDC2_CMD
417    }
418    #[doc = "`1111`"]
419    #[inline(always)]
420    pub fn is_io_disable(&self) -> bool {
421        *self == PC3_SELECT_A::IO_DISABLE
422    }
423}
424#[doc = "Field `pc3_select` writer - PC3 Select"]
425pub type PC3_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PC3_SELECT_A>;
426impl<'a, REG> PC3_SELECT_W<'a, REG>
427where
428    REG: crate::Writable + crate::RegisterSpec,
429    REG::Ux: From<u8>,
430{
431    #[doc = "`0`"]
432    #[inline(always)]
433    pub fn input(self) -> &'a mut crate::W<REG> {
434        self.variant(PC3_SELECT_A::INPUT)
435    }
436    #[doc = "`10`"]
437    #[inline(always)]
438    pub fn spi0_cs0(self) -> &'a mut crate::W<REG> {
439        self.variant(PC3_SELECT_A::SPI0_CS0)
440    }
441    #[doc = "`1110`"]
442    #[inline(always)]
443    pub fn pc_eint3(self) -> &'a mut crate::W<REG> {
444        self.variant(PC3_SELECT_A::PC_EINT3)
445    }
446    #[doc = "`1`"]
447    #[inline(always)]
448    pub fn output(self) -> &'a mut crate::W<REG> {
449        self.variant(PC3_SELECT_A::OUTPUT)
450    }
451    #[doc = "`11`"]
452    #[inline(always)]
453    pub fn sdc2_cmd(self) -> &'a mut crate::W<REG> {
454        self.variant(PC3_SELECT_A::SDC2_CMD)
455    }
456    #[doc = "`1111`"]
457    #[inline(always)]
458    pub fn io_disable(self) -> &'a mut crate::W<REG> {
459        self.variant(PC3_SELECT_A::IO_DISABLE)
460    }
461}
462#[doc = "Field `pc4_select` reader - PC4 Select"]
463pub type PC4_SELECT_R = crate::FieldReader<PC4_SELECT_A>;
464#[doc = "PC4 Select\n\nValue on reset: 0"]
465#[derive(Clone, Copy, Debug, PartialEq, Eq)]
466#[repr(u8)]
467pub enum PC4_SELECT_A {
468    #[doc = "0: `0`"]
469    INPUT = 0,
470    #[doc = "2: `10`"]
471    SPI0_MOSI = 2,
472    #[doc = "4: `100`"]
473    BOOT_SEL0 = 4,
474    #[doc = "14: `1110`"]
475    PC_EINT4 = 14,
476    #[doc = "1: `1`"]
477    OUTPUT = 1,
478    #[doc = "3: `11`"]
479    SDC2_D2 = 3,
480    #[doc = "15: `1111`"]
481    IO_DISABLE = 15,
482}
483impl From<PC4_SELECT_A> for u8 {
484    #[inline(always)]
485    fn from(variant: PC4_SELECT_A) -> Self {
486        variant as _
487    }
488}
489impl crate::FieldSpec for PC4_SELECT_A {
490    type Ux = u8;
491}
492impl PC4_SELECT_R {
493    #[doc = "Get enumerated values variant"]
494    #[inline(always)]
495    pub const fn variant(&self) -> Option<PC4_SELECT_A> {
496        match self.bits {
497            0 => Some(PC4_SELECT_A::INPUT),
498            2 => Some(PC4_SELECT_A::SPI0_MOSI),
499            4 => Some(PC4_SELECT_A::BOOT_SEL0),
500            14 => Some(PC4_SELECT_A::PC_EINT4),
501            1 => Some(PC4_SELECT_A::OUTPUT),
502            3 => Some(PC4_SELECT_A::SDC2_D2),
503            15 => Some(PC4_SELECT_A::IO_DISABLE),
504            _ => None,
505        }
506    }
507    #[doc = "`0`"]
508    #[inline(always)]
509    pub fn is_input(&self) -> bool {
510        *self == PC4_SELECT_A::INPUT
511    }
512    #[doc = "`10`"]
513    #[inline(always)]
514    pub fn is_spi0_mosi(&self) -> bool {
515        *self == PC4_SELECT_A::SPI0_MOSI
516    }
517    #[doc = "`100`"]
518    #[inline(always)]
519    pub fn is_boot_sel0(&self) -> bool {
520        *self == PC4_SELECT_A::BOOT_SEL0
521    }
522    #[doc = "`1110`"]
523    #[inline(always)]
524    pub fn is_pc_eint4(&self) -> bool {
525        *self == PC4_SELECT_A::PC_EINT4
526    }
527    #[doc = "`1`"]
528    #[inline(always)]
529    pub fn is_output(&self) -> bool {
530        *self == PC4_SELECT_A::OUTPUT
531    }
532    #[doc = "`11`"]
533    #[inline(always)]
534    pub fn is_sdc2_d2(&self) -> bool {
535        *self == PC4_SELECT_A::SDC2_D2
536    }
537    #[doc = "`1111`"]
538    #[inline(always)]
539    pub fn is_io_disable(&self) -> bool {
540        *self == PC4_SELECT_A::IO_DISABLE
541    }
542}
543#[doc = "Field `pc4_select` writer - PC4 Select"]
544pub type PC4_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PC4_SELECT_A>;
545impl<'a, REG> PC4_SELECT_W<'a, REG>
546where
547    REG: crate::Writable + crate::RegisterSpec,
548    REG::Ux: From<u8>,
549{
550    #[doc = "`0`"]
551    #[inline(always)]
552    pub fn input(self) -> &'a mut crate::W<REG> {
553        self.variant(PC4_SELECT_A::INPUT)
554    }
555    #[doc = "`10`"]
556    #[inline(always)]
557    pub fn spi0_mosi(self) -> &'a mut crate::W<REG> {
558        self.variant(PC4_SELECT_A::SPI0_MOSI)
559    }
560    #[doc = "`100`"]
561    #[inline(always)]
562    pub fn boot_sel0(self) -> &'a mut crate::W<REG> {
563        self.variant(PC4_SELECT_A::BOOT_SEL0)
564    }
565    #[doc = "`1110`"]
566    #[inline(always)]
567    pub fn pc_eint4(self) -> &'a mut crate::W<REG> {
568        self.variant(PC4_SELECT_A::PC_EINT4)
569    }
570    #[doc = "`1`"]
571    #[inline(always)]
572    pub fn output(self) -> &'a mut crate::W<REG> {
573        self.variant(PC4_SELECT_A::OUTPUT)
574    }
575    #[doc = "`11`"]
576    #[inline(always)]
577    pub fn sdc2_d2(self) -> &'a mut crate::W<REG> {
578        self.variant(PC4_SELECT_A::SDC2_D2)
579    }
580    #[doc = "`1111`"]
581    #[inline(always)]
582    pub fn io_disable(self) -> &'a mut crate::W<REG> {
583        self.variant(PC4_SELECT_A::IO_DISABLE)
584    }
585}
586#[doc = "Field `pc5_select` reader - PC5 Select"]
587pub type PC5_SELECT_R = crate::FieldReader<PC5_SELECT_A>;
588#[doc = "PC5 Select\n\nValue on reset: 0"]
589#[derive(Clone, Copy, Debug, PartialEq, Eq)]
590#[repr(u8)]
591pub enum PC5_SELECT_A {
592    #[doc = "0: `0`"]
593    INPUT = 0,
594    #[doc = "2: `10`"]
595    SPI0_MISO = 2,
596    #[doc = "4: `100`"]
597    BOOT_SEL1 = 4,
598    #[doc = "14: `1110`"]
599    PC_EINT5 = 14,
600    #[doc = "1: `1`"]
601    OUTPUT = 1,
602    #[doc = "3: `11`"]
603    SDC2_D1 = 3,
604    #[doc = "15: `1111`"]
605    IO_DISABLE = 15,
606}
607impl From<PC5_SELECT_A> for u8 {
608    #[inline(always)]
609    fn from(variant: PC5_SELECT_A) -> Self {
610        variant as _
611    }
612}
613impl crate::FieldSpec for PC5_SELECT_A {
614    type Ux = u8;
615}
616impl PC5_SELECT_R {
617    #[doc = "Get enumerated values variant"]
618    #[inline(always)]
619    pub const fn variant(&self) -> Option<PC5_SELECT_A> {
620        match self.bits {
621            0 => Some(PC5_SELECT_A::INPUT),
622            2 => Some(PC5_SELECT_A::SPI0_MISO),
623            4 => Some(PC5_SELECT_A::BOOT_SEL1),
624            14 => Some(PC5_SELECT_A::PC_EINT5),
625            1 => Some(PC5_SELECT_A::OUTPUT),
626            3 => Some(PC5_SELECT_A::SDC2_D1),
627            15 => Some(PC5_SELECT_A::IO_DISABLE),
628            _ => None,
629        }
630    }
631    #[doc = "`0`"]
632    #[inline(always)]
633    pub fn is_input(&self) -> bool {
634        *self == PC5_SELECT_A::INPUT
635    }
636    #[doc = "`10`"]
637    #[inline(always)]
638    pub fn is_spi0_miso(&self) -> bool {
639        *self == PC5_SELECT_A::SPI0_MISO
640    }
641    #[doc = "`100`"]
642    #[inline(always)]
643    pub fn is_boot_sel1(&self) -> bool {
644        *self == PC5_SELECT_A::BOOT_SEL1
645    }
646    #[doc = "`1110`"]
647    #[inline(always)]
648    pub fn is_pc_eint5(&self) -> bool {
649        *self == PC5_SELECT_A::PC_EINT5
650    }
651    #[doc = "`1`"]
652    #[inline(always)]
653    pub fn is_output(&self) -> bool {
654        *self == PC5_SELECT_A::OUTPUT
655    }
656    #[doc = "`11`"]
657    #[inline(always)]
658    pub fn is_sdc2_d1(&self) -> bool {
659        *self == PC5_SELECT_A::SDC2_D1
660    }
661    #[doc = "`1111`"]
662    #[inline(always)]
663    pub fn is_io_disable(&self) -> bool {
664        *self == PC5_SELECT_A::IO_DISABLE
665    }
666}
667#[doc = "Field `pc5_select` writer - PC5 Select"]
668pub type PC5_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PC5_SELECT_A>;
669impl<'a, REG> PC5_SELECT_W<'a, REG>
670where
671    REG: crate::Writable + crate::RegisterSpec,
672    REG::Ux: From<u8>,
673{
674    #[doc = "`0`"]
675    #[inline(always)]
676    pub fn input(self) -> &'a mut crate::W<REG> {
677        self.variant(PC5_SELECT_A::INPUT)
678    }
679    #[doc = "`10`"]
680    #[inline(always)]
681    pub fn spi0_miso(self) -> &'a mut crate::W<REG> {
682        self.variant(PC5_SELECT_A::SPI0_MISO)
683    }
684    #[doc = "`100`"]
685    #[inline(always)]
686    pub fn boot_sel1(self) -> &'a mut crate::W<REG> {
687        self.variant(PC5_SELECT_A::BOOT_SEL1)
688    }
689    #[doc = "`1110`"]
690    #[inline(always)]
691    pub fn pc_eint5(self) -> &'a mut crate::W<REG> {
692        self.variant(PC5_SELECT_A::PC_EINT5)
693    }
694    #[doc = "`1`"]
695    #[inline(always)]
696    pub fn output(self) -> &'a mut crate::W<REG> {
697        self.variant(PC5_SELECT_A::OUTPUT)
698    }
699    #[doc = "`11`"]
700    #[inline(always)]
701    pub fn sdc2_d1(self) -> &'a mut crate::W<REG> {
702        self.variant(PC5_SELECT_A::SDC2_D1)
703    }
704    #[doc = "`1111`"]
705    #[inline(always)]
706    pub fn io_disable(self) -> &'a mut crate::W<REG> {
707        self.variant(PC5_SELECT_A::IO_DISABLE)
708    }
709}
710#[doc = "Field `pc6_select` reader - PC6 Select"]
711pub type PC6_SELECT_R = crate::FieldReader<PC6_SELECT_A>;
712#[doc = "PC6 Select\n\nValue on reset: 0"]
713#[derive(Clone, Copy, Debug, PartialEq, Eq)]
714#[repr(u8)]
715pub enum PC6_SELECT_A {
716    #[doc = "0: `0`"]
717    INPUT = 0,
718    #[doc = "2: `10`"]
719    SPI0_WP = 2,
720    #[doc = "4: `100`"]
721    UART3_TX = 4,
722    #[doc = "6: `110`"]
723    DBG_CLK = 6,
724    #[doc = "14: `1110`"]
725    PC_EINT6 = 14,
726    #[doc = "1: `1`"]
727    OUTPUT = 1,
728    #[doc = "3: `11`"]
729    SDC2_D0 = 3,
730    #[doc = "5: `101`"]
731    TWI3_SCK = 5,
732    #[doc = "15: `1111`"]
733    IO_DISABLE = 15,
734}
735impl From<PC6_SELECT_A> for u8 {
736    #[inline(always)]
737    fn from(variant: PC6_SELECT_A) -> Self {
738        variant as _
739    }
740}
741impl crate::FieldSpec for PC6_SELECT_A {
742    type Ux = u8;
743}
744impl PC6_SELECT_R {
745    #[doc = "Get enumerated values variant"]
746    #[inline(always)]
747    pub const fn variant(&self) -> Option<PC6_SELECT_A> {
748        match self.bits {
749            0 => Some(PC6_SELECT_A::INPUT),
750            2 => Some(PC6_SELECT_A::SPI0_WP),
751            4 => Some(PC6_SELECT_A::UART3_TX),
752            6 => Some(PC6_SELECT_A::DBG_CLK),
753            14 => Some(PC6_SELECT_A::PC_EINT6),
754            1 => Some(PC6_SELECT_A::OUTPUT),
755            3 => Some(PC6_SELECT_A::SDC2_D0),
756            5 => Some(PC6_SELECT_A::TWI3_SCK),
757            15 => Some(PC6_SELECT_A::IO_DISABLE),
758            _ => None,
759        }
760    }
761    #[doc = "`0`"]
762    #[inline(always)]
763    pub fn is_input(&self) -> bool {
764        *self == PC6_SELECT_A::INPUT
765    }
766    #[doc = "`10`"]
767    #[inline(always)]
768    pub fn is_spi0_wp(&self) -> bool {
769        *self == PC6_SELECT_A::SPI0_WP
770    }
771    #[doc = "`100`"]
772    #[inline(always)]
773    pub fn is_uart3_tx(&self) -> bool {
774        *self == PC6_SELECT_A::UART3_TX
775    }
776    #[doc = "`110`"]
777    #[inline(always)]
778    pub fn is_dbg_clk(&self) -> bool {
779        *self == PC6_SELECT_A::DBG_CLK
780    }
781    #[doc = "`1110`"]
782    #[inline(always)]
783    pub fn is_pc_eint6(&self) -> bool {
784        *self == PC6_SELECT_A::PC_EINT6
785    }
786    #[doc = "`1`"]
787    #[inline(always)]
788    pub fn is_output(&self) -> bool {
789        *self == PC6_SELECT_A::OUTPUT
790    }
791    #[doc = "`11`"]
792    #[inline(always)]
793    pub fn is_sdc2_d0(&self) -> bool {
794        *self == PC6_SELECT_A::SDC2_D0
795    }
796    #[doc = "`101`"]
797    #[inline(always)]
798    pub fn is_twi3_sck(&self) -> bool {
799        *self == PC6_SELECT_A::TWI3_SCK
800    }
801    #[doc = "`1111`"]
802    #[inline(always)]
803    pub fn is_io_disable(&self) -> bool {
804        *self == PC6_SELECT_A::IO_DISABLE
805    }
806}
807#[doc = "Field `pc6_select` writer - PC6 Select"]
808pub type PC6_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PC6_SELECT_A>;
809impl<'a, REG> PC6_SELECT_W<'a, REG>
810where
811    REG: crate::Writable + crate::RegisterSpec,
812    REG::Ux: From<u8>,
813{
814    #[doc = "`0`"]
815    #[inline(always)]
816    pub fn input(self) -> &'a mut crate::W<REG> {
817        self.variant(PC6_SELECT_A::INPUT)
818    }
819    #[doc = "`10`"]
820    #[inline(always)]
821    pub fn spi0_wp(self) -> &'a mut crate::W<REG> {
822        self.variant(PC6_SELECT_A::SPI0_WP)
823    }
824    #[doc = "`100`"]
825    #[inline(always)]
826    pub fn uart3_tx(self) -> &'a mut crate::W<REG> {
827        self.variant(PC6_SELECT_A::UART3_TX)
828    }
829    #[doc = "`110`"]
830    #[inline(always)]
831    pub fn dbg_clk(self) -> &'a mut crate::W<REG> {
832        self.variant(PC6_SELECT_A::DBG_CLK)
833    }
834    #[doc = "`1110`"]
835    #[inline(always)]
836    pub fn pc_eint6(self) -> &'a mut crate::W<REG> {
837        self.variant(PC6_SELECT_A::PC_EINT6)
838    }
839    #[doc = "`1`"]
840    #[inline(always)]
841    pub fn output(self) -> &'a mut crate::W<REG> {
842        self.variant(PC6_SELECT_A::OUTPUT)
843    }
844    #[doc = "`11`"]
845    #[inline(always)]
846    pub fn sdc2_d0(self) -> &'a mut crate::W<REG> {
847        self.variant(PC6_SELECT_A::SDC2_D0)
848    }
849    #[doc = "`101`"]
850    #[inline(always)]
851    pub fn twi3_sck(self) -> &'a mut crate::W<REG> {
852        self.variant(PC6_SELECT_A::TWI3_SCK)
853    }
854    #[doc = "`1111`"]
855    #[inline(always)]
856    pub fn io_disable(self) -> &'a mut crate::W<REG> {
857        self.variant(PC6_SELECT_A::IO_DISABLE)
858    }
859}
860#[doc = "Field `pc7_select` reader - PC7 Select"]
861pub type PC7_SELECT_R = crate::FieldReader<PC7_SELECT_A>;
862#[doc = "PC7 Select\n\nValue on reset: 0"]
863#[derive(Clone, Copy, Debug, PartialEq, Eq)]
864#[repr(u8)]
865pub enum PC7_SELECT_A {
866    #[doc = "0: `0`"]
867    INPUT = 0,
868    #[doc = "2: `10`"]
869    SPI0_HOLD = 2,
870    #[doc = "4: `100`"]
871    UART3_RX = 4,
872    #[doc = "6: `110`"]
873    TCON_TRIG = 6,
874    #[doc = "14: `1110`"]
875    PC_EINT7 = 14,
876    #[doc = "1: `1`"]
877    OUTPUT = 1,
878    #[doc = "3: `11`"]
879    SDC2_D3 = 3,
880    #[doc = "5: `101`"]
881    TWI3_SDA = 5,
882    #[doc = "15: `1111`"]
883    IO_DISABLE = 15,
884}
885impl From<PC7_SELECT_A> for u8 {
886    #[inline(always)]
887    fn from(variant: PC7_SELECT_A) -> Self {
888        variant as _
889    }
890}
891impl crate::FieldSpec for PC7_SELECT_A {
892    type Ux = u8;
893}
894impl PC7_SELECT_R {
895    #[doc = "Get enumerated values variant"]
896    #[inline(always)]
897    pub const fn variant(&self) -> Option<PC7_SELECT_A> {
898        match self.bits {
899            0 => Some(PC7_SELECT_A::INPUT),
900            2 => Some(PC7_SELECT_A::SPI0_HOLD),
901            4 => Some(PC7_SELECT_A::UART3_RX),
902            6 => Some(PC7_SELECT_A::TCON_TRIG),
903            14 => Some(PC7_SELECT_A::PC_EINT7),
904            1 => Some(PC7_SELECT_A::OUTPUT),
905            3 => Some(PC7_SELECT_A::SDC2_D3),
906            5 => Some(PC7_SELECT_A::TWI3_SDA),
907            15 => Some(PC7_SELECT_A::IO_DISABLE),
908            _ => None,
909        }
910    }
911    #[doc = "`0`"]
912    #[inline(always)]
913    pub fn is_input(&self) -> bool {
914        *self == PC7_SELECT_A::INPUT
915    }
916    #[doc = "`10`"]
917    #[inline(always)]
918    pub fn is_spi0_hold(&self) -> bool {
919        *self == PC7_SELECT_A::SPI0_HOLD
920    }
921    #[doc = "`100`"]
922    #[inline(always)]
923    pub fn is_uart3_rx(&self) -> bool {
924        *self == PC7_SELECT_A::UART3_RX
925    }
926    #[doc = "`110`"]
927    #[inline(always)]
928    pub fn is_tcon_trig(&self) -> bool {
929        *self == PC7_SELECT_A::TCON_TRIG
930    }
931    #[doc = "`1110`"]
932    #[inline(always)]
933    pub fn is_pc_eint7(&self) -> bool {
934        *self == PC7_SELECT_A::PC_EINT7
935    }
936    #[doc = "`1`"]
937    #[inline(always)]
938    pub fn is_output(&self) -> bool {
939        *self == PC7_SELECT_A::OUTPUT
940    }
941    #[doc = "`11`"]
942    #[inline(always)]
943    pub fn is_sdc2_d3(&self) -> bool {
944        *self == PC7_SELECT_A::SDC2_D3
945    }
946    #[doc = "`101`"]
947    #[inline(always)]
948    pub fn is_twi3_sda(&self) -> bool {
949        *self == PC7_SELECT_A::TWI3_SDA
950    }
951    #[doc = "`1111`"]
952    #[inline(always)]
953    pub fn is_io_disable(&self) -> bool {
954        *self == PC7_SELECT_A::IO_DISABLE
955    }
956}
957#[doc = "Field `pc7_select` writer - PC7 Select"]
958pub type PC7_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PC7_SELECT_A>;
959impl<'a, REG> PC7_SELECT_W<'a, REG>
960where
961    REG: crate::Writable + crate::RegisterSpec,
962    REG::Ux: From<u8>,
963{
964    #[doc = "`0`"]
965    #[inline(always)]
966    pub fn input(self) -> &'a mut crate::W<REG> {
967        self.variant(PC7_SELECT_A::INPUT)
968    }
969    #[doc = "`10`"]
970    #[inline(always)]
971    pub fn spi0_hold(self) -> &'a mut crate::W<REG> {
972        self.variant(PC7_SELECT_A::SPI0_HOLD)
973    }
974    #[doc = "`100`"]
975    #[inline(always)]
976    pub fn uart3_rx(self) -> &'a mut crate::W<REG> {
977        self.variant(PC7_SELECT_A::UART3_RX)
978    }
979    #[doc = "`110`"]
980    #[inline(always)]
981    pub fn tcon_trig(self) -> &'a mut crate::W<REG> {
982        self.variant(PC7_SELECT_A::TCON_TRIG)
983    }
984    #[doc = "`1110`"]
985    #[inline(always)]
986    pub fn pc_eint7(self) -> &'a mut crate::W<REG> {
987        self.variant(PC7_SELECT_A::PC_EINT7)
988    }
989    #[doc = "`1`"]
990    #[inline(always)]
991    pub fn output(self) -> &'a mut crate::W<REG> {
992        self.variant(PC7_SELECT_A::OUTPUT)
993    }
994    #[doc = "`11`"]
995    #[inline(always)]
996    pub fn sdc2_d3(self) -> &'a mut crate::W<REG> {
997        self.variant(PC7_SELECT_A::SDC2_D3)
998    }
999    #[doc = "`101`"]
1000    #[inline(always)]
1001    pub fn twi3_sda(self) -> &'a mut crate::W<REG> {
1002        self.variant(PC7_SELECT_A::TWI3_SDA)
1003    }
1004    #[doc = "`1111`"]
1005    #[inline(always)]
1006    pub fn io_disable(self) -> &'a mut crate::W<REG> {
1007        self.variant(PC7_SELECT_A::IO_DISABLE)
1008    }
1009}
1010impl R {
1011    #[doc = "Bits 0:3 - PC0 Select"]
1012    #[inline(always)]
1013    pub fn pc0_select(&self) -> PC0_SELECT_R {
1014        PC0_SELECT_R::new((self.bits & 0x0f) as u8)
1015    }
1016    #[doc = "Bits 4:7 - PC1 Select."]
1017    #[inline(always)]
1018    pub fn pc1_select(&self) -> PC1_SELECT_R {
1019        PC1_SELECT_R::new(((self.bits >> 4) & 0x0f) as u8)
1020    }
1021    #[doc = "Bits 8:11 - PC2 Select"]
1022    #[inline(always)]
1023    pub fn pc2_select(&self) -> PC2_SELECT_R {
1024        PC2_SELECT_R::new(((self.bits >> 8) & 0x0f) as u8)
1025    }
1026    #[doc = "Bits 12:15 - PC3 Select"]
1027    #[inline(always)]
1028    pub fn pc3_select(&self) -> PC3_SELECT_R {
1029        PC3_SELECT_R::new(((self.bits >> 12) & 0x0f) as u8)
1030    }
1031    #[doc = "Bits 16:19 - PC4 Select"]
1032    #[inline(always)]
1033    pub fn pc4_select(&self) -> PC4_SELECT_R {
1034        PC4_SELECT_R::new(((self.bits >> 16) & 0x0f) as u8)
1035    }
1036    #[doc = "Bits 20:23 - PC5 Select"]
1037    #[inline(always)]
1038    pub fn pc5_select(&self) -> PC5_SELECT_R {
1039        PC5_SELECT_R::new(((self.bits >> 20) & 0x0f) as u8)
1040    }
1041    #[doc = "Bits 24:27 - PC6 Select"]
1042    #[inline(always)]
1043    pub fn pc6_select(&self) -> PC6_SELECT_R {
1044        PC6_SELECT_R::new(((self.bits >> 24) & 0x0f) as u8)
1045    }
1046    #[doc = "Bits 28:31 - PC7 Select"]
1047    #[inline(always)]
1048    pub fn pc7_select(&self) -> PC7_SELECT_R {
1049        PC7_SELECT_R::new(((self.bits >> 28) & 0x0f) as u8)
1050    }
1051}
1052impl W {
1053    #[doc = "Bits 0:3 - PC0 Select"]
1054    #[inline(always)]
1055    #[must_use]
1056    pub fn pc0_select(&mut self) -> PC0_SELECT_W<PC_CFG0_SPEC> {
1057        PC0_SELECT_W::new(self, 0)
1058    }
1059    #[doc = "Bits 4:7 - PC1 Select."]
1060    #[inline(always)]
1061    #[must_use]
1062    pub fn pc1_select(&mut self) -> PC1_SELECT_W<PC_CFG0_SPEC> {
1063        PC1_SELECT_W::new(self, 4)
1064    }
1065    #[doc = "Bits 8:11 - PC2 Select"]
1066    #[inline(always)]
1067    #[must_use]
1068    pub fn pc2_select(&mut self) -> PC2_SELECT_W<PC_CFG0_SPEC> {
1069        PC2_SELECT_W::new(self, 8)
1070    }
1071    #[doc = "Bits 12:15 - PC3 Select"]
1072    #[inline(always)]
1073    #[must_use]
1074    pub fn pc3_select(&mut self) -> PC3_SELECT_W<PC_CFG0_SPEC> {
1075        PC3_SELECT_W::new(self, 12)
1076    }
1077    #[doc = "Bits 16:19 - PC4 Select"]
1078    #[inline(always)]
1079    #[must_use]
1080    pub fn pc4_select(&mut self) -> PC4_SELECT_W<PC_CFG0_SPEC> {
1081        PC4_SELECT_W::new(self, 16)
1082    }
1083    #[doc = "Bits 20:23 - PC5 Select"]
1084    #[inline(always)]
1085    #[must_use]
1086    pub fn pc5_select(&mut self) -> PC5_SELECT_W<PC_CFG0_SPEC> {
1087        PC5_SELECT_W::new(self, 20)
1088    }
1089    #[doc = "Bits 24:27 - PC6 Select"]
1090    #[inline(always)]
1091    #[must_use]
1092    pub fn pc6_select(&mut self) -> PC6_SELECT_W<PC_CFG0_SPEC> {
1093        PC6_SELECT_W::new(self, 24)
1094    }
1095    #[doc = "Bits 28:31 - PC7 Select"]
1096    #[inline(always)]
1097    #[must_use]
1098    pub fn pc7_select(&mut self) -> PC7_SELECT_W<PC_CFG0_SPEC> {
1099        PC7_SELECT_W::new(self, 28)
1100    }
1101    #[doc = r" Writes raw bits to the register."]
1102    #[doc = r""]
1103    #[doc = r" # Safety"]
1104    #[doc = r""]
1105    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
1106    #[inline(always)]
1107    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1108        self.bits = bits;
1109        self
1110    }
1111}
1112#[doc = "PC Configure Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pc_cfg0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pc_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1113pub struct PC_CFG0_SPEC;
1114impl crate::RegisterSpec for PC_CFG0_SPEC {
1115    type Ux = u32;
1116}
1117#[doc = "`read()` method returns [`pc_cfg0::R`](R) reader structure"]
1118impl crate::Readable for PC_CFG0_SPEC {}
1119#[doc = "`write(|w| ..)` method takes [`pc_cfg0::W`](W) writer structure"]
1120impl crate::Writable for PC_CFG0_SPEC {
1121    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
1122    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
1123}
1124#[doc = "`reset()` method sets pc_cfg0 to value 0"]
1125impl crate::Resettable for PC_CFG0_SPEC {
1126    const RESET_VALUE: Self::Ux = 0;
1127}
d1_pac/gpio/pc_cfg0.rs

d1_pac/gpio/
pc_cfg0.rs
