1#[doc = "Register `pb_cfg0` reader"]
2pub type R = crate::R<PB_CFG0_SPEC>;
3#[doc = "Register `pb_cfg0` writer"]
4pub type W = crate::W<PB_CFG0_SPEC>;
5#[doc = "Field `pb0_select` reader - "]
6pub type PB0_SELECT_R = crate::FieldReader<PB0_SELECT_A>;
7#[doc = "\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum PB0_SELECT_A {
11 #[doc = "0: `0`"]
12 INPUT = 0,
13 #[doc = "1: `1`"]
14 OUTPUT = 1,
15 #[doc = "2: `10`"]
16 PWM3 = 2,
17 #[doc = "3: `11`"]
18 IR_TX = 3,
19 #[doc = "4: `100`"]
20 TWI2_SCK = 4,
21 #[doc = "5: `101`"]
22 SPI1_WP_DBI_TE = 5,
23 #[doc = "6: `110`"]
24 UART0_TX = 6,
25 #[doc = "7: `111`"]
26 UART2_TX = 7,
27 #[doc = "8: `1000`"]
28 OWA_OUT = 8,
29 #[doc = "14: `1110`"]
30 PB_EINT0 = 14,
31 #[doc = "15: `1111`"]
32 IO_DISABLE = 15,
33}
34impl From<PB0_SELECT_A> for u8 {
35 #[inline(always)]
36 fn from(variant: PB0_SELECT_A) -> Self {
37 variant as _
38 }
39}
40impl crate::FieldSpec for PB0_SELECT_A {
41 type Ux = u8;
42}
43impl PB0_SELECT_R {
44 #[doc = "Get enumerated values variant"]
45 #[inline(always)]
46 pub const fn variant(&self) -> Option<PB0_SELECT_A> {
47 match self.bits {
48 0 => Some(PB0_SELECT_A::INPUT),
49 1 => Some(PB0_SELECT_A::OUTPUT),
50 2 => Some(PB0_SELECT_A::PWM3),
51 3 => Some(PB0_SELECT_A::IR_TX),
52 4 => Some(PB0_SELECT_A::TWI2_SCK),
53 5 => Some(PB0_SELECT_A::SPI1_WP_DBI_TE),
54 6 => Some(PB0_SELECT_A::UART0_TX),
55 7 => Some(PB0_SELECT_A::UART2_TX),
56 8 => Some(PB0_SELECT_A::OWA_OUT),
57 14 => Some(PB0_SELECT_A::PB_EINT0),
58 15 => Some(PB0_SELECT_A::IO_DISABLE),
59 _ => None,
60 }
61 }
62 #[doc = "`0`"]
63 #[inline(always)]
64 pub fn is_input(&self) -> bool {
65 *self == PB0_SELECT_A::INPUT
66 }
67 #[doc = "`1`"]
68 #[inline(always)]
69 pub fn is_output(&self) -> bool {
70 *self == PB0_SELECT_A::OUTPUT
71 }
72 #[doc = "`10`"]
73 #[inline(always)]
74 pub fn is_pwm3(&self) -> bool {
75 *self == PB0_SELECT_A::PWM3
76 }
77 #[doc = "`11`"]
78 #[inline(always)]
79 pub fn is_ir_tx(&self) -> bool {
80 *self == PB0_SELECT_A::IR_TX
81 }
82 #[doc = "`100`"]
83 #[inline(always)]
84 pub fn is_twi2_sck(&self) -> bool {
85 *self == PB0_SELECT_A::TWI2_SCK
86 }
87 #[doc = "`101`"]
88 #[inline(always)]
89 pub fn is_spi1_wp_dbi_te(&self) -> bool {
90 *self == PB0_SELECT_A::SPI1_WP_DBI_TE
91 }
92 #[doc = "`110`"]
93 #[inline(always)]
94 pub fn is_uart0_tx(&self) -> bool {
95 *self == PB0_SELECT_A::UART0_TX
96 }
97 #[doc = "`111`"]
98 #[inline(always)]
99 pub fn is_uart2_tx(&self) -> bool {
100 *self == PB0_SELECT_A::UART2_TX
101 }
102 #[doc = "`1000`"]
103 #[inline(always)]
104 pub fn is_owa_out(&self) -> bool {
105 *self == PB0_SELECT_A::OWA_OUT
106 }
107 #[doc = "`1110`"]
108 #[inline(always)]
109 pub fn is_pb_eint0(&self) -> bool {
110 *self == PB0_SELECT_A::PB_EINT0
111 }
112 #[doc = "`1111`"]
113 #[inline(always)]
114 pub fn is_io_disable(&self) -> bool {
115 *self == PB0_SELECT_A::IO_DISABLE
116 }
117}
118#[doc = "Field `pb0_select` writer - "]
119pub type PB0_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PB0_SELECT_A>;
120impl<'a, REG> PB0_SELECT_W<'a, REG>
121where
122 REG: crate::Writable + crate::RegisterSpec,
123 REG::Ux: From<u8>,
124{
125 #[doc = "`0`"]
126 #[inline(always)]
127 pub fn input(self) -> &'a mut crate::W<REG> {
128 self.variant(PB0_SELECT_A::INPUT)
129 }
130 #[doc = "`1`"]
131 #[inline(always)]
132 pub fn output(self) -> &'a mut crate::W<REG> {
133 self.variant(PB0_SELECT_A::OUTPUT)
134 }
135 #[doc = "`10`"]
136 #[inline(always)]
137 pub fn pwm3(self) -> &'a mut crate::W<REG> {
138 self.variant(PB0_SELECT_A::PWM3)
139 }
140 #[doc = "`11`"]
141 #[inline(always)]
142 pub fn ir_tx(self) -> &'a mut crate::W<REG> {
143 self.variant(PB0_SELECT_A::IR_TX)
144 }
145 #[doc = "`100`"]
146 #[inline(always)]
147 pub fn twi2_sck(self) -> &'a mut crate::W<REG> {
148 self.variant(PB0_SELECT_A::TWI2_SCK)
149 }
150 #[doc = "`101`"]
151 #[inline(always)]
152 pub fn spi1_wp_dbi_te(self) -> &'a mut crate::W<REG> {
153 self.variant(PB0_SELECT_A::SPI1_WP_DBI_TE)
154 }
155 #[doc = "`110`"]
156 #[inline(always)]
157 pub fn uart0_tx(self) -> &'a mut crate::W<REG> {
158 self.variant(PB0_SELECT_A::UART0_TX)
159 }
160 #[doc = "`111`"]
161 #[inline(always)]
162 pub fn uart2_tx(self) -> &'a mut crate::W<REG> {
163 self.variant(PB0_SELECT_A::UART2_TX)
164 }
165 #[doc = "`1000`"]
166 #[inline(always)]
167 pub fn owa_out(self) -> &'a mut crate::W<REG> {
168 self.variant(PB0_SELECT_A::OWA_OUT)
169 }
170 #[doc = "`1110`"]
171 #[inline(always)]
172 pub fn pb_eint0(self) -> &'a mut crate::W<REG> {
173 self.variant(PB0_SELECT_A::PB_EINT0)
174 }
175 #[doc = "`1111`"]
176 #[inline(always)]
177 pub fn io_disable(self) -> &'a mut crate::W<REG> {
178 self.variant(PB0_SELECT_A::IO_DISABLE)
179 }
180}
181#[doc = "Field `pb1_select` reader - "]
182pub type PB1_SELECT_R = crate::FieldReader<PB1_SELECT_A>;
183#[doc = "\n\nValue on reset: 0"]
184#[derive(Clone, Copy, Debug, PartialEq, Eq)]
185#[repr(u8)]
186pub enum PB1_SELECT_A {
187 #[doc = "0: `0`"]
188 INPUT = 0,
189 #[doc = "1: `1`"]
190 OUTPUT = 1,
191 #[doc = "2: `10`"]
192 PWM4 = 2,
193 #[doc = "3: `11`"]
194 I2_S2_DOUT3 = 3,
195 #[doc = "4: `100`"]
196 TWI2_SDA = 4,
197 #[doc = "5: `101`"]
198 I2_S2_DIN3 = 5,
199 #[doc = "6: `110`"]
200 UART0_RX = 6,
201 #[doc = "7: `111`"]
202 UART2_RX = 7,
203 #[doc = "8: `1000`"]
204 IR_RX = 8,
205 #[doc = "14: `1110`"]
206 PB_EINT1 = 14,
207 #[doc = "15: `1111`"]
208 IO_DISABLE = 15,
209}
210impl From<PB1_SELECT_A> for u8 {
211 #[inline(always)]
212 fn from(variant: PB1_SELECT_A) -> Self {
213 variant as _
214 }
215}
216impl crate::FieldSpec for PB1_SELECT_A {
217 type Ux = u8;
218}
219impl PB1_SELECT_R {
220 #[doc = "Get enumerated values variant"]
221 #[inline(always)]
222 pub const fn variant(&self) -> Option<PB1_SELECT_A> {
223 match self.bits {
224 0 => Some(PB1_SELECT_A::INPUT),
225 1 => Some(PB1_SELECT_A::OUTPUT),
226 2 => Some(PB1_SELECT_A::PWM4),
227 3 => Some(PB1_SELECT_A::I2_S2_DOUT3),
228 4 => Some(PB1_SELECT_A::TWI2_SDA),
229 5 => Some(PB1_SELECT_A::I2_S2_DIN3),
230 6 => Some(PB1_SELECT_A::UART0_RX),
231 7 => Some(PB1_SELECT_A::UART2_RX),
232 8 => Some(PB1_SELECT_A::IR_RX),
233 14 => Some(PB1_SELECT_A::PB_EINT1),
234 15 => Some(PB1_SELECT_A::IO_DISABLE),
235 _ => None,
236 }
237 }
238 #[doc = "`0`"]
239 #[inline(always)]
240 pub fn is_input(&self) -> bool {
241 *self == PB1_SELECT_A::INPUT
242 }
243 #[doc = "`1`"]
244 #[inline(always)]
245 pub fn is_output(&self) -> bool {
246 *self == PB1_SELECT_A::OUTPUT
247 }
248 #[doc = "`10`"]
249 #[inline(always)]
250 pub fn is_pwm4(&self) -> bool {
251 *self == PB1_SELECT_A::PWM4
252 }
253 #[doc = "`11`"]
254 #[inline(always)]
255 pub fn is_i2_s2_dout3(&self) -> bool {
256 *self == PB1_SELECT_A::I2_S2_DOUT3
257 }
258 #[doc = "`100`"]
259 #[inline(always)]
260 pub fn is_twi2_sda(&self) -> bool {
261 *self == PB1_SELECT_A::TWI2_SDA
262 }
263 #[doc = "`101`"]
264 #[inline(always)]
265 pub fn is_i2_s2_din3(&self) -> bool {
266 *self == PB1_SELECT_A::I2_S2_DIN3
267 }
268 #[doc = "`110`"]
269 #[inline(always)]
270 pub fn is_uart0_rx(&self) -> bool {
271 *self == PB1_SELECT_A::UART0_RX
272 }
273 #[doc = "`111`"]
274 #[inline(always)]
275 pub fn is_uart2_rx(&self) -> bool {
276 *self == PB1_SELECT_A::UART2_RX
277 }
278 #[doc = "`1000`"]
279 #[inline(always)]
280 pub fn is_ir_rx(&self) -> bool {
281 *self == PB1_SELECT_A::IR_RX
282 }
283 #[doc = "`1110`"]
284 #[inline(always)]
285 pub fn is_pb_eint1(&self) -> bool {
286 *self == PB1_SELECT_A::PB_EINT1
287 }
288 #[doc = "`1111`"]
289 #[inline(always)]
290 pub fn is_io_disable(&self) -> bool {
291 *self == PB1_SELECT_A::IO_DISABLE
292 }
293}
294#[doc = "Field `pb1_select` writer - "]
295pub type PB1_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PB1_SELECT_A>;
296impl<'a, REG> PB1_SELECT_W<'a, REG>
297where
298 REG: crate::Writable + crate::RegisterSpec,
299 REG::Ux: From<u8>,
300{
301 #[doc = "`0`"]
302 #[inline(always)]
303 pub fn input(self) -> &'a mut crate::W<REG> {
304 self.variant(PB1_SELECT_A::INPUT)
305 }
306 #[doc = "`1`"]
307 #[inline(always)]
308 pub fn output(self) -> &'a mut crate::W<REG> {
309 self.variant(PB1_SELECT_A::OUTPUT)
310 }
311 #[doc = "`10`"]
312 #[inline(always)]
313 pub fn pwm4(self) -> &'a mut crate::W<REG> {
314 self.variant(PB1_SELECT_A::PWM4)
315 }
316 #[doc = "`11`"]
317 #[inline(always)]
318 pub fn i2_s2_dout3(self) -> &'a mut crate::W<REG> {
319 self.variant(PB1_SELECT_A::I2_S2_DOUT3)
320 }
321 #[doc = "`100`"]
322 #[inline(always)]
323 pub fn twi2_sda(self) -> &'a mut crate::W<REG> {
324 self.variant(PB1_SELECT_A::TWI2_SDA)
325 }
326 #[doc = "`101`"]
327 #[inline(always)]
328 pub fn i2_s2_din3(self) -> &'a mut crate::W<REG> {
329 self.variant(PB1_SELECT_A::I2_S2_DIN3)
330 }
331 #[doc = "`110`"]
332 #[inline(always)]
333 pub fn uart0_rx(self) -> &'a mut crate::W<REG> {
334 self.variant(PB1_SELECT_A::UART0_RX)
335 }
336 #[doc = "`111`"]
337 #[inline(always)]
338 pub fn uart2_rx(self) -> &'a mut crate::W<REG> {
339 self.variant(PB1_SELECT_A::UART2_RX)
340 }
341 #[doc = "`1000`"]
342 #[inline(always)]
343 pub fn ir_rx(self) -> &'a mut crate::W<REG> {
344 self.variant(PB1_SELECT_A::IR_RX)
345 }
346 #[doc = "`1110`"]
347 #[inline(always)]
348 pub fn pb_eint1(self) -> &'a mut crate::W<REG> {
349 self.variant(PB1_SELECT_A::PB_EINT1)
350 }
351 #[doc = "`1111`"]
352 #[inline(always)]
353 pub fn io_disable(self) -> &'a mut crate::W<REG> {
354 self.variant(PB1_SELECT_A::IO_DISABLE)
355 }
356}
357#[doc = "Field `pb2_select` reader - "]
358pub type PB2_SELECT_R = crate::FieldReader<PB2_SELECT_A>;
359#[doc = "\n\nValue on reset: 0"]
360#[derive(Clone, Copy, Debug, PartialEq, Eq)]
361#[repr(u8)]
362pub enum PB2_SELECT_A {
363 #[doc = "0: `0`"]
364 INPUT = 0,
365 #[doc = "1: `1`"]
366 OUTPUT = 1,
367 #[doc = "2: `10`"]
368 LCD0_D0 = 2,
369 #[doc = "3: `11`"]
370 I2_S2_DOUT2 = 3,
371 #[doc = "4: `100`"]
372 TWI0_SDA = 4,
373 #[doc = "5: `101`"]
374 I2_S2_DIN2 = 5,
375 #[doc = "6: `110`"]
376 LCD0_D18 = 6,
377 #[doc = "7: `111`"]
378 UART4_TX = 7,
379 #[doc = "14: `1110`"]
380 PB_EINT2 = 14,
381 #[doc = "15: `1111`"]
382 IO_DISABLE = 15,
383}
384impl From<PB2_SELECT_A> for u8 {
385 #[inline(always)]
386 fn from(variant: PB2_SELECT_A) -> Self {
387 variant as _
388 }
389}
390impl crate::FieldSpec for PB2_SELECT_A {
391 type Ux = u8;
392}
393impl PB2_SELECT_R {
394 #[doc = "Get enumerated values variant"]
395 #[inline(always)]
396 pub const fn variant(&self) -> Option<PB2_SELECT_A> {
397 match self.bits {
398 0 => Some(PB2_SELECT_A::INPUT),
399 1 => Some(PB2_SELECT_A::OUTPUT),
400 2 => Some(PB2_SELECT_A::LCD0_D0),
401 3 => Some(PB2_SELECT_A::I2_S2_DOUT2),
402 4 => Some(PB2_SELECT_A::TWI0_SDA),
403 5 => Some(PB2_SELECT_A::I2_S2_DIN2),
404 6 => Some(PB2_SELECT_A::LCD0_D18),
405 7 => Some(PB2_SELECT_A::UART4_TX),
406 14 => Some(PB2_SELECT_A::PB_EINT2),
407 15 => Some(PB2_SELECT_A::IO_DISABLE),
408 _ => None,
409 }
410 }
411 #[doc = "`0`"]
412 #[inline(always)]
413 pub fn is_input(&self) -> bool {
414 *self == PB2_SELECT_A::INPUT
415 }
416 #[doc = "`1`"]
417 #[inline(always)]
418 pub fn is_output(&self) -> bool {
419 *self == PB2_SELECT_A::OUTPUT
420 }
421 #[doc = "`10`"]
422 #[inline(always)]
423 pub fn is_lcd0_d0(&self) -> bool {
424 *self == PB2_SELECT_A::LCD0_D0
425 }
426 #[doc = "`11`"]
427 #[inline(always)]
428 pub fn is_i2_s2_dout2(&self) -> bool {
429 *self == PB2_SELECT_A::I2_S2_DOUT2
430 }
431 #[doc = "`100`"]
432 #[inline(always)]
433 pub fn is_twi0_sda(&self) -> bool {
434 *self == PB2_SELECT_A::TWI0_SDA
435 }
436 #[doc = "`101`"]
437 #[inline(always)]
438 pub fn is_i2_s2_din2(&self) -> bool {
439 *self == PB2_SELECT_A::I2_S2_DIN2
440 }
441 #[doc = "`110`"]
442 #[inline(always)]
443 pub fn is_lcd0_d18(&self) -> bool {
444 *self == PB2_SELECT_A::LCD0_D18
445 }
446 #[doc = "`111`"]
447 #[inline(always)]
448 pub fn is_uart4_tx(&self) -> bool {
449 *self == PB2_SELECT_A::UART4_TX
450 }
451 #[doc = "`1110`"]
452 #[inline(always)]
453 pub fn is_pb_eint2(&self) -> bool {
454 *self == PB2_SELECT_A::PB_EINT2
455 }
456 #[doc = "`1111`"]
457 #[inline(always)]
458 pub fn is_io_disable(&self) -> bool {
459 *self == PB2_SELECT_A::IO_DISABLE
460 }
461}
462#[doc = "Field `pb2_select` writer - "]
463pub type PB2_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PB2_SELECT_A>;
464impl<'a, REG> PB2_SELECT_W<'a, REG>
465where
466 REG: crate::Writable + crate::RegisterSpec,
467 REG::Ux: From<u8>,
468{
469 #[doc = "`0`"]
470 #[inline(always)]
471 pub fn input(self) -> &'a mut crate::W<REG> {
472 self.variant(PB2_SELECT_A::INPUT)
473 }
474 #[doc = "`1`"]
475 #[inline(always)]
476 pub fn output(self) -> &'a mut crate::W<REG> {
477 self.variant(PB2_SELECT_A::OUTPUT)
478 }
479 #[doc = "`10`"]
480 #[inline(always)]
481 pub fn lcd0_d0(self) -> &'a mut crate::W<REG> {
482 self.variant(PB2_SELECT_A::LCD0_D0)
483 }
484 #[doc = "`11`"]
485 #[inline(always)]
486 pub fn i2_s2_dout2(self) -> &'a mut crate::W<REG> {
487 self.variant(PB2_SELECT_A::I2_S2_DOUT2)
488 }
489 #[doc = "`100`"]
490 #[inline(always)]
491 pub fn twi0_sda(self) -> &'a mut crate::W<REG> {
492 self.variant(PB2_SELECT_A::TWI0_SDA)
493 }
494 #[doc = "`101`"]
495 #[inline(always)]
496 pub fn i2_s2_din2(self) -> &'a mut crate::W<REG> {
497 self.variant(PB2_SELECT_A::I2_S2_DIN2)
498 }
499 #[doc = "`110`"]
500 #[inline(always)]
501 pub fn lcd0_d18(self) -> &'a mut crate::W<REG> {
502 self.variant(PB2_SELECT_A::LCD0_D18)
503 }
504 #[doc = "`111`"]
505 #[inline(always)]
506 pub fn uart4_tx(self) -> &'a mut crate::W<REG> {
507 self.variant(PB2_SELECT_A::UART4_TX)
508 }
509 #[doc = "`1110`"]
510 #[inline(always)]
511 pub fn pb_eint2(self) -> &'a mut crate::W<REG> {
512 self.variant(PB2_SELECT_A::PB_EINT2)
513 }
514 #[doc = "`1111`"]
515 #[inline(always)]
516 pub fn io_disable(self) -> &'a mut crate::W<REG> {
517 self.variant(PB2_SELECT_A::IO_DISABLE)
518 }
519}
520#[doc = "Field `pb3_select` reader - "]
521pub type PB3_SELECT_R = crate::FieldReader<PB3_SELECT_A>;
522#[doc = "\n\nValue on reset: 0"]
523#[derive(Clone, Copy, Debug, PartialEq, Eq)]
524#[repr(u8)]
525pub enum PB3_SELECT_A {
526 #[doc = "0: `0`"]
527 INPUT = 0,
528 #[doc = "1: `1`"]
529 OUTPUT = 1,
530 #[doc = "2: `10`"]
531 LCD0_D1 = 2,
532 #[doc = "3: `11`"]
533 I2_S2_DOUT1 = 3,
534 #[doc = "4: `100`"]
535 TWI0_SCK = 4,
536 #[doc = "5: `101`"]
537 I2_S2_DIN0 = 5,
538 #[doc = "6: `110`"]
539 LCD0_D19 = 6,
540 #[doc = "7: `111`"]
541 UART4_RX = 7,
542 #[doc = "14: `1110`"]
543 PB_EINT3 = 14,
544 #[doc = "15: `1111`"]
545 IO_DISABLE = 15,
546}
547impl From<PB3_SELECT_A> for u8 {
548 #[inline(always)]
549 fn from(variant: PB3_SELECT_A) -> Self {
550 variant as _
551 }
552}
553impl crate::FieldSpec for PB3_SELECT_A {
554 type Ux = u8;
555}
556impl PB3_SELECT_R {
557 #[doc = "Get enumerated values variant"]
558 #[inline(always)]
559 pub const fn variant(&self) -> Option<PB3_SELECT_A> {
560 match self.bits {
561 0 => Some(PB3_SELECT_A::INPUT),
562 1 => Some(PB3_SELECT_A::OUTPUT),
563 2 => Some(PB3_SELECT_A::LCD0_D1),
564 3 => Some(PB3_SELECT_A::I2_S2_DOUT1),
565 4 => Some(PB3_SELECT_A::TWI0_SCK),
566 5 => Some(PB3_SELECT_A::I2_S2_DIN0),
567 6 => Some(PB3_SELECT_A::LCD0_D19),
568 7 => Some(PB3_SELECT_A::UART4_RX),
569 14 => Some(PB3_SELECT_A::PB_EINT3),
570 15 => Some(PB3_SELECT_A::IO_DISABLE),
571 _ => None,
572 }
573 }
574 #[doc = "`0`"]
575 #[inline(always)]
576 pub fn is_input(&self) -> bool {
577 *self == PB3_SELECT_A::INPUT
578 }
579 #[doc = "`1`"]
580 #[inline(always)]
581 pub fn is_output(&self) -> bool {
582 *self == PB3_SELECT_A::OUTPUT
583 }
584 #[doc = "`10`"]
585 #[inline(always)]
586 pub fn is_lcd0_d1(&self) -> bool {
587 *self == PB3_SELECT_A::LCD0_D1
588 }
589 #[doc = "`11`"]
590 #[inline(always)]
591 pub fn is_i2_s2_dout1(&self) -> bool {
592 *self == PB3_SELECT_A::I2_S2_DOUT1
593 }
594 #[doc = "`100`"]
595 #[inline(always)]
596 pub fn is_twi0_sck(&self) -> bool {
597 *self == PB3_SELECT_A::TWI0_SCK
598 }
599 #[doc = "`101`"]
600 #[inline(always)]
601 pub fn is_i2_s2_din0(&self) -> bool {
602 *self == PB3_SELECT_A::I2_S2_DIN0
603 }
604 #[doc = "`110`"]
605 #[inline(always)]
606 pub fn is_lcd0_d19(&self) -> bool {
607 *self == PB3_SELECT_A::LCD0_D19
608 }
609 #[doc = "`111`"]
610 #[inline(always)]
611 pub fn is_uart4_rx(&self) -> bool {
612 *self == PB3_SELECT_A::UART4_RX
613 }
614 #[doc = "`1110`"]
615 #[inline(always)]
616 pub fn is_pb_eint3(&self) -> bool {
617 *self == PB3_SELECT_A::PB_EINT3
618 }
619 #[doc = "`1111`"]
620 #[inline(always)]
621 pub fn is_io_disable(&self) -> bool {
622 *self == PB3_SELECT_A::IO_DISABLE
623 }
624}
625#[doc = "Field `pb3_select` writer - "]
626pub type PB3_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PB3_SELECT_A>;
627impl<'a, REG> PB3_SELECT_W<'a, REG>
628where
629 REG: crate::Writable + crate::RegisterSpec,
630 REG::Ux: From<u8>,
631{
632 #[doc = "`0`"]
633 #[inline(always)]
634 pub fn input(self) -> &'a mut crate::W<REG> {
635 self.variant(PB3_SELECT_A::INPUT)
636 }
637 #[doc = "`1`"]
638 #[inline(always)]
639 pub fn output(self) -> &'a mut crate::W<REG> {
640 self.variant(PB3_SELECT_A::OUTPUT)
641 }
642 #[doc = "`10`"]
643 #[inline(always)]
644 pub fn lcd0_d1(self) -> &'a mut crate::W<REG> {
645 self.variant(PB3_SELECT_A::LCD0_D1)
646 }
647 #[doc = "`11`"]
648 #[inline(always)]
649 pub fn i2_s2_dout1(self) -> &'a mut crate::W<REG> {
650 self.variant(PB3_SELECT_A::I2_S2_DOUT1)
651 }
652 #[doc = "`100`"]
653 #[inline(always)]
654 pub fn twi0_sck(self) -> &'a mut crate::W<REG> {
655 self.variant(PB3_SELECT_A::TWI0_SCK)
656 }
657 #[doc = "`101`"]
658 #[inline(always)]
659 pub fn i2_s2_din0(self) -> &'a mut crate::W<REG> {
660 self.variant(PB3_SELECT_A::I2_S2_DIN0)
661 }
662 #[doc = "`110`"]
663 #[inline(always)]
664 pub fn lcd0_d19(self) -> &'a mut crate::W<REG> {
665 self.variant(PB3_SELECT_A::LCD0_D19)
666 }
667 #[doc = "`111`"]
668 #[inline(always)]
669 pub fn uart4_rx(self) -> &'a mut crate::W<REG> {
670 self.variant(PB3_SELECT_A::UART4_RX)
671 }
672 #[doc = "`1110`"]
673 #[inline(always)]
674 pub fn pb_eint3(self) -> &'a mut crate::W<REG> {
675 self.variant(PB3_SELECT_A::PB_EINT3)
676 }
677 #[doc = "`1111`"]
678 #[inline(always)]
679 pub fn io_disable(self) -> &'a mut crate::W<REG> {
680 self.variant(PB3_SELECT_A::IO_DISABLE)
681 }
682}
683#[doc = "Field `pb4_select` reader - "]
684pub type PB4_SELECT_R = crate::FieldReader<PB4_SELECT_A>;
685#[doc = "\n\nValue on reset: 0"]
686#[derive(Clone, Copy, Debug, PartialEq, Eq)]
687#[repr(u8)]
688pub enum PB4_SELECT_A {
689 #[doc = "0: `0`"]
690 INPUT = 0,
691 #[doc = "1: `1`"]
692 OUTPUT = 1,
693 #[doc = "2: `10`"]
694 LCD0_D8 = 2,
695 #[doc = "3: `11`"]
696 I2_S2_DOUT0 = 3,
697 #[doc = "4: `100`"]
698 TWI1_SCK = 4,
699 #[doc = "5: `101`"]
700 I2_S2_DIN1 = 5,
701 #[doc = "6: `110`"]
702 LCD0_D20 = 6,
703 #[doc = "7: `111`"]
704 UART5_TX = 7,
705 #[doc = "14: `1110`"]
706 PB_EINT4 = 14,
707 #[doc = "15: `1111`"]
708 IO_DISABLE = 15,
709}
710impl From<PB4_SELECT_A> for u8 {
711 #[inline(always)]
712 fn from(variant: PB4_SELECT_A) -> Self {
713 variant as _
714 }
715}
716impl crate::FieldSpec for PB4_SELECT_A {
717 type Ux = u8;
718}
719impl PB4_SELECT_R {
720 #[doc = "Get enumerated values variant"]
721 #[inline(always)]
722 pub const fn variant(&self) -> Option<PB4_SELECT_A> {
723 match self.bits {
724 0 => Some(PB4_SELECT_A::INPUT),
725 1 => Some(PB4_SELECT_A::OUTPUT),
726 2 => Some(PB4_SELECT_A::LCD0_D8),
727 3 => Some(PB4_SELECT_A::I2_S2_DOUT0),
728 4 => Some(PB4_SELECT_A::TWI1_SCK),
729 5 => Some(PB4_SELECT_A::I2_S2_DIN1),
730 6 => Some(PB4_SELECT_A::LCD0_D20),
731 7 => Some(PB4_SELECT_A::UART5_TX),
732 14 => Some(PB4_SELECT_A::PB_EINT4),
733 15 => Some(PB4_SELECT_A::IO_DISABLE),
734 _ => None,
735 }
736 }
737 #[doc = "`0`"]
738 #[inline(always)]
739 pub fn is_input(&self) -> bool {
740 *self == PB4_SELECT_A::INPUT
741 }
742 #[doc = "`1`"]
743 #[inline(always)]
744 pub fn is_output(&self) -> bool {
745 *self == PB4_SELECT_A::OUTPUT
746 }
747 #[doc = "`10`"]
748 #[inline(always)]
749 pub fn is_lcd0_d8(&self) -> bool {
750 *self == PB4_SELECT_A::LCD0_D8
751 }
752 #[doc = "`11`"]
753 #[inline(always)]
754 pub fn is_i2_s2_dout0(&self) -> bool {
755 *self == PB4_SELECT_A::I2_S2_DOUT0
756 }
757 #[doc = "`100`"]
758 #[inline(always)]
759 pub fn is_twi1_sck(&self) -> bool {
760 *self == PB4_SELECT_A::TWI1_SCK
761 }
762 #[doc = "`101`"]
763 #[inline(always)]
764 pub fn is_i2_s2_din1(&self) -> bool {
765 *self == PB4_SELECT_A::I2_S2_DIN1
766 }
767 #[doc = "`110`"]
768 #[inline(always)]
769 pub fn is_lcd0_d20(&self) -> bool {
770 *self == PB4_SELECT_A::LCD0_D20
771 }
772 #[doc = "`111`"]
773 #[inline(always)]
774 pub fn is_uart5_tx(&self) -> bool {
775 *self == PB4_SELECT_A::UART5_TX
776 }
777 #[doc = "`1110`"]
778 #[inline(always)]
779 pub fn is_pb_eint4(&self) -> bool {
780 *self == PB4_SELECT_A::PB_EINT4
781 }
782 #[doc = "`1111`"]
783 #[inline(always)]
784 pub fn is_io_disable(&self) -> bool {
785 *self == PB4_SELECT_A::IO_DISABLE
786 }
787}
788#[doc = "Field `pb4_select` writer - "]
789pub type PB4_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PB4_SELECT_A>;
790impl<'a, REG> PB4_SELECT_W<'a, REG>
791where
792 REG: crate::Writable + crate::RegisterSpec,
793 REG::Ux: From<u8>,
794{
795 #[doc = "`0`"]
796 #[inline(always)]
797 pub fn input(self) -> &'a mut crate::W<REG> {
798 self.variant(PB4_SELECT_A::INPUT)
799 }
800 #[doc = "`1`"]
801 #[inline(always)]
802 pub fn output(self) -> &'a mut crate::W<REG> {
803 self.variant(PB4_SELECT_A::OUTPUT)
804 }
805 #[doc = "`10`"]
806 #[inline(always)]
807 pub fn lcd0_d8(self) -> &'a mut crate::W<REG> {
808 self.variant(PB4_SELECT_A::LCD0_D8)
809 }
810 #[doc = "`11`"]
811 #[inline(always)]
812 pub fn i2_s2_dout0(self) -> &'a mut crate::W<REG> {
813 self.variant(PB4_SELECT_A::I2_S2_DOUT0)
814 }
815 #[doc = "`100`"]
816 #[inline(always)]
817 pub fn twi1_sck(self) -> &'a mut crate::W<REG> {
818 self.variant(PB4_SELECT_A::TWI1_SCK)
819 }
820 #[doc = "`101`"]
821 #[inline(always)]
822 pub fn i2_s2_din1(self) -> &'a mut crate::W<REG> {
823 self.variant(PB4_SELECT_A::I2_S2_DIN1)
824 }
825 #[doc = "`110`"]
826 #[inline(always)]
827 pub fn lcd0_d20(self) -> &'a mut crate::W<REG> {
828 self.variant(PB4_SELECT_A::LCD0_D20)
829 }
830 #[doc = "`111`"]
831 #[inline(always)]
832 pub fn uart5_tx(self) -> &'a mut crate::W<REG> {
833 self.variant(PB4_SELECT_A::UART5_TX)
834 }
835 #[doc = "`1110`"]
836 #[inline(always)]
837 pub fn pb_eint4(self) -> &'a mut crate::W<REG> {
838 self.variant(PB4_SELECT_A::PB_EINT4)
839 }
840 #[doc = "`1111`"]
841 #[inline(always)]
842 pub fn io_disable(self) -> &'a mut crate::W<REG> {
843 self.variant(PB4_SELECT_A::IO_DISABLE)
844 }
845}
846#[doc = "Field `pb5_select` reader - "]
847pub type PB5_SELECT_R = crate::FieldReader<PB5_SELECT_A>;
848#[doc = "\n\nValue on reset: 0"]
849#[derive(Clone, Copy, Debug, PartialEq, Eq)]
850#[repr(u8)]
851pub enum PB5_SELECT_A {
852 #[doc = "0: `0`"]
853 INPUT = 0,
854 #[doc = "1: `1`"]
855 OUTPUT = 1,
856 #[doc = "2: `10`"]
857 LCD0_D9 = 2,
858 #[doc = "3: `11`"]
859 I2_S2_BCLK = 3,
860 #[doc = "4: `100`"]
861 TWI1_SDA = 4,
862 #[doc = "5: `101`"]
863 PWM0 = 5,
864 #[doc = "6: `110`"]
865 LCD0_D21 = 6,
866 #[doc = "7: `111`"]
867 UART5_RX = 7,
868 #[doc = "14: `1110`"]
869 PB_EINT5 = 14,
870 #[doc = "15: `1111`"]
871 IO_DISABLE = 15,
872}
873impl From<PB5_SELECT_A> for u8 {
874 #[inline(always)]
875 fn from(variant: PB5_SELECT_A) -> Self {
876 variant as _
877 }
878}
879impl crate::FieldSpec for PB5_SELECT_A {
880 type Ux = u8;
881}
882impl PB5_SELECT_R {
883 #[doc = "Get enumerated values variant"]
884 #[inline(always)]
885 pub const fn variant(&self) -> Option<PB5_SELECT_A> {
886 match self.bits {
887 0 => Some(PB5_SELECT_A::INPUT),
888 1 => Some(PB5_SELECT_A::OUTPUT),
889 2 => Some(PB5_SELECT_A::LCD0_D9),
890 3 => Some(PB5_SELECT_A::I2_S2_BCLK),
891 4 => Some(PB5_SELECT_A::TWI1_SDA),
892 5 => Some(PB5_SELECT_A::PWM0),
893 6 => Some(PB5_SELECT_A::LCD0_D21),
894 7 => Some(PB5_SELECT_A::UART5_RX),
895 14 => Some(PB5_SELECT_A::PB_EINT5),
896 15 => Some(PB5_SELECT_A::IO_DISABLE),
897 _ => None,
898 }
899 }
900 #[doc = "`0`"]
901 #[inline(always)]
902 pub fn is_input(&self) -> bool {
903 *self == PB5_SELECT_A::INPUT
904 }
905 #[doc = "`1`"]
906 #[inline(always)]
907 pub fn is_output(&self) -> bool {
908 *self == PB5_SELECT_A::OUTPUT
909 }
910 #[doc = "`10`"]
911 #[inline(always)]
912 pub fn is_lcd0_d9(&self) -> bool {
913 *self == PB5_SELECT_A::LCD0_D9
914 }
915 #[doc = "`11`"]
916 #[inline(always)]
917 pub fn is_i2_s2_bclk(&self) -> bool {
918 *self == PB5_SELECT_A::I2_S2_BCLK
919 }
920 #[doc = "`100`"]
921 #[inline(always)]
922 pub fn is_twi1_sda(&self) -> bool {
923 *self == PB5_SELECT_A::TWI1_SDA
924 }
925 #[doc = "`101`"]
926 #[inline(always)]
927 pub fn is_pwm0(&self) -> bool {
928 *self == PB5_SELECT_A::PWM0
929 }
930 #[doc = "`110`"]
931 #[inline(always)]
932 pub fn is_lcd0_d21(&self) -> bool {
933 *self == PB5_SELECT_A::LCD0_D21
934 }
935 #[doc = "`111`"]
936 #[inline(always)]
937 pub fn is_uart5_rx(&self) -> bool {
938 *self == PB5_SELECT_A::UART5_RX
939 }
940 #[doc = "`1110`"]
941 #[inline(always)]
942 pub fn is_pb_eint5(&self) -> bool {
943 *self == PB5_SELECT_A::PB_EINT5
944 }
945 #[doc = "`1111`"]
946 #[inline(always)]
947 pub fn is_io_disable(&self) -> bool {
948 *self == PB5_SELECT_A::IO_DISABLE
949 }
950}
951#[doc = "Field `pb5_select` writer - "]
952pub type PB5_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PB5_SELECT_A>;
953impl<'a, REG> PB5_SELECT_W<'a, REG>
954where
955 REG: crate::Writable + crate::RegisterSpec,
956 REG::Ux: From<u8>,
957{
958 #[doc = "`0`"]
959 #[inline(always)]
960 pub fn input(self) -> &'a mut crate::W<REG> {
961 self.variant(PB5_SELECT_A::INPUT)
962 }
963 #[doc = "`1`"]
964 #[inline(always)]
965 pub fn output(self) -> &'a mut crate::W<REG> {
966 self.variant(PB5_SELECT_A::OUTPUT)
967 }
968 #[doc = "`10`"]
969 #[inline(always)]
970 pub fn lcd0_d9(self) -> &'a mut crate::W<REG> {
971 self.variant(PB5_SELECT_A::LCD0_D9)
972 }
973 #[doc = "`11`"]
974 #[inline(always)]
975 pub fn i2_s2_bclk(self) -> &'a mut crate::W<REG> {
976 self.variant(PB5_SELECT_A::I2_S2_BCLK)
977 }
978 #[doc = "`100`"]
979 #[inline(always)]
980 pub fn twi1_sda(self) -> &'a mut crate::W<REG> {
981 self.variant(PB5_SELECT_A::TWI1_SDA)
982 }
983 #[doc = "`101`"]
984 #[inline(always)]
985 pub fn pwm0(self) -> &'a mut crate::W<REG> {
986 self.variant(PB5_SELECT_A::PWM0)
987 }
988 #[doc = "`110`"]
989 #[inline(always)]
990 pub fn lcd0_d21(self) -> &'a mut crate::W<REG> {
991 self.variant(PB5_SELECT_A::LCD0_D21)
992 }
993 #[doc = "`111`"]
994 #[inline(always)]
995 pub fn uart5_rx(self) -> &'a mut crate::W<REG> {
996 self.variant(PB5_SELECT_A::UART5_RX)
997 }
998 #[doc = "`1110`"]
999 #[inline(always)]
1000 pub fn pb_eint5(self) -> &'a mut crate::W<REG> {
1001 self.variant(PB5_SELECT_A::PB_EINT5)
1002 }
1003 #[doc = "`1111`"]
1004 #[inline(always)]
1005 pub fn io_disable(self) -> &'a mut crate::W<REG> {
1006 self.variant(PB5_SELECT_A::IO_DISABLE)
1007 }
1008}
1009#[doc = "Field `pb6_select` reader - "]
1010pub type PB6_SELECT_R = crate::FieldReader<PB6_SELECT_A>;
1011#[doc = "\n\nValue on reset: 0"]
1012#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1013#[repr(u8)]
1014pub enum PB6_SELECT_A {
1015 #[doc = "0: `0`"]
1016 INPUT = 0,
1017 #[doc = "1: `1`"]
1018 OUTPUT = 1,
1019 #[doc = "2: `10`"]
1020 LCD0_D16 = 2,
1021 #[doc = "3: `11`"]
1022 I2_S2_LRCK = 3,
1023 #[doc = "4: `100`"]
1024 TWI3_SCK = 4,
1025 #[doc = "5: `101`"]
1026 PWM1 = 5,
1027 #[doc = "6: `110`"]
1028 LCD0_D22 = 6,
1029 #[doc = "7: `111`"]
1030 UART3_TX = 7,
1031 #[doc = "8: `1000`"]
1032 CPUBIST0 = 8,
1033 #[doc = "14: `1110`"]
1034 PB_EINT6 = 14,
1035 #[doc = "15: `1111`"]
1036 IO_DISABLE = 15,
1037}
1038impl From<PB6_SELECT_A> for u8 {
1039 #[inline(always)]
1040 fn from(variant: PB6_SELECT_A) -> Self {
1041 variant as _
1042 }
1043}
1044impl crate::FieldSpec for PB6_SELECT_A {
1045 type Ux = u8;
1046}
1047impl PB6_SELECT_R {
1048 #[doc = "Get enumerated values variant"]
1049 #[inline(always)]
1050 pub const fn variant(&self) -> Option<PB6_SELECT_A> {
1051 match self.bits {
1052 0 => Some(PB6_SELECT_A::INPUT),
1053 1 => Some(PB6_SELECT_A::OUTPUT),
1054 2 => Some(PB6_SELECT_A::LCD0_D16),
1055 3 => Some(PB6_SELECT_A::I2_S2_LRCK),
1056 4 => Some(PB6_SELECT_A::TWI3_SCK),
1057 5 => Some(PB6_SELECT_A::PWM1),
1058 6 => Some(PB6_SELECT_A::LCD0_D22),
1059 7 => Some(PB6_SELECT_A::UART3_TX),
1060 8 => Some(PB6_SELECT_A::CPUBIST0),
1061 14 => Some(PB6_SELECT_A::PB_EINT6),
1062 15 => Some(PB6_SELECT_A::IO_DISABLE),
1063 _ => None,
1064 }
1065 }
1066 #[doc = "`0`"]
1067 #[inline(always)]
1068 pub fn is_input(&self) -> bool {
1069 *self == PB6_SELECT_A::INPUT
1070 }
1071 #[doc = "`1`"]
1072 #[inline(always)]
1073 pub fn is_output(&self) -> bool {
1074 *self == PB6_SELECT_A::OUTPUT
1075 }
1076 #[doc = "`10`"]
1077 #[inline(always)]
1078 pub fn is_lcd0_d16(&self) -> bool {
1079 *self == PB6_SELECT_A::LCD0_D16
1080 }
1081 #[doc = "`11`"]
1082 #[inline(always)]
1083 pub fn is_i2_s2_lrck(&self) -> bool {
1084 *self == PB6_SELECT_A::I2_S2_LRCK
1085 }
1086 #[doc = "`100`"]
1087 #[inline(always)]
1088 pub fn is_twi3_sck(&self) -> bool {
1089 *self == PB6_SELECT_A::TWI3_SCK
1090 }
1091 #[doc = "`101`"]
1092 #[inline(always)]
1093 pub fn is_pwm1(&self) -> bool {
1094 *self == PB6_SELECT_A::PWM1
1095 }
1096 #[doc = "`110`"]
1097 #[inline(always)]
1098 pub fn is_lcd0_d22(&self) -> bool {
1099 *self == PB6_SELECT_A::LCD0_D22
1100 }
1101 #[doc = "`111`"]
1102 #[inline(always)]
1103 pub fn is_uart3_tx(&self) -> bool {
1104 *self == PB6_SELECT_A::UART3_TX
1105 }
1106 #[doc = "`1000`"]
1107 #[inline(always)]
1108 pub fn is_cpubist0(&self) -> bool {
1109 *self == PB6_SELECT_A::CPUBIST0
1110 }
1111 #[doc = "`1110`"]
1112 #[inline(always)]
1113 pub fn is_pb_eint6(&self) -> bool {
1114 *self == PB6_SELECT_A::PB_EINT6
1115 }
1116 #[doc = "`1111`"]
1117 #[inline(always)]
1118 pub fn is_io_disable(&self) -> bool {
1119 *self == PB6_SELECT_A::IO_DISABLE
1120 }
1121}
1122#[doc = "Field `pb6_select` writer - "]
1123pub type PB6_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PB6_SELECT_A>;
1124impl<'a, REG> PB6_SELECT_W<'a, REG>
1125where
1126 REG: crate::Writable + crate::RegisterSpec,
1127 REG::Ux: From<u8>,
1128{
1129 #[doc = "`0`"]
1130 #[inline(always)]
1131 pub fn input(self) -> &'a mut crate::W<REG> {
1132 self.variant(PB6_SELECT_A::INPUT)
1133 }
1134 #[doc = "`1`"]
1135 #[inline(always)]
1136 pub fn output(self) -> &'a mut crate::W<REG> {
1137 self.variant(PB6_SELECT_A::OUTPUT)
1138 }
1139 #[doc = "`10`"]
1140 #[inline(always)]
1141 pub fn lcd0_d16(self) -> &'a mut crate::W<REG> {
1142 self.variant(PB6_SELECT_A::LCD0_D16)
1143 }
1144 #[doc = "`11`"]
1145 #[inline(always)]
1146 pub fn i2_s2_lrck(self) -> &'a mut crate::W<REG> {
1147 self.variant(PB6_SELECT_A::I2_S2_LRCK)
1148 }
1149 #[doc = "`100`"]
1150 #[inline(always)]
1151 pub fn twi3_sck(self) -> &'a mut crate::W<REG> {
1152 self.variant(PB6_SELECT_A::TWI3_SCK)
1153 }
1154 #[doc = "`101`"]
1155 #[inline(always)]
1156 pub fn pwm1(self) -> &'a mut crate::W<REG> {
1157 self.variant(PB6_SELECT_A::PWM1)
1158 }
1159 #[doc = "`110`"]
1160 #[inline(always)]
1161 pub fn lcd0_d22(self) -> &'a mut crate::W<REG> {
1162 self.variant(PB6_SELECT_A::LCD0_D22)
1163 }
1164 #[doc = "`111`"]
1165 #[inline(always)]
1166 pub fn uart3_tx(self) -> &'a mut crate::W<REG> {
1167 self.variant(PB6_SELECT_A::UART3_TX)
1168 }
1169 #[doc = "`1000`"]
1170 #[inline(always)]
1171 pub fn cpubist0(self) -> &'a mut crate::W<REG> {
1172 self.variant(PB6_SELECT_A::CPUBIST0)
1173 }
1174 #[doc = "`1110`"]
1175 #[inline(always)]
1176 pub fn pb_eint6(self) -> &'a mut crate::W<REG> {
1177 self.variant(PB6_SELECT_A::PB_EINT6)
1178 }
1179 #[doc = "`1111`"]
1180 #[inline(always)]
1181 pub fn io_disable(self) -> &'a mut crate::W<REG> {
1182 self.variant(PB6_SELECT_A::IO_DISABLE)
1183 }
1184}
1185#[doc = "Field `pb7_select` reader - "]
1186pub type PB7_SELECT_R = crate::FieldReader<PB7_SELECT_A>;
1187#[doc = "\n\nValue on reset: 0"]
1188#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1189#[repr(u8)]
1190pub enum PB7_SELECT_A {
1191 #[doc = "0: `0`"]
1192 INPUT = 0,
1193 #[doc = "1: `1`"]
1194 OUTPUT = 1,
1195 #[doc = "2: `10`"]
1196 LCD0_D17 = 2,
1197 #[doc = "3: `11`"]
1198 I2_S2_MCLK = 3,
1199 #[doc = "4: `100`"]
1200 TWI3_SDA = 4,
1201 #[doc = "5: `101`"]
1202 IR_RX = 5,
1203 #[doc = "6: `110`"]
1204 LCD0_D23 = 6,
1205 #[doc = "7: `111`"]
1206 UART3_RX = 7,
1207 #[doc = "8: `1000`"]
1208 CPUBIST1 = 8,
1209 #[doc = "14: `1110`"]
1210 PB_EINT7 = 14,
1211 #[doc = "15: `1111`"]
1212 IO_DISABLE = 15,
1213}
1214impl From<PB7_SELECT_A> for u8 {
1215 #[inline(always)]
1216 fn from(variant: PB7_SELECT_A) -> Self {
1217 variant as _
1218 }
1219}
1220impl crate::FieldSpec for PB7_SELECT_A {
1221 type Ux = u8;
1222}
1223impl PB7_SELECT_R {
1224 #[doc = "Get enumerated values variant"]
1225 #[inline(always)]
1226 pub const fn variant(&self) -> Option<PB7_SELECT_A> {
1227 match self.bits {
1228 0 => Some(PB7_SELECT_A::INPUT),
1229 1 => Some(PB7_SELECT_A::OUTPUT),
1230 2 => Some(PB7_SELECT_A::LCD0_D17),
1231 3 => Some(PB7_SELECT_A::I2_S2_MCLK),
1232 4 => Some(PB7_SELECT_A::TWI3_SDA),
1233 5 => Some(PB7_SELECT_A::IR_RX),
1234 6 => Some(PB7_SELECT_A::LCD0_D23),
1235 7 => Some(PB7_SELECT_A::UART3_RX),
1236 8 => Some(PB7_SELECT_A::CPUBIST1),
1237 14 => Some(PB7_SELECT_A::PB_EINT7),
1238 15 => Some(PB7_SELECT_A::IO_DISABLE),
1239 _ => None,
1240 }
1241 }
1242 #[doc = "`0`"]
1243 #[inline(always)]
1244 pub fn is_input(&self) -> bool {
1245 *self == PB7_SELECT_A::INPUT
1246 }
1247 #[doc = "`1`"]
1248 #[inline(always)]
1249 pub fn is_output(&self) -> bool {
1250 *self == PB7_SELECT_A::OUTPUT
1251 }
1252 #[doc = "`10`"]
1253 #[inline(always)]
1254 pub fn is_lcd0_d17(&self) -> bool {
1255 *self == PB7_SELECT_A::LCD0_D17
1256 }
1257 #[doc = "`11`"]
1258 #[inline(always)]
1259 pub fn is_i2_s2_mclk(&self) -> bool {
1260 *self == PB7_SELECT_A::I2_S2_MCLK
1261 }
1262 #[doc = "`100`"]
1263 #[inline(always)]
1264 pub fn is_twi3_sda(&self) -> bool {
1265 *self == PB7_SELECT_A::TWI3_SDA
1266 }
1267 #[doc = "`101`"]
1268 #[inline(always)]
1269 pub fn is_ir_rx(&self) -> bool {
1270 *self == PB7_SELECT_A::IR_RX
1271 }
1272 #[doc = "`110`"]
1273 #[inline(always)]
1274 pub fn is_lcd0_d23(&self) -> bool {
1275 *self == PB7_SELECT_A::LCD0_D23
1276 }
1277 #[doc = "`111`"]
1278 #[inline(always)]
1279 pub fn is_uart3_rx(&self) -> bool {
1280 *self == PB7_SELECT_A::UART3_RX
1281 }
1282 #[doc = "`1000`"]
1283 #[inline(always)]
1284 pub fn is_cpubist1(&self) -> bool {
1285 *self == PB7_SELECT_A::CPUBIST1
1286 }
1287 #[doc = "`1110`"]
1288 #[inline(always)]
1289 pub fn is_pb_eint7(&self) -> bool {
1290 *self == PB7_SELECT_A::PB_EINT7
1291 }
1292 #[doc = "`1111`"]
1293 #[inline(always)]
1294 pub fn is_io_disable(&self) -> bool {
1295 *self == PB7_SELECT_A::IO_DISABLE
1296 }
1297}
1298#[doc = "Field `pb7_select` writer - "]
1299pub type PB7_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PB7_SELECT_A>;
1300impl<'a, REG> PB7_SELECT_W<'a, REG>
1301where
1302 REG: crate::Writable + crate::RegisterSpec,
1303 REG::Ux: From<u8>,
1304{
1305 #[doc = "`0`"]
1306 #[inline(always)]
1307 pub fn input(self) -> &'a mut crate::W<REG> {
1308 self.variant(PB7_SELECT_A::INPUT)
1309 }
1310 #[doc = "`1`"]
1311 #[inline(always)]
1312 pub fn output(self) -> &'a mut crate::W<REG> {
1313 self.variant(PB7_SELECT_A::OUTPUT)
1314 }
1315 #[doc = "`10`"]
1316 #[inline(always)]
1317 pub fn lcd0_d17(self) -> &'a mut crate::W<REG> {
1318 self.variant(PB7_SELECT_A::LCD0_D17)
1319 }
1320 #[doc = "`11`"]
1321 #[inline(always)]
1322 pub fn i2_s2_mclk(self) -> &'a mut crate::W<REG> {
1323 self.variant(PB7_SELECT_A::I2_S2_MCLK)
1324 }
1325 #[doc = "`100`"]
1326 #[inline(always)]
1327 pub fn twi3_sda(self) -> &'a mut crate::W<REG> {
1328 self.variant(PB7_SELECT_A::TWI3_SDA)
1329 }
1330 #[doc = "`101`"]
1331 #[inline(always)]
1332 pub fn ir_rx(self) -> &'a mut crate::W<REG> {
1333 self.variant(PB7_SELECT_A::IR_RX)
1334 }
1335 #[doc = "`110`"]
1336 #[inline(always)]
1337 pub fn lcd0_d23(self) -> &'a mut crate::W<REG> {
1338 self.variant(PB7_SELECT_A::LCD0_D23)
1339 }
1340 #[doc = "`111`"]
1341 #[inline(always)]
1342 pub fn uart3_rx(self) -> &'a mut crate::W<REG> {
1343 self.variant(PB7_SELECT_A::UART3_RX)
1344 }
1345 #[doc = "`1000`"]
1346 #[inline(always)]
1347 pub fn cpubist1(self) -> &'a mut crate::W<REG> {
1348 self.variant(PB7_SELECT_A::CPUBIST1)
1349 }
1350 #[doc = "`1110`"]
1351 #[inline(always)]
1352 pub fn pb_eint7(self) -> &'a mut crate::W<REG> {
1353 self.variant(PB7_SELECT_A::PB_EINT7)
1354 }
1355 #[doc = "`1111`"]
1356 #[inline(always)]
1357 pub fn io_disable(self) -> &'a mut crate::W<REG> {
1358 self.variant(PB7_SELECT_A::IO_DISABLE)
1359 }
1360}
1361impl R {
1362 #[doc = "Bits 0:3"]
1363 #[inline(always)]
1364 pub fn pb0_select(&self) -> PB0_SELECT_R {
1365 PB0_SELECT_R::new((self.bits & 0x0f) as u8)
1366 }
1367 #[doc = "Bits 4:7"]
1368 #[inline(always)]
1369 pub fn pb1_select(&self) -> PB1_SELECT_R {
1370 PB1_SELECT_R::new(((self.bits >> 4) & 0x0f) as u8)
1371 }
1372 #[doc = "Bits 8:11"]
1373 #[inline(always)]
1374 pub fn pb2_select(&self) -> PB2_SELECT_R {
1375 PB2_SELECT_R::new(((self.bits >> 8) & 0x0f) as u8)
1376 }
1377 #[doc = "Bits 12:15"]
1378 #[inline(always)]
1379 pub fn pb3_select(&self) -> PB3_SELECT_R {
1380 PB3_SELECT_R::new(((self.bits >> 12) & 0x0f) as u8)
1381 }
1382 #[doc = "Bits 16:19"]
1383 #[inline(always)]
1384 pub fn pb4_select(&self) -> PB4_SELECT_R {
1385 PB4_SELECT_R::new(((self.bits >> 16) & 0x0f) as u8)
1386 }
1387 #[doc = "Bits 20:23"]
1388 #[inline(always)]
1389 pub fn pb5_select(&self) -> PB5_SELECT_R {
1390 PB5_SELECT_R::new(((self.bits >> 20) & 0x0f) as u8)
1391 }
1392 #[doc = "Bits 24:27"]
1393 #[inline(always)]
1394 pub fn pb6_select(&self) -> PB6_SELECT_R {
1395 PB6_SELECT_R::new(((self.bits >> 24) & 0x0f) as u8)
1396 }
1397 #[doc = "Bits 28:31"]
1398 #[inline(always)]
1399 pub fn pb7_select(&self) -> PB7_SELECT_R {
1400 PB7_SELECT_R::new(((self.bits >> 28) & 0x0f) as u8)
1401 }
1402}
1403impl W {
1404 #[doc = "Bits 0:3"]
1405 #[inline(always)]
1406 #[must_use]
1407 pub fn pb0_select(&mut self) -> PB0_SELECT_W<PB_CFG0_SPEC> {
1408 PB0_SELECT_W::new(self, 0)
1409 }
1410 #[doc = "Bits 4:7"]
1411 #[inline(always)]
1412 #[must_use]
1413 pub fn pb1_select(&mut self) -> PB1_SELECT_W<PB_CFG0_SPEC> {
1414 PB1_SELECT_W::new(self, 4)
1415 }
1416 #[doc = "Bits 8:11"]
1417 #[inline(always)]
1418 #[must_use]
1419 pub fn pb2_select(&mut self) -> PB2_SELECT_W<PB_CFG0_SPEC> {
1420 PB2_SELECT_W::new(self, 8)
1421 }
1422 #[doc = "Bits 12:15"]
1423 #[inline(always)]
1424 #[must_use]
1425 pub fn pb3_select(&mut self) -> PB3_SELECT_W<PB_CFG0_SPEC> {
1426 PB3_SELECT_W::new(self, 12)
1427 }
1428 #[doc = "Bits 16:19"]
1429 #[inline(always)]
1430 #[must_use]
1431 pub fn pb4_select(&mut self) -> PB4_SELECT_W<PB_CFG0_SPEC> {
1432 PB4_SELECT_W::new(self, 16)
1433 }
1434 #[doc = "Bits 20:23"]
1435 #[inline(always)]
1436 #[must_use]
1437 pub fn pb5_select(&mut self) -> PB5_SELECT_W<PB_CFG0_SPEC> {
1438 PB5_SELECT_W::new(self, 20)
1439 }
1440 #[doc = "Bits 24:27"]
1441 #[inline(always)]
1442 #[must_use]
1443 pub fn pb6_select(&mut self) -> PB6_SELECT_W<PB_CFG0_SPEC> {
1444 PB6_SELECT_W::new(self, 24)
1445 }
1446 #[doc = "Bits 28:31"]
1447 #[inline(always)]
1448 #[must_use]
1449 pub fn pb7_select(&mut self) -> PB7_SELECT_W<PB_CFG0_SPEC> {
1450 PB7_SELECT_W::new(self, 28)
1451 }
1452 #[doc = r" Writes raw bits to the register."]
1453 #[doc = r""]
1454 #[doc = r" # Safety"]
1455 #[doc = r""]
1456 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
1457 #[inline(always)]
1458 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1459 self.bits = bits;
1460 self
1461 }
1462}
1463#[doc = "PB Configure Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pb_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pb_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1464pub struct PB_CFG0_SPEC;
1465impl crate::RegisterSpec for PB_CFG0_SPEC {
1466 type Ux = u32;
1467}
1468#[doc = "`read()` method returns [`pb_cfg0::R`](R) reader structure"]
1469impl crate::Readable for PB_CFG0_SPEC {}
1470#[doc = "`write(|w| ..)` method takes [`pb_cfg0::W`](W) writer structure"]
1471impl crate::Writable for PB_CFG0_SPEC {
1472 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
1473 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
1474}
1475#[doc = "`reset()` method sets pb_cfg0 to value 0"]
1476impl crate::Resettable for PB_CFG0_SPEC {
1477 const RESET_VALUE: Self::Ux = 0;
1478}