d1_pac/gpadc/
gp_fifo_intc.rs

1#[doc = "Register `gp_fifo_intc` reader"]
2pub type R = crate::R<GP_FIFO_INTC_SPEC>;
3#[doc = "Register `gp_fifo_intc` writer"]
4pub type W = crate::W<GP_FIFO_INTC_SPEC>;
5#[doc = "Field `fifo_flush` reader - ADC FIFO Flush\n\nWrite 1 to flush TX FIFO, clear automatically to 0."]
6pub type FIFO_FLUSH_R = crate::BitReader;
7#[doc = "Field `fifo_flush` writer - ADC FIFO Flush\n\nWrite 1 to flush TX FIFO, clear automatically to 0."]
8pub type FIFO_FLUSH_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `fifo_trig_level` reader - Interrupt trigger level for ADC\n\nTrigger Level = TXTL + 1"]
10pub type FIFO_TRIG_LEVEL_R = crate::FieldReader;
11#[doc = "Field `fifo_trig_level` writer - Interrupt trigger level for ADC\n\nTrigger Level = TXTL + 1"]
12pub type FIFO_TRIG_LEVEL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13#[doc = "Field `fifo_data_irq_en` reader - ADC FIFO Data Available IRQ Enable"]
14pub type FIFO_DATA_IRQ_EN_R = crate::BitReader<FIFO_DATA_IRQ_EN_A>;
15#[doc = "ADC FIFO Data Available IRQ Enable\n\nValue on reset: 0"]
16#[derive(Clone, Copy, Debug, PartialEq, Eq)]
17pub enum FIFO_DATA_IRQ_EN_A {
18    #[doc = "0: Disable"]
19    DISABLE = 0,
20    #[doc = "1: Enable"]
21    ENABLE = 1,
22}
23impl From<FIFO_DATA_IRQ_EN_A> for bool {
24    #[inline(always)]
25    fn from(variant: FIFO_DATA_IRQ_EN_A) -> Self {
26        variant as u8 != 0
27    }
28}
29impl FIFO_DATA_IRQ_EN_R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> FIFO_DATA_IRQ_EN_A {
33        match self.bits {
34            false => FIFO_DATA_IRQ_EN_A::DISABLE,
35            true => FIFO_DATA_IRQ_EN_A::ENABLE,
36        }
37    }
38    #[doc = "Disable"]
39    #[inline(always)]
40    pub fn is_disable(&self) -> bool {
41        *self == FIFO_DATA_IRQ_EN_A::DISABLE
42    }
43    #[doc = "Enable"]
44    #[inline(always)]
45    pub fn is_enable(&self) -> bool {
46        *self == FIFO_DATA_IRQ_EN_A::ENABLE
47    }
48}
49#[doc = "Field `fifo_data_irq_en` writer - ADC FIFO Data Available IRQ Enable"]
50pub type FIFO_DATA_IRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, FIFO_DATA_IRQ_EN_A>;
51impl<'a, REG> FIFO_DATA_IRQ_EN_W<'a, REG>
52where
53    REG: crate::Writable + crate::RegisterSpec,
54{
55    #[doc = "Disable"]
56    #[inline(always)]
57    pub fn disable(self) -> &'a mut crate::W<REG> {
58        self.variant(FIFO_DATA_IRQ_EN_A::DISABLE)
59    }
60    #[doc = "Enable"]
61    #[inline(always)]
62    pub fn enable(self) -> &'a mut crate::W<REG> {
63        self.variant(FIFO_DATA_IRQ_EN_A::ENABLE)
64    }
65}
66#[doc = "Field `fifo_overrun_irq_en` reader - ADC FIFO Overrun IRQ Enable"]
67pub type FIFO_OVERRUN_IRQ_EN_R = crate::BitReader<FIFO_OVERRUN_IRQ_EN_A>;
68#[doc = "ADC FIFO Overrun IRQ Enable\n\nValue on reset: 0"]
69#[derive(Clone, Copy, Debug, PartialEq, Eq)]
70pub enum FIFO_OVERRUN_IRQ_EN_A {
71    #[doc = "0: Disable"]
72    DISABLE = 0,
73    #[doc = "1: Enable"]
74    ENABLE = 1,
75}
76impl From<FIFO_OVERRUN_IRQ_EN_A> for bool {
77    #[inline(always)]
78    fn from(variant: FIFO_OVERRUN_IRQ_EN_A) -> Self {
79        variant as u8 != 0
80    }
81}
82impl FIFO_OVERRUN_IRQ_EN_R {
83    #[doc = "Get enumerated values variant"]
84    #[inline(always)]
85    pub const fn variant(&self) -> FIFO_OVERRUN_IRQ_EN_A {
86        match self.bits {
87            false => FIFO_OVERRUN_IRQ_EN_A::DISABLE,
88            true => FIFO_OVERRUN_IRQ_EN_A::ENABLE,
89        }
90    }
91    #[doc = "Disable"]
92    #[inline(always)]
93    pub fn is_disable(&self) -> bool {
94        *self == FIFO_OVERRUN_IRQ_EN_A::DISABLE
95    }
96    #[doc = "Enable"]
97    #[inline(always)]
98    pub fn is_enable(&self) -> bool {
99        *self == FIFO_OVERRUN_IRQ_EN_A::ENABLE
100    }
101}
102#[doc = "Field `fifo_overrun_irq_en` writer - ADC FIFO Overrun IRQ Enable"]
103pub type FIFO_OVERRUN_IRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, FIFO_OVERRUN_IRQ_EN_A>;
104impl<'a, REG> FIFO_OVERRUN_IRQ_EN_W<'a, REG>
105where
106    REG: crate::Writable + crate::RegisterSpec,
107{
108    #[doc = "Disable"]
109    #[inline(always)]
110    pub fn disable(self) -> &'a mut crate::W<REG> {
111        self.variant(FIFO_OVERRUN_IRQ_EN_A::DISABLE)
112    }
113    #[doc = "Enable"]
114    #[inline(always)]
115    pub fn enable(self) -> &'a mut crate::W<REG> {
116        self.variant(FIFO_OVERRUN_IRQ_EN_A::ENABLE)
117    }
118}
119#[doc = "Field `fifo_data_drq_en` reader - ADC FIFO Date DRQ Enable"]
120pub type FIFO_DATA_DRQ_EN_R = crate::BitReader<FIFO_DATA_DRQ_EN_A>;
121#[doc = "ADC FIFO Date DRQ Enable\n\nValue on reset: 0"]
122#[derive(Clone, Copy, Debug, PartialEq, Eq)]
123pub enum FIFO_DATA_DRQ_EN_A {
124    #[doc = "0: Disable"]
125    DISABLE = 0,
126    #[doc = "1: Enable"]
127    ENABLE = 1,
128}
129impl From<FIFO_DATA_DRQ_EN_A> for bool {
130    #[inline(always)]
131    fn from(variant: FIFO_DATA_DRQ_EN_A) -> Self {
132        variant as u8 != 0
133    }
134}
135impl FIFO_DATA_DRQ_EN_R {
136    #[doc = "Get enumerated values variant"]
137    #[inline(always)]
138    pub const fn variant(&self) -> FIFO_DATA_DRQ_EN_A {
139        match self.bits {
140            false => FIFO_DATA_DRQ_EN_A::DISABLE,
141            true => FIFO_DATA_DRQ_EN_A::ENABLE,
142        }
143    }
144    #[doc = "Disable"]
145    #[inline(always)]
146    pub fn is_disable(&self) -> bool {
147        *self == FIFO_DATA_DRQ_EN_A::DISABLE
148    }
149    #[doc = "Enable"]
150    #[inline(always)]
151    pub fn is_enable(&self) -> bool {
152        *self == FIFO_DATA_DRQ_EN_A::ENABLE
153    }
154}
155#[doc = "Field `fifo_data_drq_en` writer - ADC FIFO Date DRQ Enable"]
156pub type FIFO_DATA_DRQ_EN_W<'a, REG> = crate::BitWriter<'a, REG, FIFO_DATA_DRQ_EN_A>;
157impl<'a, REG> FIFO_DATA_DRQ_EN_W<'a, REG>
158where
159    REG: crate::Writable + crate::RegisterSpec,
160{
161    #[doc = "Disable"]
162    #[inline(always)]
163    pub fn disable(self) -> &'a mut crate::W<REG> {
164        self.variant(FIFO_DATA_DRQ_EN_A::DISABLE)
165    }
166    #[doc = "Enable"]
167    #[inline(always)]
168    pub fn enable(self) -> &'a mut crate::W<REG> {
169        self.variant(FIFO_DATA_DRQ_EN_A::ENABLE)
170    }
171}
172impl R {
173    #[doc = "Bit 4 - ADC FIFO Flush\n\nWrite 1 to flush TX FIFO, clear automatically to 0."]
174    #[inline(always)]
175    pub fn fifo_flush(&self) -> FIFO_FLUSH_R {
176        FIFO_FLUSH_R::new(((self.bits >> 4) & 1) != 0)
177    }
178    #[doc = "Bits 8:13 - Interrupt trigger level for ADC\n\nTrigger Level = TXTL + 1"]
179    #[inline(always)]
180    pub fn fifo_trig_level(&self) -> FIFO_TRIG_LEVEL_R {
181        FIFO_TRIG_LEVEL_R::new(((self.bits >> 8) & 0x3f) as u8)
182    }
183    #[doc = "Bit 16 - ADC FIFO Data Available IRQ Enable"]
184    #[inline(always)]
185    pub fn fifo_data_irq_en(&self) -> FIFO_DATA_IRQ_EN_R {
186        FIFO_DATA_IRQ_EN_R::new(((self.bits >> 16) & 1) != 0)
187    }
188    #[doc = "Bit 17 - ADC FIFO Overrun IRQ Enable"]
189    #[inline(always)]
190    pub fn fifo_overrun_irq_en(&self) -> FIFO_OVERRUN_IRQ_EN_R {
191        FIFO_OVERRUN_IRQ_EN_R::new(((self.bits >> 17) & 1) != 0)
192    }
193    #[doc = "Bit 18 - ADC FIFO Date DRQ Enable"]
194    #[inline(always)]
195    pub fn fifo_data_drq_en(&self) -> FIFO_DATA_DRQ_EN_R {
196        FIFO_DATA_DRQ_EN_R::new(((self.bits >> 18) & 1) != 0)
197    }
198}
199impl W {
200    #[doc = "Bit 4 - ADC FIFO Flush\n\nWrite 1 to flush TX FIFO, clear automatically to 0."]
201    #[inline(always)]
202    #[must_use]
203    pub fn fifo_flush(&mut self) -> FIFO_FLUSH_W<GP_FIFO_INTC_SPEC> {
204        FIFO_FLUSH_W::new(self, 4)
205    }
206    #[doc = "Bits 8:13 - Interrupt trigger level for ADC\n\nTrigger Level = TXTL + 1"]
207    #[inline(always)]
208    #[must_use]
209    pub fn fifo_trig_level(&mut self) -> FIFO_TRIG_LEVEL_W<GP_FIFO_INTC_SPEC> {
210        FIFO_TRIG_LEVEL_W::new(self, 8)
211    }
212    #[doc = "Bit 16 - ADC FIFO Data Available IRQ Enable"]
213    #[inline(always)]
214    #[must_use]
215    pub fn fifo_data_irq_en(&mut self) -> FIFO_DATA_IRQ_EN_W<GP_FIFO_INTC_SPEC> {
216        FIFO_DATA_IRQ_EN_W::new(self, 16)
217    }
218    #[doc = "Bit 17 - ADC FIFO Overrun IRQ Enable"]
219    #[inline(always)]
220    #[must_use]
221    pub fn fifo_overrun_irq_en(&mut self) -> FIFO_OVERRUN_IRQ_EN_W<GP_FIFO_INTC_SPEC> {
222        FIFO_OVERRUN_IRQ_EN_W::new(self, 17)
223    }
224    #[doc = "Bit 18 - ADC FIFO Date DRQ Enable"]
225    #[inline(always)]
226    #[must_use]
227    pub fn fifo_data_drq_en(&mut self) -> FIFO_DATA_DRQ_EN_W<GP_FIFO_INTC_SPEC> {
228        FIFO_DATA_DRQ_EN_W::new(self, 18)
229    }
230    #[doc = r" Writes raw bits to the register."]
231    #[doc = r""]
232    #[doc = r" # Safety"]
233    #[doc = r""]
234    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
235    #[inline(always)]
236    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
237        self.bits = bits;
238        self
239    }
240}
241#[doc = "GPADC FIFO Interrupt Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gp_fifo_intc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gp_fifo_intc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
242pub struct GP_FIFO_INTC_SPEC;
243impl crate::RegisterSpec for GP_FIFO_INTC_SPEC {
244    type Ux = u32;
245}
246#[doc = "`read()` method returns [`gp_fifo_intc::R`](R) reader structure"]
247impl crate::Readable for GP_FIFO_INTC_SPEC {}
248#[doc = "`write(|w| ..)` method takes [`gp_fifo_intc::W`](W) writer structure"]
249impl crate::Writable for GP_FIFO_INTC_SPEC {
250    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
251    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
252}
253#[doc = "`reset()` method sets gp_fifo_intc to value 0x1f00"]
254impl crate::Resettable for GP_FIFO_INTC_SPEC {
255    const RESET_VALUE: Self::Ux = 0x1f00;
256}
d1_pac/gpadc/gp_fifo_intc.rs

d1_pac/gpadc/
gp_fifo_intc.rs
